EDA 作业

EDA课堂作业

072092 20091003745 左国勇 7-5:

用于调用的LPM_ROM程序如下：

-- megafunction wizard: %ROM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram

-- ============================================================ -- File Name: data_rom.vhd -- Megafunction Name(s): -- altsyncram --

-- Simulation Library Files(s): -- altera_mf

-- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --

-- 9.0 Build 132 02/25/2009 SJ Full Version

-- ************************************************************

--Copyright (C) 1991-2009 Altera Corporation

--Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License

--Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf; USE altera_mf.all;

ENTITY data_rom IS

ARCHITECTURE SYN OF data_rom IS

SIGNAL sub_wire0

: STD_LOGIC_VECTOR (7 DOWNTO 0);

PORT ( );

address inclock q

: IN STD_LOGIC_VECTOR (5 DOWNTO 0); : IN STD_LOGIC ;

: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

END data_rom;

COMPONENT altsyncram

GENERIC ( address_aclr_a : STRING; init_file : STRING; intended_device_family : STRING;

lpm_hint lpm_type

: STRING; : STRING;

numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a widthad_a

: STRING; : NATURAL;

width_a : NATURAL; width_byteena_a : NATURAL

);

PORT (

clock0 : IN STD_LOGIC ;

address_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

);

END COMPONENT;

BEGIN q <= sub_wire0(7 DOWNTO 0);

altsyncram_component : altsyncram GENERIC MAP ( address_aclr_a => \ init_file => \ )

intended_device_family => \

lpm_hint => \lpm_type => \numwords_a => 64, operation_mode => \outdata_aclr_a => \outdata_reg_a => \widthad_a => 6, width_a => 8, width_byteena_a => 1

PORT MAP ( clock0 => inclock, address_a => address, q_a => sub_wire0 );

END SYN;

-- ============================================================ -- CNX file retrieval info

-- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC \-- Retrieval info: PRIVATE: AclrAddr NUMERIC \-- Retrieval info: PRIVATE: AclrByte NUMERIC \-- Retrieval info: PRIVATE: AclrOutput NUMERIC \-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC \-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC \-- Retrieval info: PRIVATE: BlankMemory NUMERIC \

-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC \-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC \-- Retrieval info: PRIVATE: Clken NUMERIC \

-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC \

-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING \-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC \

-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING \-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC \

-- Retrieval info: PRIVATE: JTAG_ID STRING \

-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC \

-- Retrieval info: PRIVATE: MIFfilename STRING \-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC \-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC \-- Retrieval info: PRIVATE: RegAddr NUMERIC \-- Retrieval info: PRIVATE: RegOutput NUMERIC \

-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING \-- Retrieval info: PRIVATE: SingleClock NUMERIC \-- Retrieval info: PRIVATE: UseDQRAM NUMERIC \-- Retrieval info: PRIVATE: WidthAddr NUMERIC \-- Retrieval info: PRIVATE: WidthData NUMERIC \

-- Retrieval info: PRIVATE: rden NUMERIC \

-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING \

-- Retrieval info: CONSTANT: INIT_FILE STRING \

-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING \-- Retrieval info: CONSTANT: LPM_HINT \

-- Retrieval info: CONSTANT: LPM_TYPE STRING \-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC \

-- Retrieval info: CONSTANT: OPERATION_MODE STRING \

-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING \

-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING \-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC \-- Retrieval info: CONSTANT: WIDTH_A NUMERIC \

-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC \

-- Retrieval info: USED_PORT: address 0 0 6 0 INPUT NODEFVAL address[5..0] -- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] -- Retrieval info: CONNECT: @address_a 0 0 6 0 address 0 0 6 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0

-- Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0

-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL data_rom.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL data_rom.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL data_rom.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL data_rom.bsf FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL data_rom_inst.vhd FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL data_rom_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL data_rom_wave*.jpg FALSE -- Retrieval info: LIB_FILE: altera_mf

STRING

顶层程序设计如下： LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SINGT IS

PORT( CLK: IN STD_LOGIC;

DOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END SINGT;

ARCHITECTURE DACC OF SINGT IS COMPONENT data_rom

PORT ( address: IN STD_LOGIC_VECTOR (5 DOWNTO 0); inclock: IN STD_LOGIC;

q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END COMPONENT;

SIGNAL Q1:STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN

PROCESS(CLK) BEGIN

IF CLK'EVENT AND CLK='1' THEN Q1<=Q1+1; END IF; END PROCESS;

u1:data_rom PORT MAP (address=>Q1,q=>DOUT,inclock=>CLK); END;

其RTL电路图如下：

仿真波形如下

SignalTapII数据窗的实时信号图形如下：

7-2实验与设计： 测频控制程序如下:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FTCTRL IS

PORT ( CLKK: IN STD_LOGIC; CNT_EN: OUT STD_LOGIC; RST_CNT: OUT STD_LOGIC; Load: OUT STD_LOGIC); END FTCTRL;

ARCHITECTURE behav OF FTCTRL IS SIGNAL Div2CLK : STD_LOGIC; BEGIN

PROCESS (CLKK)

BEGIN

IF CLKK'EVENT AND CLKK='1' THEN Div2CLK<=NOT Div2CLK; END IF; END PROCESS;

PROCESS (CLKK,Div2CLK)

BEGIN

IF CLKK='0' AND Div2CLK='0' THEN RST_CNT<='1'; ELSE RST_CNT<='0'; END IF; END PROCESS;

Load <= NOT Div2CLK; CNT_EN<=Div2CLK; END behav;

其RTL电路图如下;

其工作时序如下：

32位计数器程序如下：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER32B IS

PORT( FIN: IN STD_LOGIC;

CLR: IN STD_LOGIC; ENABL: IN STD_LOGIC;

DOUT: OUT STD_LOGIC_VECTOR(31 DOWNTO 0));

END COUNTER32B;

ARCHITECTURE behav OF COUNTER32B IS

SIGNAL CQI: STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN

PROCESS(FIN, CLR,ENABL)

BEGIN

IF CLR='1' THEN CQI<=(OTHERS=>'0'); ELSIF FIN'EVENT AND FIN='1' THEN IF ENABL='1' THEN CQI<=CQI+1; END IF; END IF; END PROCESS; DOUT<=CQI; END behav;

其RTL电路图如下：

32位锁存器程序如下： 其RTL电路图如下：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG32B IS

PORT ( LK:IN STD_LOGIC;

DIN: IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END REG32B;

ARCHITECTURE behav OF REG32B IS BEGIN

PROCESS (LK,DIN) BEGIN

IF LK'EVENT AND LK='1' THEN DOUT<=DIN;

END IF; END PROCESS; END behav;

RTL电路如下：

8位16进制频率计顶层文件程序如下：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY FREQTEST IS

PORT ( CLK1HZ: IN STD_LOGIC; FSIN: IN STD_LOGIC;

DOUT: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END FREQTEST;

ARCHITECTURE struc OF FREQTEST IS COMPONENT FTCTRL

PORT ( CLKK: IN STD_LOGIC; CNT_EN: OUT STD_LOGIC; RST_CNT: OUT STD_LOGIC; Load: OUT STD_LOGIC); END COMPONENT;

COMPONENT COUNTER32B

PORT ( FIN: IN STD_LOGIC; CLR: IN STD_LOGIC; ENABL: IN STD_LOGIC;

DOUT: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT;

COMPONENT REG32B

PORT ( LK: IN STD_LOGIC;

DIN: IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT;

SIGNAL TSTEN1: STD_LOGIC;

SIGNAL CLR_CNT1: STD_LOGIC; SIGNAL Load1: STD_LOGIC;

SIGNAL DTO1: STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL CARRY_OUT1: STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN U1:

FTCTRL

PORT

MAP

(CLKK=>CLK1HZ,CNT_EN=>TSTEN1,RST_CNT=>CLR_CNT1,Load=>Load1); U2: REG32B PORT MAP (LK=>Load1,DIN=>DTO1,DOUT=>DOUT);

U3: COUNTER32B PORT MAP (FIN=>FSIN,CLR=>CLR_CNT1,ENABL=>TSTEN1,DOUT=>DTO1); END struc;

其RTL电路图如下：

其控制时序如下：

8-3:

该状态机为mealy型有限状态机。

程序如下：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY SCHK IS

PORT( DIN,CLK,CLR:IN STD_LOGIC;

AB: OUT STD_LOGIC_VECTOR( 3 DOWNTO 0)); END SCHK;

ARCHITECTURE behav OF SCHK IS SIGNAL Q:INTEGER RANGE 0 TO 8;

SIGNAL D:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN

D<=\

PROCESS(CLK,CLR) BEGIN

IF CLR='1' THEN Q<=0;

ELSIF CLK'EVENT AND CLK='1' THEN CASE Q IS

WHEN 0=> IF DIN=D(7) THEN Q<=1;ELSE Q<=0;END IF; WHEN 1=> IF DIN=D(6) THEN Q<=2;ELSE Q<=0;END IF; WHEN 2=> IF DIN=D(5) THEN Q<=3;ELSE Q<=0;END IF; WHEN 3=> IF DIN=D(4) THEN Q<=4;ELSE Q<=0;END IF; WHEN 4=> IF DIN=D(3) THEN Q<=5;ELSE Q<=0;END IF; WHEN 5=> IF DIN=D(2) THEN Q<=6;ELSE Q<=0;END IF; WHEN 6=> IF DIN=D(1) THEN Q<=7;ELSE Q<=0;END IF; WHEN 7=> IF DIN=D(0) THEN Q<=8;ELSE Q<=0;END IF; WHEN OTHERS => Q<=0; END CASE; END IF; END PROCESS; PROCESS(Q) BEGIN

IF Q=8 THEN AB<=\ ELSE AB<=\ END IF;

END PROCESS; END behav;

其RTL电路图如下;

时序仿真：

因为给定的DIN序列中与预赋值有所不同，故显示1011. 该程序无状态机。（ design has no state machine）

实验与设计8_3：

用LPM_RAM调出程序如下：

LIBRARY ieee;

USE ieee.std_logic_1164.all; LIBRARY altera_mf;

USE altera_mf.all; ENTITY RAM8B IS PORT ( address ); END RAM8B;

ARCHITECTURE SYN OF ram8b IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( address_aclr_a

: STRING;

clock data wren q

: IN STD_LOGIC_VECTOR (7 DOWNTO 0); : IN STD_LOGIC ;

: IN STD_LOGIC_VECTOR (7 DOWNTO 0);

: IN STD_LOGIC ;

: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

indata_aclr_a : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type numwords_a

: STRING; : NATURAL;

operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; widthad_a width_a

: NATURAL; : NATURAL;

: NATURAL; : STRING

width_byteena_a wrcontrol_aclr_a );

PORT ( wren_a : IN STD_LOGIC ; );

END COMPONENT; BEGIN

q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_aclr_a => \ indata_aclr_a => \

clock0 : IN STD_LOGIC ;

address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0)

intended_device_family => \lpm_hint => \lpm_type => \numwords_a => 256,

operation_mode => \outdata_aclr_a => \outdata_reg_a => \

power_up_uninitialized => \widthad_a => 8, width_a => 8,

width_byteena_a => 1, wrcontrol_aclr_a => \

)

PORT MAP (

wren_a => wren, clock0 => clock, address_a => address, data_a => data, q_a => sub_wire0

);

END SYN;

元件ADCINT的程序如下：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY ADCINT IS

PORT(D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --来自0809转换好的8位数据 CLK : IN STD_LOGIC; --状态机工作时钟

EOC : IN STD_LOGIC; --转换状态指示，低电平表示正在转换 ALE : OUT STD_LOGIC; --8个模拟信号通道地址锁存信号 START : OUT STD_LOGIC; --转换开始信号

OE : OUT STD_LOGIC; --数据输出3态控制信号 ADDA : OUT STD_LOGIC; --信号通道最低位控制信号 LOCK0 : OUT STD_LOGIC; --观察数据锁存时钟 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --8位数据输出 END ADCINT;

ARCHITECTURE behav OF ADCINT IS

TYPE states IS (st0, st1, st2, st3,st4) ; --定义各状态子类型 SIGNAL current_state, next_state: states :=st0 ;

SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL LOCK : STD_LOGIC; -- 转换后数据输出锁存时钟信号

BEGIN

ADDA <= '1';--当ADDA<='0'，模拟信号进入通道IN0；当ADDA<='1'，则进入通道IN1 Q <= REGL; LOCK0 <= LOCK ;

COM: PROCESS(current_state,EOC) BEGIN --规定各状态转换方式

CASE current_state IS

WHEN st0=>ALE<='0';START<='0';LOCK<='0';OE<='0'; next_state <= st1; --0809初始化

WHEN st1=>ALE<='1';START<='1';LOCK<='0';OE<='0'; next_state <= st2; --启动采样

WHEN st2=> ALE<='0';START<='0';LOCK<='0';OE<='0';

IF (EOC='1') THEN next_state <= st3; --EOC=1表明转换结束 ELSE next_state <= st2; END IF ; --转换未结束，继续等待

WHEN st3=> ALE<='0';START<='0';LOCK<='0';OE<='1'; next_state <= st4;--开启OE,输出转换好的数据

WHEN st4=> ALE<='0';START<='0';LOCK<='1';OE<='1'; next_state <= st0; WHEN OTHERS => next_state <= st0; END CASE ;

END PROCESS COM ;

REG: PROCESS (CLK)

BEGIN

IF (CLK'EVENT AND CLK='1') THEN current_state<=next_state; END IF;

END PROCESS REG ; -- 由信号current_state将当前状态值带出此进程:REG LATCH1: PROCESS (LOCK) -- 此进程中，在LOCK的上升沿，将转换好的数据锁入 BEGIN

IF LOCK='1' AND LOCK'EVENT THEN REGL <= D ; END IF; END PROCESS LATCH1 ; END behav;

元件CINT10B的程序如下：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10B IS

PORT (LOCK0,CLR : IN STD_LOGIC; CLK : IN STD_LOGIC;

WE : IN STD_LOGIC;

DOUT : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); CLKOUT : OUT STD_LOGIC ); END CNT10B;

ARCHITECTURE behav OF CNT10B IS

SIGNAL CQI : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL CLK0 : STD_LOGIC; BEGIN

CLK0 <= LOCK0 WHEN WE='1' ELSE CLK;

PROCESS(CLK0,CLR,CQI) BEGIN

IF CLR = '1' THEN CQI <= \

ELSIF CLK0'EVENT AND CLK0 = '1' THEN CQI <= CQI + 1; END IF; END PROCESS;

DOUT <= CQI; CLKOUT <= CLK0; END behav;

ADC0809采样电路系统RSV.bdf图如下：

波形仿真如下：

9-15：

用两种方法设计8位比较器，比较器的输入是两个待比较的8位数A=[A7..A0]和B=[B7..B0],输出是D、E、F。当A=B时D=1;当A>B时E=1；当A

比较值的大小。对两种设计方案的资源耗用情况进行比较，并给以解释。 第一种设计方案： VHDL描述： library ieee;

use ieee.std_logic_1164.all; entity comp is

generic (x:integer:=8);

port(A,B:in std_logic_vector(0 to x-1); D,E,F:out std_logic); end ;

architecture a of comp is begin

process(A,B) begin

if A>B then E<='1'; else E<='0'; end if;

if A=B then D<='1'; else D<='0'; end if;

if A

end process; end; RTL：

第二种设计方案： VHDL描述： LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; ENTITY comp2 IS

port( A,B : in std_logic_vector(7 downto 0); D,E,F: out std_logic ); END ;

ARCHITECTURE hdlarch OF comp2 IS signal tmp : std_logic_vector(8 downto 0); signal t : std_logic; BEGIN

tmp <= ('0'&A)-('0'&B);

t <= '1' when tmp = 0 else '0';

D <= t;E <= (not tmp(8)) and (not t); F<= tmp(8) and (not t); RTL：

波形仿真：

分析：当A

实验与设计9-3：

（3）实验内容1：编译以上文件，给出仿真波形。

仿真波形：

10-5 ：

下述VHDL代码的综合结果会有几个触发器或锁存器？

程序1有两个2触发器，程序2有一个触发器，程序3有1个锁存器。

10-6 ：比较CASE语句与WITH_SELECT语句，叙述它们的异同点。

答：case是条件选择语句,必须在进程里面才可以;

WITH_SELECT是并行分支语句不可以在进程里面使用. 相同点就是全部是根据条件选择执行的语句

实验与设计：

10-1（6）实验内容4：设计一个纯组合电路的8*8等于16位的乘法器和一个LPM

乘法器（选择不同的流水线方式），具体说明并比较这两种乘法器的逻辑资源占用情况和运行速度情况。 纯组合电路乘法器设计： VHDL描述：

LIBRARY IEEE; --测频控制 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ftctrl IS

PORT ( CLKK : IN STD_LOGIC; -- 1Hz CNT_EN,RST_CNT,LOAD : OUT STD_LOGIC); END ftctrl;

ARCHITECTURE behav OF ftctrl IS SIGNAL DIV2CLK : STD_LOGIC; BEGIN

PROCESS( CLKK )

BEGIN

IF CLKK'EVENT AND CLKK = '1' THEN DIV2CLK <= NOT DIV2CLK; END IF;

END PROCESS;

PROCESS (CLKK, DIV2CLK)

BEGIN

IF CLKK='0' AND Div2CLK='0' THEN RST_CNT <= '1'; ELSE RST_CNT <= '0'; END IF; END PROCESS;

LOAD <= NOT DIV2CLK ; CNT_EN <= DIV2CLK; END behav;

LIBRARY IEEE; --32位锁存器 USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG32B IS

PORT ( LK : IN STD_LOGIC; DIN :

IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT :

OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END REG32B;

ARCHITECTURE behav OF REG32B IS BEGIN

PROCESS(LK, DIN) BEGIN

IF LK'EVENT AND LK = '1' THEN DOUT <= DIN; --时钟到来时，锁存输入数据

END IF; END PROCESS; END behav;

LIBRARY IEEE; --32位计数器 USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY counter32b IS

PORT ( ENABL,CLR,FIN : IN STD_LOGIC;

DOUT: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END counter32b;

ARCHITECTURE behav OF counter32b IS

SIGNAL CQI : STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN

PROCESS( ENABL,CLR,FIN ) BEGIN

IF CLR='1' THEN CQI <= (OTHERS=>'0'); --清零 ELSIF FIN'EVENT AND FIN='1' THEN IF ENABL='1' THEN CQI<= CQI + 1; END IF; END IF;

END PROCESS; DOUT <= CQI; END behav;

library ieee;

use ieee.std_logic_1164.all; entity preqtest is

port(clk1hz:in std_logic; fsin:in std_logic;

dout:out std_logic_vector(31 downto 0)); end preqtest;

architecture struc of preqtest is component ftctrl

port(clkk:in std_logic; cnt_en:out std_logic; rst_cnt:out std_logic; load:out std_logic); end component;

component counter32b

port(fin:in std_logic;

clr:in std_logic; enabl:in std_logic;

dout:out std_logic_vector(31 downto 0)); end component;

component reg32b

port(lk:in std_logic;

din:in std_logic_vector(31 downto 0); dout:out std_logic_vector(31 downto 0)); end component;

signal tsten1:std_logic; signal clr_cnt1:std_logic;

signal load1:std_logic;

signal dt01:std_logic_vector(31 downto 0); signal carry_out1:std_logic_vector(6 downto 0); begin

u1: ftctrl port map(clkk=>clk1hz,cnt_en=>tsten1, rst_cnt=>clr_cnt1,load=>load1); u2:reg32b port map(lk=>load1,din=>dt01,dout=>dout); u3:counter32b port map(fin=>fsin,clr=>clr_cnt1, enabl=>tsten1,dout=>dt01); end struc;

其RTL电路图如下：

LPM乘法器设计

VHDL描述： LIBRARY ieee;

USE ieee.std_logic_1164.all; LIBRARY work;

ENTITY lpm_mult_0 IS PORT

(a : IN STD_LOGIC_VECTOR(7 DOWNTO 0); b : IN STD_LOGIC_VECTOR(7 DOWNTO 0); r : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)

);

END lpm_mult_0

ARCHITECTURE bdf_type OF lpm_mult_0 IS COMPONENT lpm_mult0 PORT(dataa : IN STD_LOGIC_VECTOR(7 DOWNTO 0); datab : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) );

END COMPONENT; BEGIN

b2v_inst : lpm_mult0 PORT MAP(dataa => a, datab => b, result => r); END bdf_type;

LPM乘法器原理图及引脚指定：

其RTL电路图如下：

仿真波形如下：

两种乘法器的逻辑资源占用情况和运行速度情况对比分析：

由编译报告得出, LPM乘法器使用逻辑资源较少，且运行速度较快。