CRC8 - verilog

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: //

// Create Date: 15:40:57 09/17/09 // Design Name:

// Module Name: crc8 // Project Name: // Target Device: // Tool versions: // Description: //

// Dependencies: //

// Revision:

// Revision 0.01 - File Created // Additional Comments: //

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module crc8(reset,clk,start,data_in,out_rs,crc_code); parameter width=32; //信息位宽 input reset; input clk;

input [width-1:0] data_in; input start;

output [7:0] out_rs;

output [width+7:0] crc_code;

reg [5:0] cnt;

reg [width+7:0] dat_reg;

wire [width+7:0] crc_enc; wire [width+7:0] reg_tem;

reg crc_16bit_end; reg [width+7:0] tmp; reg [width-1:0] cd;

always @(posedge clk or negedge reset) begin

if(!reset) begin cnt <= 0; end else if(start) begin cnt <= 0; end else if(cnt==34) begin cnt <= 34; end else begin cnt <= cnt + 1'b1; end end

always @(posedge clk or negedge reset) begin if(!reset) begin dat_reg <= 0; end else if(start) begin dat_reg <= {data_in,8'h00}; end else if(cnt>0 && cnt <33) begin dat_reg <= crc_enc; end end

always @(posedge clk or negedge reset) begin if(!reset) begin crc_16bit_end <= 0; end else if(cnt == 33) begin crc_16bit_end <= 0; end else begin crc_16bit_end <= 1; end end

always @(posedge clk or negedge reset) begin if(!reset) begin

tmp <= 0; end else if(cnt==32) begin tmp <= reg_tem; end end

always @(posedge clk or negedge reset) begin if(!reset) begin cd <= 0; end else if(start) begin cd <= data_in; end end

assign reg_tem = (cnt>0) ? {dat_reg[width+6:0],1'b0} : dat_reg;

assign crc_enc[width+7] = (reg_tem[width+7]==1) ? ~reg_tem[width+7] : reg_tem[width+7]; assign crc_enc[width+7-1:width] = reg_tem[width+7-1:width];

assign crc_enc[width-1] = (reg_tem[width+7]==1) ? ~reg_tem[width-1] : reg_tem[width-1];

assign crc_enc[width-2:0] = reg_tem[width-2:0];

//always @(posedge clk or negedge reset) begin // if(!reset) begin // out_rs <= 0; // end // else if(!crc_16bit_end) begin // out_rs <= crc_reg; // end //end

assign out_rs = (~crc_16bit_end) ? tmp[width+7:32] : 0;

assign crc_code = (~crc_16bit_end) ? {cd,tmp[width+7:32]} : 0;

endmodule

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