The Definition of a VHDL-AMS Subset for Behavioral Synthesis of Analog Systems

This paper defines a VHDL-AMS subset for behavioral synthesis of analog systems. The subset includes language constructs for describing most of the functional aspects pertaining to analog systems. Besides, these constructs can be implemented with electroni

The De nition of a VHDL-AMS Subset for Behavioral Synthesis of Analog SystemsAlex Doboli and Ranga Vemurifadoboli,rangag@ececs.uc.edu

Department of ECECS University of Cincinnati Cincinnati, OH, 45221-0030

This paper de nes a VHDL-AMS subset for behavioral synthesis of analog systems. The subset includes language constructs for describing most of the functional aspects pertaining to analog systems. Besides, these constructs can be implemented with electronic circuits. Functional aspects, which can be expressed with the subset, relate to two interacting parts. The analog part continuously processes analog signals, while the control part generates control signals for conguring the ow of signals in the analog part. However, some language constructs have to be constrained or augmented, so that they become e ective for synthesis. To motivate that constructs in the subset can be synthesized, we present, by means of an example, how VHDL-AMS programs are compiled into an intermediate format. The intermediate format can be either directly mapped to components from a component library, or used for further synthesis-related optimization steps. Finally, we discuss a complete experiment for specifying of functionality, compiling the speci cation, and its mapping to electronic components.

Abstract

The design of analog electronic systems is a very di cult task mainly because of complex constraints to be satis ed by the nal product, and the high sensitivity of analog characteristics to outer-world perturbations. Nevertheless, the consumer's market o ers a growing demand for analog and mixed analog-digital electronic systems. Previous research developed very e ective computer-aided design (CAD) tools for automated design of digital systems 6]. However, while analog parts represent only 10% of a system functionality, they require 90% of the development time. Evidently, more recently, research has been focused on developing e ective tools for automated synthesis of analog circuits 8] 10] 15] and systems 3]. Automated analog synthesis starts with input speci cations for the system functionality and performance constraints, and automatically produces aThis work was sponsored by the USAF, Wright Laboratories, Wright Patterson Air Force Base under contract number F33615-96-C-1911

1 Introduction

high-quality implementation. A typical behavioralsynthesis ow includes four design tasks. First, the system functionality (behavior) is described by using a speci cation language. Next, architectural synthesis and component selection pick a set of electronic components from a prede ned library of component topologies, and explore which of their interconnections result in functionally correct implementations. Finally, the sizing step calculates physical dimensions (width, length) for the transistors of the picked components, so that existing design constraints are satised. Previous research on analog synthesis assumes a known circuit or system topology, and exclusively c

oncentrates on the issue of using performance attributes for guiding the synthesis task. We believe that the absence of more substantial work on specifying analog functionality is mainly because of the lack of a standard speci cation language. Recently, Very High Speed Integrated Circuits Description Language for Analog Mixed Systems (VHDL-AMS) 1] emerged as a standard for speci cation of mixed analog-digital systems. In this paper, we will de ne a subset of the VHDLAMS language, and indicate how this subset is used for automated system synthesis. We will motivate what language constructs are necessary, so that virtually all functional aspects of a system can be described. Besides, these constructs must be implementable as electronic circuits. By analyzing a meaningful number of real-life examples, we have identi ed that analog systems can be modeled as consisting of two interacting parts. The analog part has di erent modes of functioning, and it performs all (signal) processing dened by the functionality. The control part generates signals for selecting the current functioning mode of the analog part. Our VHDL-AMS subset can describe any functional aspect pertaining to the analog or control parts. Nevertheless, being oriented towards simulation, some of the language constructs can not be synthesized, unless restrictions are imposed. Moreover, we believe that VHDL-AMS can not describe some speci c system characteristics, i.e. low/high input/output impedance, but which are crucial for synthesis. In this paper, we present our language constraints/extensions for synthesis. Finally, by using an example, we show how our VHDL-AMS subset is com-

This paper defines a VHDL-AMS subset for behavioral synthesis of analog systems. The subset includes language constructs for describing most of the functional aspects pertaining to analog systems. Besides, these constructs can be implemented with electroni

Control SignalsEvents fromfrom external environmentexternal environment

Analog System

Analog PartEvent 2Control Part

if (Event1) then x := 0.0;elsif (Event2) then x := -5.0;AnalogInputSignalsAnalogComponentInternal EventsInternalControl Signalsoutput signal == k * Event 1integral of xControlComponent

Continous output signal

a)AnalogOutput Signalsb)

This paper defines a VHDL-AMS subset for behavioral synthesis of analog systems. The subset includes language constructs for describing most of the functional aspects pertaining to analog systems. Besides, these constructs can be implemented with electroni

Example Function Generator Iter.Equat. Solver Temperature Controller Dual-slope A/D converter Missile Solver Telephone Set Power Meter Rimoldi Diversity Receiver Massey Diversity Receiver Example 1 Example 2

Analog Part yes yes yes yes yes yes yes yes yes yes yes

Control Part yes yes yes yes no yes yes yes yes yes yes

Events outside intern no yes no yes no yes yes yes yes yes yes no yes yes yes yes yes yes no yes yes yes

Control signals outside intern no yes yes no no yes yes no no no no yes no yes no yes no no no yes yes yes

time yes yes yes yes yes yes yes yes yes yes no

Model in frequency no no no no no no no no no yes yes

Table 1: The e ectiveness of the behavioral model for real-life examples continuous-time processing of signals. The control of the analog part to a new mode of functioning. part has an event-driven behavior, and it generates This shift is performed by the control component, signals for selecting among di erent modes. We show which recognizes these events, and produces the the e ectiveness of our model by presenting the rerequired control signals. sults of 11 case studies, that we conducted. We used The control part produces control signals for this model for selecting the language constructs in our changing the mode of behavior for the analog subset. part. For illustrating the model, we rely on the examThe main advantage of this model is that it di erenple of a ramp-signal generator, also because it was altiates the essentially distinct parts of a system (with ready used by another analog-synthesis related work respect to their functionality and performance charac9]. The model of the ramp-signal generator consists teristics), and which will go through di erent syntheof two functional parts, which are depicted in Figure sis steps, in our synthesis environment. Besides, the 1a. The analog part continuously integrates a conmodel can be naturally extended for describing also stant input signal x. It has two modes of functioning. mixed-signal systems. In the rst mode, it continuously integrates starting For emphasizing the e ectiveness of the suggested from the value of 0.0 to the upper limit of 5.0, while in model, we considered 10 o

ther real-life systems, bethe second mode, it integrates with a negative factor sides the ramp signal-generator. These examples were of -5.0 until the lower value of 0.0 is reached. Exceedselected so that they represent essentially di erent ing the threshold values of 0.0 or 5.0 represent events, processing aspects. Temperature Controller 2] is a and are denoted in Figure 1a as Event1 and Event2. control system for preserving temperature in a predeThe two events are addressed to the control part. Dened range. The names of Telephone Set 18], Power pending on the type of the event, the control part will Meter 7], Iterative Equation Solver 21], Di erential produce the appropriate control signals for switchsolver for a missile guider 11] are self-explanatory for ing the analog part to a new mode of functioning. their functionality. Dual-slope A/D converter 5] is By generalizing the previous example, we suggest an analog to digital converter, Rimoldy Diversity Rethat an analog system consists of two interacting ceiver 16] and Massey's Diversity Receiver 16] are parts, as it is depicted in Figure 1b: modulation schemes used in telecommunication. We The analog part performs continuous-time inalso developed two arti cial examples for some missformation processing according to multiple modes ing functional aspects, and which are indicated by the of functioning. This part is described functionally generic names Example1 and Example 2. (behaviorally) by using sets of di erential and alTable 1 presents the e ectiveness of our analoggebraic equations (DAE), transfer functions, or system model for representing the suggested examples. algorithmically, by indicating the signal ow and All examples include an analog part, and all, but one, computation algorithm they perform. have also a control part (thus, all, but one, have anaThe control part has an event-driven behavior, log parts with multiple modes of functioning). Events and produces control signals for the analog part. for the control part and control signals for the analog This part does not perform any signal processing, part are produced either inside or outside the analog but instead, it generates control signals for selectsystem. The functionality of all real-life examples is ing among the modes of analog functioning. The expressed in time, although behavior in frequency is existence of this component is justi ed for analog also very common for analog systems 5]. The addisystems with multiple modes of behavior. As a by-product of the processing in the analog tional examples that we will develop address the issue part, events can happen, that determine the shift of functionality in frequency.

This paper defines a VHDL-AMS subset for behavioral synthesis of analog systems. The subset includes language constructs for describing most of the functional aspects pertaining to analog systems. Besides, these constructs can be implemented with electroni

The behavioral model points to some of the basic language constructs of any synthesis-oriented subset. A subset should include language constructs for describing the functional aspects pertaining to the analog and control parts, and their interactions. In the next section, we discuss our VHDL-AMS subset for synth

esis.

4 VHDL-AMS Subset for Analog System Synthesis

This section concentrates on describing VASS (VHDL-AMS Subset for Synthesis), our subset for synthesis. When de ning the subset, we targeted two distinct objectives. First, the subset must include all language constructs, which are required for expressing the functional aspects of an analog system. According to our behavioral model, VASS has constructs, that describe the functionality of the analog and control parts, and their interactions. Second, it should be possible to implement the subset constructs with electronic circuits. For each construct, we developed transformation rules, that convert it into a structural signal- ow representation. This representation can be directly mapped to components from a library 4], or used for the next synthesis steps. These transformation rules were embedded into a compiler for the VASS set. Being oriented towards simulation, VHDL-AMS has to be partially"adjusted", so that it can be e ectively used for synthesis. The adaption involves both restricting some of the language constructs, and augmenting the language with missing synthesis-oriented constructs. The necessity of restricting language constructs is exempli ed by the use of a for instruction inside a procedural statement. Its semantics is de ned in terms of a discrete counter, but which is di cult to be realized in a signal- ow structure. Instead, we impose that the number of iterations, for each for instruction, is statically known, so that its body can be unrolled for that number of times. Second, it is very common, that a system terminal must have a very low output impedance because of its external connections. This system characteristic can be achieved by synthesizing a speci c output stage, but which can not be inferred, unless it is accordingly indicated (i.e. through annotations) in the speci cation. The overall structure of an VASS program consists of entity declarations, architecture bodies, package declarations, and package bodies. In the rest of this section, we present the main language constructs in our subset, the constraints we impose for their synthesis, and their translation into a structural signal- ow graph. We also discuss our synthesis-related annotations, by which we augment a speci cation. Translation rules and the mapping to library components are illustrated by an example, in Section 5. An entity declarations de nes the interface of a system with its external environment. In VASS, we accept signal 1, quantity, and terminal ports. Ter-

1 To distinguish VHDL-AMS signals from physical signals, we will indicate the rst in italics.

minal ports describe the structural interconnection of a system with its external environment. Still, we impose that, for each terminal port, only one of its through (current) or across (voltage) quantities is used in the description. This accommodates the rest of the speci cation, in which only one of the facets (current/voltage) of an analog signa

l is utilized. According to our behavioral model, the architectural body of an VASS program indicates the continuous-time behavior of the analog part, the event-driven behavior of the control part, and their interactions. The system functionality is expressed as relationships and computations on free quantities and on signal objects. Quantities de ne signals with a continuous-time behavior, and signals those with an event-driven behavior. VASS admits only quantities of nature type ( oating-point or a composite type with elements of nature type), as they naturally represent analog signals. Signals are of nature or bitvector types. Quantities can be composite (array or record type), but array quantities are indexed only by signals of bit-vector types. This accommodates well our model, where all non-analog computations are performed inside the control part. Continuous-time behavior can be formulated in an implicit or explicit manner. In the implicit way, the behavior results from solving a set of di erential and algebraic equations (DAEs). The explicit method denes the functionality either as a transfer functions or an algorithmic way, in which the ow of signals is indicated. Our subset supports both description styles. VASS accepts unrestricted DAE de nitions as simple simultaneous and simultaneous if/case statements. Simultaneous statements can not be uniquely mapped into a signal- ow structure, as a set of distinct"solvers" correspond to each DAE set. Our synthesis environment considers all topologies that"solve" a DAE set, while searching for the best implementation. More challenging for the subset de nition is the explicit speci cation of continuous-time behavior by using procedural statements (procedurals). VASS accepts restricted de nitions of procedurals, so that they can be translated into a realistic signal- ow path: Procedurals are described as a sequence of instructions, which refer to quantities, signals or variables. We infer the signal- ow path from the way in which quantities are assigned/referred by instructions (their data-dependencies), without considering any information about instruction sequencing. However, we interpret sequencing as a"redundant" information for verifying the correctness of a speci cation. Thus, in a sequence, a reference to a quantity must always be after an assignment to that quantity. Besides, due to their global nature, quantities are assigned at most once, and by only one procedural, in the speci cation. The simulation semantics of while loops can be preserved after synthesis, only if constraints are speci ed on their input (referred inside the loop) and output signals (assigned inside the loop). We impose that inputs for a loop change slower than

This paper defines a VHDL-AMS subset for behavioral synthesis of analog systems. The subset includes language constructs for describing most of the functional aspects pertaining to analog systems. Besides, these constructs can be implemented with electroni

required as the simulation cycle assumes that a loop is always executed in zero time steps, while in reality, a delay of Tmax time units can occur. Under these restrictions, a while loop describes a sampling functionality: input signals are constant while th

e loop body executes, and the produced structure is fast enough to implement the described behavior. subroutine calls are a powerful mechanism for sharing of functionality. Nevertheless, for continuous-time procedurals, functionality sharing is infeasible, unless we guarantee that all subroutine calls mutually exclude each other. In VASS, we accept function de nitions and calls inside a procedural, under the following observations. If by analyzing the speci cation, mutual exclusiveness can not be guaranteed, then all calls to a function are expanded with the function body. If mutual exclusiveness is guaranteed, i.e. a function is only called from inside the alternatives of a branch, then we generate a structure, which multiplexes actual parameters to the inputs of the structure of the function body. VASS includes process statements for specifying event-driven behavior. However, the peculiarities of our design problem can be exploited for restricting process de nitions, so that they result in more e ective structural descriptions. Accepting unrestricted interactions between processes (i.e. synchronization, communication), ultimately means that the VHDLAMS simulation-cycle has to be explicitly realized in hardware. However, synchronization and inter-process communications are common for discrete-time systems, but they can be hardly accommodated with a continuous-time behavior. Thus, it is realistic to assume a simpli ed model of processes interactions, so that simpler hardware structures can be synthezised. We assume that processes react to events, and after resuming, they execute their entire body (calculate control signals), and then suspend. Process de nitions do not include any wait statements. Events originate either in the analog part (events on 'above' constructs), or the outer environment (events on port signals). The e ectiveness of the synthezised process structure can be further increased, if speci cations contemplate the following aspect with regard to signal use. Memory modules are expensive hardware (area, manufacturing), hence, whenever possible, our method avoids their use in the structural representation. General signals consist of a signal driver, apart from their current value. In order to reduce the amount of memory cells, we restrict the use of signals, so that they can be realized as one memory block. This is equivalent to avoiding to refer a signal after assigning a value to it. It is worth being mentioned, that the simpli ed process model also supports the constraint way of using signals. As opposed to VHDL-AMS, our subset includes a declarative mechanism for describing properties of quantities and signals. This mechanism is required

Tmax, and it is su cient that its outputs are produced at time steps greater than Tmax. This is

for synthesis as the behavior is strongly heterogeneous with respect to the signal types and characteristics. An integrator circuit 5] performs its functionality with regard to its input voltage, bu

t not its current. Besides, a declarative description style can be complementary to traditional description methods. Typically, transfer functions express the behavior of a lter. Nevertheless, if the transfer function is provided, then also the lter type, and its structure are decided. Instead, we could describe the properties of the signals along the signal path, i.e. frequency ranges, and let the synthesis tool infer the appropriate lter type. Currently, our annotation mechanism describes signal properties such as kind (voltage, current), value range, frequency range, and impedances at the terminal ports. Our ongoing work will explore a more systematic way of declaring the synthesis-related attributes of a design. This section details our experiment with the behavioral speci cation and synthesis of the real-life application of the receiver module of a telephone set 18]. This example is at the level of complexity which can be currently handled by our synthesis method. Besides, it corresponds to an interesting situation, where the control part is implemented by using only analog components. In this section, we present our modeling of the receiver functionality, and its speci cation with VASS (including some required annotations). Next, we describe the intermediate representation (signalow graph and control part) produced by our compiler. We manually mapped the representation onto library components, and then, sized their physical dimensions. We analyzed the behavior of the resulted design by simulating it, and observing its outputs. The main function of the receiver module is to provide an audible signal to the telephone set earphone. It ampli es, with di erent gains, incoming signals transmitted from the calling part, and those produced by its own microphone ampli er and transmitter module. Besides, it automatically compensates losses introduced by di erent telephone line lengths. The output has a signal limiting capability, and is capable of driving a 270 load at 285 mV peak amplitude. A simpli ed VHDL-AMS speci cation of this example is depicted in Figure 2a. The output voltage earph is a weighted sum of the input voltages line and local. The resulted value is multiplied with a variable value rvar, which models the variable compensation resistance. The compensation algorithm is represented by a process statement, which, depending on the result of comparing quantity line and threshold voltage Vth, selects the corresponding compensation value. Quantities are annotated with attributes that indicate their kind (voltage), and output earph is augmented with information about its limiting and driving capabilities. Our compiler translated the speci cation into the signal- ow graph in Figure 2b. The signal- ow graph details the sequence of continuous-time operations on the input signals by showing block functionality, their

5 Application of the VHDL-AMS Subset for a Synthesis Experiment

This paper defines a VHDL-AMS subset for behavioral synthesis of analog systems. The subset includes language constructs for describing most of the functional aspects pertaining to analog systems. Besides, these constructs can be implemented with electroni

ENTITY telephone IS

PORT (

QUANTITY line: IN real; -- IS voltageQUANTITY local: IN real; -- IS voltageQUANTITY earph: OUT real) -- IS voltage-- limited-- drives 270 OEND ENTITY;

ARCHITECTURE behavioral OF telephone ISQUANTITY rvar: real;

SIGNAL c1: bit;

(1) earph == (Aline * line + Alocal * local) * rvar;(2) IF (c1=’1’) USErvar == r1c;ELSErvar == r1c + r2c;END USE;PROCESS (line’ABOVE(Vth)) ISBEGINIF (line’ABOVE(Vth) = TRUE) THENc1 <= ’1’;ELSEc1 <= ’0’;END IF;END PROCESS;END ARCHITECTURE;

a)

block3

line-- voltage

local-- voltage* Aline* Alocal

block1

block5

line

Vth+-block3block2b)VDDearph-- limited-- drives 270 O c1 = ’1’21line < Vth3c1 = ’0’startline

local-

+-+earphblock1block2

c)block4

This paper defines a VHDL-AMS subset for behavioral synthesis of analog systems. The subset includes language constructs for describing most of the functional aspects pertaining to analog systems. Besides, these constructs can be implemented with electroni

quency bandwidth, etc. Such information is required not only for design parameter optimization, but also, as our experiment showed, for inferring a proper hardware structure for a VHDL-AMS speci cation. Each of the language constructs in the subset can be translated into a signal- ow based representation, which is mappable to library components, and then, sized for optimizing performance constraints. Our translation rules were already embedded in a VHDL-AMS compiler. Our ongoing work is oriented towards two distinct objectives. We will explore a more systematic way of describing system attributes for synthesis. Besides, we are also concerned about the impact of the speci cation style on the quality of the produced implementation. Second, we plan to focus on the development of an algorithm for automatically mapping the structural representation into a net-list of components. This algorithm will separately consider the signal- ow part and the Finite State Machine, but it will care about their interdependence with respect to the performance attributes of the global system.

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