MAX1310ECM中文资料

元器件交易网

19-3052; Rev 3; 8/04

8-/4-/2-Channel,with ±10V, ±5V12-Bit,, and 0 to +5V Analog Input Ranges

Simultaneous-Sampling ADCsGeneral Description

The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312– Up to Eight Channels of Simultaneous Sampling

MAX1314 12-bit, analog-to-digital converters (ADCs) offereight, four, or two independent input channels.8ns Aperture Delay

Independent track-and-hold (T/H) circuitry provides simul-100ps Channel-to-Channel T/H Matchtaneous sampling for each channel. The MAX1304/ Extended Input Ranges

MAX1305/MAX1306 provide a 0 to +5V input range with0 to +5V (MAX1304/MAX1305/MAX1306)±6V fault-tolerant inputs. The MAX1308/MAX1309/-5V to +5V (MAX1308/MAX1309/MAX1310)MAX1310 provide a ±5V input range with ±16.5V fault-tol--10V to +10V (MAX1312/MAX1313/MAX1314)erant inputs. The MAX1312/MAX1313/MAX1314 have a Fast Conversion Time

±10V input range with ±16.5V fault-tolerant inputs. TheseADCs convert two channels in 0.9µs, and up to eightOne Channel in 0.72µschannels in 1.98µs, with an 8-channel throughput ofTwo Channels in 0.9µs456ksps per channel. Other features include a 20MHz T/HFour Channels in 1.26µsinput bandwidth, internal clock, internal (+2.5V) or externalEight Channels in 1.98µs

(+2.0V to +3.0V) reference, and power-saving modes. High Throughput

A 20MHz, 12-bit, bidirectional parallel data bus pro-1075ksps/Channel for One Channelvides the conversion results and accepts digital inputs901ksps/Channel for Two Channelsthat activate each channel individually.

680ksps/Channel for Four ChannelsAll devices operate from a +4.75V to +5.25V analog supply456ksps/Channel for Eight Channelsand a +2.7V to +5.25V digital supply and consume 57mA ±1 LSB INL, ±0.9 LSB DNL (max)total supply current when fully operational.

84dBc SFDR, -86dBc THD, 71dBSINAD, Each device is available in a 48-pin 7mm x 7mm TQFPfIN= 500kHz at 0.4dBFSpackage and operates over the extended -40°C to+85°C temperature range.

12-Bit, 20MHz, Parallel Interface Internal or External Clock

Applications

+2.5V Internal Reference or +2.0V to +3.0VSIN/COS Position EncoderExternal ReferenceMultiphase Motor Control +5V Analog Supply, +3V to +5V Digital Supply

Multiphase Power Monitoring55mA Analog Supply CurrentPower-Grid Synchronization1.3mA Digital Supply Current

Shutdown and Power-Saving ModesPower-Factor Monitoring 48-Pin TQFP Package (7mm x 7mm Footprint)

Vibration and Waveform Analysis

________________________________________________________________Maxim Integrated Products

1

For pricing delivery, and ordering informationplease contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .

MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

8-/4-/2-Channel,12-Bit,Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

ABSOLUTE MAXIMUM RATINGS

AVDD to AGND.........................................................-0.3V to +6VDVDDto DGND.........................................................-0.3V to +6VAGND to DGND.....................................................-0.3V to +0.3VCH0–CH7, I.C. to AGND (MAX1304/MAX1305/MAX1306)....±6VCH0–CH7, I.C. to AGND (MAX1308/MAX1309/MAX1310)..±16.5VCH0–CH7, I.C. to AGND (MAX1312/MAX1313/MAX1314)..±16.5VD0–D11 to DGND....................................-0.3V to (DVDD + 0.3V)EOC, EOLC, RD, WR, CSto DGND.........-0.3V to (DVDD + 0.3V)CONVST, CLK, SHDN, CHSHDNto DGND..-0.3V to (DVDD + 0.3V)INTCLK/EXTCLKto AGND.......................-0.3V to (AVDD + 0.3V)

REFMS, REF, MSV to AGND.....................-0.3V to (AVDD + 0.3V)REF+, COM, REF- to AGND.....................-0.3V to (AVDD + 0.3V)Maximum Current into Any Pin Except AVDD, DVDD, AGND,DGND...........................................................................±50mAContinuous Power Dissipation (TA= +70°C)

TQFP (derate 22.7mW/°C above +70°C)................1818.2mWOperating Temperature Range...........................-40°C to +85°CJunction Temperature......................................................+150°CStorage Temperature Range.............................-65°C to +150°CLead Temperature (soldering, 10s).................................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(AVDD= +5V, DVDD= +3V, AGND = DGND = 0, VREF = VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+ =CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-lar devices), fCLK= 16.67MHz 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA= TMINto TMAX,unless otherwise noted. Typical values are at TA= +25°C. See Figures 3 and 4.)

2_______________________________________________________________________________________

8-/4-/2-Channel,with ±10V, ±5V12-Bit,, and 0 to +5V Analog Input Ranges

Simultaneous-Sampling ADCsELECTRICAL CHARACTERISTICS (continued)

(AVDD= +5V, DVDD= +3V, AGND = DGND = 0, VREF = VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+ =CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-lar devices), fCLK= 16.67MHz 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA= TMINto TMAX,unless otherwise noted. Typical values are at TA= +25°C. See Figures 3 and 4.)

_______________________________________________________________________________________3

MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

8-/4-/2-Channel,12-Bit,Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= +5V, DVDD= +3V, AGND = DGND = 0, VREF = VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+ =CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-lar devices), fCLK= 16.67MHz 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA= TMINto TMAX,unless otherwise noted. Typical values are at TA= +25°C. See Figures 3 and 4.)

4_______________________________________________________________________________________

8-/4-/2-Channel,with ±10V, ±5V12-Bit,, and 0 to +5V Analog Input Ranges

Simultaneous-Sampling ADCsELECTRICAL CHARACTERISTICS (continued)

(AVDD= +5V, DVDD= +3V, AGND = DGND = 0, VREF = VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+ =CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-lar devices), fCLK= 16.67MHz 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA= TMINto TMAX,unless otherwise noted. Typical values are at TA= +25°C. See Figures 3 and 4.)

_______________________________________________________________________________________5

MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

8-/4-/2-Channel,12-Bit,Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= +5V, DVDD= +3V, AGND = DGND = 0, VREF = VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+ =CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-lar devices), fCLK= 16.67MHz 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA= TMINto TMAX,unless otherwise noted. Typical values are at TA= +25°C. See Figures 3 and 4.)

MAX1312/MAX1313/MAX1314, VIN= -10V to +10V.

Note 2:All channel performance is guaranteed by correlation to a single channel test.

Note 3:The analog input resistance is terminated to an internal bias point (Figure 5). Calculate the analog input current using:

ICH_=

VCH_ VBIAS

RCH_

for VCHwithin the input voltage range.

Note 4:Throughput rate is given per channel. Throughput rate is a function of clock frequency (fCLK). The external clock through-put rate is specified with fCLK= 16.67MHz and the internal clock throughput rate is specified with fCLK= 15MHz. See theData Throughputsection for more information.

Note 5:The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using:

IREF=

VREF 2.5V

RREF

for VREFwithin the input voltage range.

Note 6:The REFMSinput resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REFMSinput current using:

IREFMS=

VREFMS 2.5V

RREFMS

for VREFMSwithin the input voltage range.

Note 7:All analog inputs are driven with a -0.4dBFS 500kHz sine wave.

Note 8:Shutdown current is measured with the analog input floating. The large amplitude of the maximum shutdown current speci-fication is due to automated test equipment limitations.

Note 9:CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop.Note 10:CSto WRand CSto RDare internally AND together. Setup and hold times do not apply.

Note 11:Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST

and the falling edge of EOLCto a maximum of 1ms.

6_______________________________________________________________________________________

元器件交易网

8-/4-/2-Channel,with ±10V, ±5V12-Bit,, and 0 to +5V Analog Input Ranges

Simultaneous-Sampling ADCsTypical Operating Characteristics

(AVDD= +5V, DVDD= +3V, AGND = DGND = 0, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+=CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolardevices), fCLK= 16.67MHz 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), fIN= 500kHz, AIN= -0.4dBFS. TA= +25°C,unless otherwise noted.) (Figures 3 and 4)

INTEGRAL NONLINEARITYDIFFERENTIAL NONLINEARITYvs. DIGITAL OUTPUT CODE

vs. DIGITAL OUTPUT CODE

1.01

1.0

2

00ccoot t40.8 4000.83311XXA0.6AM0.6M0.40.4)

)

BB0.2S0.2SLL( ( L0L0NNDI-0.2-0.2-0.4-0.4-0.6-0.6-0.8-0.8-1.0

-1.0

5121024153620482560307235844096

5121024153620482560307235844096

DIGITAL OUTPUT CODE

DIGITAL OUTPUT CODE

OFFSET ERROR

OFFSET ERRORvs. ANALOG SUPPLY VOLTAGE

vs. TEMPERATURE

1.016

0.8120.6)

8B)

S0.4BLS( LR0.2(4 ORRORRE0R0 TE ETS-0.2EFSFF-4O-0.4FO-0.6-8-0.8-12

-1.0

-164.7

4.8

4.9

5.05.1

5.2

5.3

-40

-15

10

35

60

85

AVDD (V)

TEMPERATURE (°C)

GAIN ERROR

GAIN ERRORvs. ANALOG SUPPLY VOLTAGE

vs. TEMPERATURE

116

1208

)

B)

S-1BLS(L4 (R ORROR-2R0ER EN INAIG-3A-4G-8-4-12-5-164.7

4.8

4.9

5.05.1

5.2

5.3

-40

-15

10

35

60

85

AVDD (V)

TEMPERATURE (°C)

_______________________________________________________________________________________7

MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

元器件交易网

8-/4-/2-Channel,12-Bit,Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

(AVDD= +5V, DVDD= +3V, AGND = DGND = 0, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+=CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolardevices), fCLK= 16.67MHz 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), fIN= 500kHz, AIN= -0.4dBFS. TA= +25°C,unless otherwise noted.) (Figures 3 and 4)

SMALL-SIGNAL BANDWIDTHvs. ANALOG INPUT FREQUENCY

LARGE-SIGNAL BANDWIDTHvs. ANALOG INPUT FREQUENCY

20-2GAIN (dB)

-4-6-8-10-12

0.1

1

20-2GAIN (dB)

-4-6-8-10-12

101000.1110100

ANALOG INPUT FREQUENCY (MHz)ANALOG INPUT FREQUENCY (MHz)

FFT PLOT

(2048-POINT DATA RECORD)

OUTPUT HISTOGRAM (DC INPUT)

600050004000COUNTS300020001000

2045

2046

2047

2048

0-10-20AMPLITUDE (dBFS)

-30-40-50-60-70-80-90-100-110

2044

FREQUENCY (kHz)

DIGITAL OUTPUT CODE

8_______________________________________________________________________________________

元器件交易网

8-/4-/2-Channel,with ±10V, ±5V12-Bit,, and 0 to +5V Analog Input Ranges

Simultaneous-Sampling ADCs(AVDD= +5V, DVDD= +3V, AGND = DGND = 0, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+=CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolardevices), fCLK= 16.67MHz 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), fIN= 500kHz, AIN= -0.4dBFS. TA= +25°C,unless otherwise noted.) (Figures 3 and 4)

SIGNAL-TO-NOISE RATIOSIGNAL-TO-NOISE PLUS DISTORTION

vs. CLOCK FREQUENCY

vs. CLOCK FREQUENCY

801

80

2

11ccoo78t 40378t 40311XX76AM76AM7474)

)

B72Bd72d(( RDN70A70SNI68S6866666464626260

60

5

10

15

20

250510152025

fCLK (MHz)fCLK (MHz)

TOTAL HARMONIC DISTORTION

SPURIOUS-FREE DYNAMIC RANGE

vs. CLOCK FREQUENCY

vs. CLOCK FREQUENCY

-603

1100

4

1ccoott 4400-653311X95XAAMM-7090)

)

c85c-75BBdd(( D-80RHD80FTS-8575-9070-9565-100

60

5

10

15

20

25

5

10

15

20

25

fCLK (MHz)

fCLK (MHz)

_______________________________________________________________________________________9

MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

元器件交易网

8-/4-/2-Channel,12-Bit,Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

(AVDD= +5V, DVDD= +3V, AGND = DGND = 0, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+=CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolardevices), fCLK= 16.67MHz 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), fIN= 500kHz, AIN= -0.4dBFS. TA= +25°C,unless otherwise noted.) (Figures 3 and 4)

SIGNAL-TO-NOISE RATIOvs. REFERENCE VOLTAGE

MAX1304 toc15

SIGNAL-TO-NOISE PLUS DISTORTION

vs. REFERENCE VOLTAGE

747372SINAD (dB)

71706968676665

MAX1304 toc16

75747372SNR (dB)

717069686766652.0

2.2

2.4

2.6

2.8

75

3.0

2.02.22.42.62.83.0

VREF (V)

VREF (V)

TOTAL HARMONIC DISTORTIONvs. REFERENCE VOLTAGE

MAX1304 toc17

SPURIOUS-FREE DYNAMIC RANGE

vs. REFERENCE VOLTAGE

MAX1304 toc18

-70-72-74-76

1009590SFDR (dBc)

858075702.0

2.2

2.4

2.6

2.8

THD (dBc)

-78-80-82-84-86-88-90

2.0

2.2

2.4

2.6

2.8

3.0

VREF (V)

3.0

VREF (V)

10______________________________________________________________________________________

元器件交易网

8-/4-/2-Channel,with ±10V, ±5V12-Bit,, and 0 to +5V Analog Input Ranges

Simultaneous-Sampling ADCs(AVDD= +5V, DVDD= +3V, AGND = DGND = 0, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+=CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolardevices), fCLK= 16.67MHz 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), fIN= 500kHz, AIN= -0.4dBFS. TA= +25°C,unless otherwise noted.) (Figures 3 and 4)

ANALOG SUPPLY CURRENTDIGITAL SUPPLY CURRENTvs. ANALOG SUPPLY VOLTAGE

vs. DIGITAL SUPPLY VOLTAGE

572.0561.8

1.655)

)

AAmm(1.4( DDDD54VVDAI1.2I531.0520.8510.6

4.7

4.8

4.9

5.05.1

5.2

5.3

2.53.03.54.04.55.05.5

AVDD

(V)

DVDD (V)

ANALOG SHUTDOWN CURRENTDIGITAL SHUTDOWN CURRENTvs. ANALOG SUPPLY VOLTAGE

vs. DIGITAL SUPPLY VOLTAGE

7002268066020640

18)

)

AAn620n(( D600DDD16VVADI580I5601454012

520500

104.7

4.8

4.9

5.05.1

5.2

5.3

2.5

3.03.54.04.55.05.5

AVDD (V)

DVDD (V)

ANALOG SUPPLY CURRENT

DIGITAL SUPPLY CURRENT

vs. NUMBER OF CHANNELS SELECTED

vs. NUMBER OF CHANNELS SELECTED

60

1.0

0.9550.8500.7)

A)

Amm( 0.6(D D45DDVDV0.5IAI400.40.3

350.230

0.1

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

NUMBER OF CHANNELS SELECTED

NUMBER OF CHANNELS SELECTED

______________________________________________________________________________________11

MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

元器件交易网

8-/4-/2-Channel,12-Bit,Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

(AVDD= +5V, DVDD= +3V, AGND = DGND = 0, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+=CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipolardevices), fCLK= 16.67MHz 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), fIN= 500kHz, AIN= -0.4dBFS. TA= +25°C,unless otherwise noted.) (Figures 3 and 4)

INTERNAL REFERENCE VOLTAGEvs. ANALOG SUPPLY VOLTAGE

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

2.5032.502VREF (V)2.5012.5002.4992.4982.4972.496

2.50042.50032.5002VREF (V)2.50012.50002.49992.49982.49972.4996

4.7

4.8

4.9

5.0AVDD (V)

5.1

5.2

2.504

5.3-40

-1510356085

TEMPERATURE (°C)

INTERNAL CLOCK CONVERSION TIMEvs. ANALOG SUPPLY VOLTAGE

INTERNAL CLOCK CONVERSION TIME

vs. TEMPERATURE

900800

700600TIME (ns)

50040030020010004.7

4.8

4.9

5.0AVDD (V)

5.1

5.2

TIME (ns)

-40

-15

10

35

60

85

TEMPERATURE (°C)

5.3

ANALOG INPUT CHANNEL CURRENTvs. ANALOG INPUT CHANNEL VOLTAGE

ANALOG INPUT CHANNEL CURRENTvs. ANALOG INPUT CHANNEL VOLTAGE

ANALOG INPUT CHANNEL CURRENTvs. ANALOG INPUT CHANNEL VOLTAGE

1.51.0ICH_ (mA)

0.50-0.5-1.0-1.5-2.0

2.01.51.0

3.02.52.01.51.0ICH_ (mA)

0.50-0.5-1.0-1.5-2.0-2.5-3.0

-20

-15

-10

-5

0VCH_ (V)

5

10

15

2.0

ICH_ (mA)

0.50-0.5-1.0-1.5-2.0

-6

-4

-2

0VCH_ (V)

2

4

6

20-20-15-10-50VCH_ (V)

5101520

12______________________________________________________________________________________

8-/4-/2-Channel,with ±10V, ±5V12-Bit,, and 0 to +5V Analog Input Ranges

Simultaneous-Sampling ADCsPin Description

______________________________________________________________________________________13

MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

8-/4-/2-Channel,12-Bit,Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

14______________________________________________________________________________________

8-/4-/2-Channel,with ±10V, ±5V12-Bit,, and 0 to +5V Analog Input Ranges

Simultaneous-Sampling ADCsPin Description (continued)

The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 are 12-bit ADCs. The devices offer 8, 4, or 2independently selectable input channels, each withdedicated T/H circuitry. Simultaneous sampling of allactive channels preserves relative phase informationmaking these devices ideal for motor control and powermonitoring. Three input ranges are available, 0 to +5V,±5V and ±10V. The 0 to +5V devices provide ±6V fault-tolerant inputs. The ±5V and ±10V devices provide±16.5V fault-tolerant inputs. Two-channel conversionresults are available in 0.9µs. Conversion results fromall eight channels are available in 1.98µs. The 8-chan-nel throughput is 456ksps per channel. Internal orexternal reference and clock capability offer great flexi-bility, and ease of use. A write-only configuration regis-ter can mask out unused channels and a shutdownfeature reduces power. A 20MHz, 12-bit, parallel databus outputs the conversion results. Figure 2 shows thefunctional diagram of these ADCs.

______________________________________________________________________________________15

MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

8-/4-/2-Channel,12-Bit,Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

Figure 2. Functional Diagram

16______________________________________________________________________________________

8-/4-/2-Channel,with ±10V, ±5V12-Bit,, and 0 to +5V Analog Input Ranges

Simultaneous-Sampling ADCsFigure 3. Typical Bipolar Operating Circuit

______________________________________________________________________________________17

MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

with ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

Figure 4. Typical Unipolar Operating Circuit

18______________________________________________________________________________________

with ±10V, ±5V, and 0 to +5V Analog Input Ranges

acquisition time must be limited to 1ms. Accuracy withconversion times longer than 1ms cannot be guaran-teed due to capacitor droop in the input circuitry.

Due to the analog input resistive divider formed by R1and R2 in Figure 5, any significant analog input sourceresistance (RSOURCE) results in gain error. Further-more, RSOURCEcauses distortion due to nonlinear analog input currents. Limit RSOURCEto a maximum of 100 .

MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

Selecting an Input Buffer

To improve the input signal bandwidth under AC condi-tions, drive the input with a wideband buffer (>50MHz)that can drive the ADC’s input capacitance (15pF) andsettle quickly. For example, the MAX4431 or theMAX4265 can be used for the 0 to +5V unipolar devices,or the MAX4350 can be used for ±5V bipolar inputs.

Most applications require an input buffer to achieve 12-bitaccuracy. Although slew rate and bandwidth are impor-tant, the most critical input buffer specification is settlingtime. The simultaneous sampling of multiple channelsrequires an acquisition time of 100ns. At the beginning ofthe acquisition, the ADC internal sampling capacitor arrayconnects to the analog inputs, causing some distur-bance. Ensure the amplifier is capable of settling to atleast 12-bit accuracy during this interval. Use a low-noise,low-distortion, wideband amplifier that settles quickly andis stable with the ADC’s 15pF input capacitance.

See the Maxim website at for appli-cation notes on how to choose the optimum bufferamplifier for your ADC application.

Input Bandwidth

The input-tracking circuitry has a 20MHz small-signalbandwidth, making it possible to digitize high-speedtransient events and measure periodic signals withbandwidths exceeding the ADC’s sampling rate byusing undersampling techniques. To avoid high-fre-quency signals being aliased into the frequency bandof interest, anti-alias filtering is recommended.

Input Range and Protection

The MAX1304/MAX1305/MAX1306 provide a 0 to +5Vinput voltage range with fault protection of ±6V. TheMAX1308/MAX1309/MAX1310 provide a ±5V input volt-age range with fault protection of ±16.5V. TheMAX1312/MAX1313/MAX1314 provide a ±10V inputvoltage range with fault protection of ±16.5V. Figure 5shows the single-channel equivalent input circuit.

Figure 5. Single-Channel, Equivalent Analog Input T/H Circuit

Analog Inputs

Track and Hold (T/H)

To preserve phase information across the multichannelMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314, all input channels have dedicated T/H ampli-fiers. Figure 5 shows the equivalent analog input T/Hcircuit for one channel.

The input T/H circuit is controlled by the CONVST input.When CONVST is low, the T/H circuit tracks the analoginput. When CONVST is high the T/H circuit holds theanalog input. The rising edge of CONVST is the analoginput sampling instant. There is an aperture delay (tAD)of 8ns and a 50psRMSaperture jitter (tAJ). The aperturedelay of each dedicated T/H input is matched within100ps of each other.

To settle the charge on CSAMPLEto 12-bit accuracy,use a minimum acquisition time (tACQ) of 100ns.Therefore, CONVST must be low for at least 100ns.Although longer acquisition times allow the analog inputto settle to its final value more accurately, the maximum

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with ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

Data Throughput

The data throughput (fTH) of the MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 is a functionof the clock speed (fCLK). In internal clock mode, fCLK=15MHz (typ). In external clock mode, 100kHz ≤fCLK≤20MHz. When reading during conversion (Figures 7 and8), calculate fTHas follows:

fTH=

tACQ+tQUIET

1

+

fCLK

Clock Modes

The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314 provide a 15MHz internal conversion clock.Alternatively, an external clock can be used.

Internal Clock

Internal clock mode frees the microprocessor from theburden of running the ADC conversion clock. For inter-nal clock operation, connect INTCLK/EXTCLKto AVDDand connect CLK to DGND. Note that INTCLK/EXTCLKis referenced to AVDD, not DVDD.

External Clock

For external clock operation, connect INTCLK/EXTCLKto AGND and connect an external clock source to CLK.Note that INTCLK/EXTCLKis referenced to AVDD, notDVDD. The external clock frequency can be up to20MHz. Linearity is not guaranteed with clock frequen-cies below 100kHz due to droop in the T/H circuits.

where N is the number of active channels and tQUIETisthe period of bus inactivity before the rising edge ofCONVST. See the Starting a Conversion section formore information.

Table 1 uses the above equation and shows the totalthroughput as a function of the number of channelsselected for conversion.

Table 1. Throughput vs. Channels Sampled: f

= 15MHz, t= 100ns, t= 50ns

20______________________________________________________________________________________

8-/4-/2-Channel,with ±10V, ±5V12-Bit,, and 0 to +5V Analog Input Ranges

Simultaneous-Sampling ADCsHowever, the new configuration does not take effectDigital Interface

until the next CONVST falling edge. At power-up allThe bidirectional parallel digital interface allows for settingchannels default active. Shutdown does not change thethe 8-bit configuration register (see the Configurationconfiguration register. The configuration register mayRegistersection) and reading the 12-bit conversionbe written to in shutdown. See the Channel Shutdownresult. The interface includes the following control signals:(CHSHDN) section for information about using the con-chip select (CS), read (RD), write (WR), end of conversionfiguration register for power saving.

(EOC), end of last conversion (EOLC), conversion start(CONVST), shutdown (SHDN), channel shutdown(CHSHDN), internal clock select (INTCLK/EXTCLK), andexternal clock input (CLK). Figures 6, 7, 8, 9, Table 2, andthe Timing Characteristicsshow the operation of the inter-face. D0–D7 are bidirectional, and D8–D11 are outputonly. D0–D11 go high impedance when RD= 1 or CS= 1.

Configuration Register

Enable channels as active by writing to the configura-tion register through I/O lines D0–D7 (Table 2). The bitsin the configuration register map directly to the chan-nels, with D0 controlling channel zero, and D7 control-ling channel seven. Setting any bit high activates thecorresponding input channel, while resetting any bitlow deactivates the corresponding channel. On thedevices with less than eight channels, some of the bitshave no function (Table 2).

To write to the configuration register, pull CSand WRlow, load bits D0 through D7 onto the parallel bus, andforce WRhigh. The data are latched on the rising edgeof WR(Figure 6). Write to the configuration register atany point during the conversion sequence. At power-up, write to the configuration register to select theactive channels before beginning a conversion.

Table 2. Configuration Register

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MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

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