IS62WV51216BLL-55TLI中文资料

元器件交易网

IS62WV51216ALLIS62WV51216BLL

512K x 16 LOW VOLTAGE,

ULTRA LOW POWER CMOS STATIC RAM

ISSI

FEBRUARY 2005

®

FEATURES

High-speed access time: 45ns, 55ns CMOS low power operation– 36 mW (typical) operating– 12 µW (typical) CMOS standby TTL compatible interface levels Single power supply

– 1.65V--2.2V VDD (62WV51216ALL)– 2.5V--3.6V VDD (62WV51216BLL) Fully static operation: no clock or refreshrequired Three state outputs

Data control for upper and lower bytes Industrial temperature available Lead-free available

DESCRIPTION

The ISSI IS62WV51216ALL/ IS62WV51216BLL are high-speed, 8M bit static RAMs organized as 512K words by 16bits. It is fabricated using ISSI's high-performance CMOStechnology. This highly reliable process coupled withinnovative circuit design techniques, yields high-performance and low power consumption devices.When CS1 is HIGH (deselected) or when CS2 is LOW(deselected) or when CS1 is LOW, CS2 is HIGH and bothLB and UB are HIGH, the device assumes a standby modeat which the power dissipation can be reduced down withCMOS input levels.

Easy memory expansion is provided by using Chip Enableand Output Enable inputs. The active LOW Write Enable(WE) controls both writing and reading of the memory. Adata byte allows Upper Byte (UB) and Lower Byte (LB)access.

The IS62WV51216ALL and IS62WV51216BLL are packagedin the JEDEC standard 48-pin mini BGA (7.2mm x 8.7mm)and 44-Pin TSOP (TYPE II).

FUNCTIONAL BLOCK DIAGRAM

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabilityarising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on anypublished information and before placing orders for products.

Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

1

元器件交易网

IS62WV51216ALL, IS62WV51216BLL

PIN CONFIGURATIONS

48-Pin mini BGA (7.2mm x 8.7mm)

1 2 3 4 5 6

ISSI

PIN DESCRIPTIONS

A0-A18I/O0-I/O15CS1, CS2OEWELBUBNCVDDGND

Address InputsData Inputs/OutputsChip Enable InputOutput Enable InputWrite Enable Input

Lower-byte Control (I/O0-I/O7)Upper-byte Control (I/O8-I/O15)No ConnectionPowerGround

®

ABCDEFGH

LBI/O8I/O9VDDI/OI/O15A18

OEUBI/O10I/O1112I/ONCA8

A0A3A5A17GNDA14A12A9

A1A4A6A7A16A15A13A10

A2CS1I/O1I/O3I/O4I/O5WEA11

CS2I/O0I/O2VDD`I/O6I/O7NC

44-Pin TSOP (Type II)

A4A3A2A1A0CS1I/O0I/O1I/O2I/O3VDDGNDI/O4I/O5I/O6I/O7WEA16A15A14A13A121234567891011121314151617181920212244434241403938373635343332313029282726252423A5A6A7OEUBLBI/O15I/O14I/O13I/O12GNDVDDI/O11I/O10I/O9I/O8A18A8A9A10A11A17

2Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

元器件交易网

IS62WV51216ALL, IS62WV51216BLL

TRUTH TABLE

ModeNot Selected

WEXXXHHHHHLLL

CS1HXXLLLLLLLL

CS2XLXHHHHHHHH

OEXXXHHLLLXXX

LBXXHLXLHLLHL

UBXXHXLHLLHLL

I/O PIN

I/O0-I/O7I/O8-I/O15High-ZHigh-ZHigh-ZHigh-ZHigh-ZDOUTHigh-ZDOUTDINHigh-ZDIN

High-ZHigh-ZHigh-ZHigh-ZHigh-ZHigh-ZDOUTDOUTHigh-ZDINDIN

ISSI

VDD CurrentISB1, ISB2ISB1, ISB2ISB1, ISB2

ICCICCICC

®

Output DisabledRead

WriteICC

OPERATING RANGE (VDD)

Range

Ambient TemperatureIS62WV51216ALL (70ns)IS62WV51216BLL (55ns, 70ns)

IS62WV51216BLL (45ns)

CommercialIndustrial

0°C to +70°C–40°C to +85°C

1.65V - 2.2V1.65V - 2.2V

2.5V - 3.6V 2.5V - 3.6V

3.0 - 3.6V

Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

3

元器件交易网

IS62WV51216ALL, IS62WV51216BLL

ABSOLUTE MAXIMUM RATINGS(1)

SymbolVTERMTBIASVDDTSTGPT

Parameter

Terminal Voltage with Respect to GNDTemperature Under BiasVDD Related to GNDStorage TemperaturePower Dissipation

Value

–0.2 to VDD+0.3–40 to +85–0.2 to +3.8–65 to +150

1.0

UnitV°CV°CW

ISSI

®

Note:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at these or any other conditions abovethose indicated in the operational sections of this specification is not implied. Exposure to absolute maximumrating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

SymbolVOHVOLVIHVIL(1)ILIILO

Parameter

Output HIGH VoltageOutput LOW VoltageInput HIGH VoltageInput LOW VoltageInput LeakageOutput Leakage

GND ≤ VIN ≤ VDD

GND ≤ VOUT ≤ VDD, Outputs DisabledTest ConditionsIOH = -0.1 mAIOH = -1 mAIOL = 0.1 mAIOL = 2.1 mA

VDD1.65-2.2V2.5-3.6V1.65-2.2V2.5-3.6V1.65-2.2V2.5-3.6V1.65-2.2V2.5-3.6V

Min.1.42.2——1.42.2–0.2–0.2–1–1

Max.——0.20.4VDD + 0.2VDD + 0.30.40.611

UnitVVVVVVVVµAµA

Notes:

1.VIL (min.) = –1.0V for pulse width less than 10 ns.

4Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

元器件交易网

IS62WV51216ALL, IS62WV51216BLL

CAPACITANCE(1)

SymbolCINCOUT

ParameterInput CapacitanceInput/Output Capacitance

ConditionsVIN = 0VVOUT = 0V

Max.810

UnitpFpF

ISSI

®

Note:

1.Tested initially and after any design or process changes that may affect these parameters.

AC TEST CONDITIONS

Parameter

Input Pulse Level

Input Rise and Fall TimesInput and Output Timingand Reference LevelOutput Load

62WV51216ALL

(Unit)

0.4V to VDD-0.2

5 nsVREFSee Figures 1 and 2

62WV51216BLL

(Unit)

0.4V to VDD-0.3V

5nsVREFSee Figures 1 and 2

62WV51216ALL(1.65V - 2.2V)

R1( )R2( )VREFVTM

307031500.9V1.8V

62WV51216BLL(2.5V - 3.6V)

102917281.5V2.8V

AC TEST LOADS

Figure 1

Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

5

元器件交易网

IS62WV51216ALL, IS62WV51216BLL

IS62WV51216ALL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)

SymbolICCICC1

Parameter

VDD Dynamic OperatingSupply CurrentOperating SupplyCurrent

TTL Standby Current(TTL Inputs)

Test ConditionsVDD = Max.,

IOUT = 0 mA, f = fMAX

VDD = Max., CS1 = 0.2VWE = VDD – 0.2V

CS2 = VDD – 0.2V, f = 1MHZVDD = Max.,VIN = VIH or VIL

CS1 = VIH , CS2 = VIL,f = 1 MHZ

.Ind.

Max.702025440.30.3

UnitmAmA

ISSI

®

ISB1mA

ORULB Control

ISB2

CMOS Standby

Current (CMOS Inputs)

VDD = Max., VIN = VIH or VIL

CS1 = VIL, f = 0, UB = VIH, LB = VIHVDD = Max.,Com.CS1 ≥ VDD – 0.2V,Ind.CS2 ≤ 0.2V,typ.(1)VIN ≥ VDD – 0.2V, orVIN ≤ 0.2V, f = 0

15213

µA

ORULB Control

VDD = Max., CS1 = VIL, CS2=VIHVIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0;UB / LB = VDD – 0.2V

Note:.

1. Typical values are measured at VDD = 1.8V, TA = 25oC and not 100% tested.

6Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

元器件交易网

IS62WV51216ALL, IS62WV51216BLL

IS62WV51216BLL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)

SymbolICCICC1

Parameter

VDD Dynamic OperatingSupply CurrentOperating SupplyCurrent

TTL Standby Current(TTL Inputs)

Test ConditionsVDD = Max.,

IOUT = 0 mA, f = fMAX

VDD = Max., CS1 = 0.2VWE = VDD – 0.2V

CS2 = VDD – 0.2V, f = 1MHZVDD = Max.,VIN = VIH or VIL

CS1 = VIH , CS2 = VIL,f = 1 MHZ

.Ind.

Max.453540550.30.3

Max.553035550.30.3

Max.702530550.30.3

ISSI

UnitmAmA

®

ISB1mA

ORULB Control

ISB2

CMOS Standby

Current (CMOS Inputs)

VDD = Max., VIN = VIH or VIL

CS1 = VIL, f = 0, UB = VIH, LB = VIHVDD = Max.,Com.CS1 ≥ VDD – 0.2V,Ind.CS2 ≤ 0.2V,typ. (2)VIN ≥ VDD – 0.2V, orVIN ≤ 0.2V, f = 0

202542025420254

µA

ORULB Control

VDD = Max., CS1 = VIL, CS2=VIHVIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0;UB / LB = VDD – 0.2V

Note:

1.At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.

Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

7

元器件交易网

IS62WV51216ALL, IS62WV51216BLL

READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)

Symbol

ParameterRead Cycle TimeAddress Access TimeOutput Hold TimeCS1/CS2 Access TimeOE Access TimeOE to High-Z OutputOE to Low-Z OutputCS1/CS2 to High-Z OutputCS1/CS2 to Low-Z OutputLB, UB Access TimeLB, UB to High-Z OutputLB, UB to Low-Z Output

45 nsMin.Max.45—10———5010—00

—45—452015—15—4515—

55 ns

Min.Max.55—10———5010—00

—55—552520—20—5520—

ISSI

70 ns

Min.Max.70—10———5010—00

—70—703525—25—7025—

Unitnsnsnsnsnsnsnsnsnsnsnsns

®

tRCtAAtOHAtACS1/tACS2tDOEtHZOE(2)tLZOE(2)

tHZCS1/tHZCS2(2)tLZCS1/tLZCS2(2)tBAtHZBtLZB

Notes:

1.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 toVDD-0.2V/0.4V to VDD-0.3V and output loading specified in Figure 1.

2.Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

AC WAVEFORMS

READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH, UB or LB = VIL)

8Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

元器件交易网

IS62WV51216ALL, IS62WV51216BLL

AC WAVEFORMS

READ CYCLE NO. 2(1,3)(CS1, CS2, OE, AND UB/LB Controlled)

ISSI

®

1.WE is HIGH for a Read Cycle.

2.The device is continuously selected. OE, CS1, UB, or LB = VIL. CS2=WE=VIH.3.Address is valid prior to or coincident with CS1 LOW transition.

Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

9

元器件交易网

IS62WV51216ALL, IS62WV51216BLL

WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)

Symbol

ParameterWrite Cycle Time

45ns Min.Max. 45 35 35 0 0 35 35 20 0 — 5

—————————20—

55 ns Min.Max. 55 45 45 0 0 45 40 25 0 — 5

—————————20—

ISSI

70 ns Min.Max. 70 60 60 0 0 60 50 30 0 — 5

—————————30—

Unitnsnsnsnsnsnsnsnsnsnsns

®

tWC

tSCS1/tSCS2CS1/CS2 to Write EndtAWAddress Setup Time to Write EndtHAtSAtPWBtPWE(4)tSDtHDtHZWE(3)tLZWE(3)

Notes:

Address Hold from Write EndAddress Setup TimeLB, UB Valid to End of WriteWE Pulse WidthData Setup to Write EndData Hold from Write EndWE LOW to High-Z OutputWE HIGH to Low-Z Output

1.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 toVDD-0.2V/0.4V to VDD-0.3V and output loading specified in Figure 1.

2.The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, butany one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates thewrite.

3.Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.4. tPWE > tHZWE + tSD when OE is LOW.

AC WAVEFORMS

WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW)

1.WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and atleast one of the LB and UB inputs being in the LOW state.2.WRITE = (CS1) [ (LB) = (UB) ] (WE).

10Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

元器件交易网

IS62WV51216ALL, IS62WV51216BLL

WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)

ISSI

®

WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)

Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

11

元器件交易网

IS62WV51216ALL, IS62WV51216BLL

WRITE CYCLE NO. 4 (UB/LB Controlled)

ISSI

®

12Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

元器件交易网

IS62WV51216ALL, IS62WV51216BLL

DATA RETENTION SWITCHING CHARACTERISTICS

Symbol

Parameter

VDD for Data RetentionData Retention CurrentData Retention Setup TimeRecovery Time

Test Condition

See Data Retention WaveformVDD = 1.2V, CS1 ≥ VDD – 0.2VSee Data Retention WaveformSee Data Retention Waveform

Min.1.2—0

Max.3.620——

UnitVµAnsns

ISSI

®

VDR

IDR

tSDRtRDR

tRC

DATA RETENTION WAVEFORM (CS1 Controlled)

DATA RETENTION WAVEFORM (CS2 Controlled)

Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

13

元器件交易网

IS62WV51216ALL, IS62WV51216BLL

ORDERING INFORMATIONIS62WV51216ALL (1.65V - 2.2V)Industrial Range: –40°C to +85°C

Speed (ns)

70

Order Part No.IS62WV51216ALL-70TIIS62WV51216ALL-70BIIS62WV51216ALL-70XI

PackageTSOP-II

ISSI

®

mini BGA (7.2mm x 8.7mm)DIE

ORDERING INFORMATIONIS62WV51216BLL (2.5V - 3.6V)Commercial Range: 0°C to +70°C

Speed (ns)

45

Order Part No.IS62WV51216BLL-45B

Package

mini BGA (7.2mm x 8.7mm)

Industrial Range: –40°C to +85°C

Speed (ns)

55

Order Part No.IS62WV51216BLL-55TIIS62WV51216BLL-55TLIIS62WV51216BLL-55BIIS62WV51216BLL-55BLI

70

IS62WV51216BLL-70XI

PackageTSOP-II

TSOP-II, Lead-freemini BGA (7.2mm x 8.7mm)

mini BGA (7.2mm x 8.7mm), Lead-freeDIE

14Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

元器件交易网

IS62WV51216ALL, IS62WV51216BLLMini Ball Grid Array

Package Code: B (48-pin)

Top ViewBottom View

ISSI

®

mBGA - 7.2mm x 8.7mm

MILLIMETERS

Sym.

N0.LeadsAA1A2DD1EE1eb

0.307.10—0 .240.608.60

Notes:

1. Controlling dimensions are in millimeters.

INCHESMin.Typ.Max.

Min.Typ.Max.

48———5.25BSC7.207.303.75BSC0.75BSC0.35

0.401.200.30—

—0.0090.024

— ——

0.0470.012—

8.708.800.3390.3430.346

0.207BSC0.2800.2830.287

0.148BSC0.030BSC0.0120.0140.016

Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.B02/24/05

15

元器件交易网

PACKAGING INFORMATION

Plastic TSOP

Package Code: T (Type II)

ISSI

®

Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.F06/18/03

本文来源：https://www.bwwdw.com/article/ychq.html