TMS320F2801PZS-60中文资料

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TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

Data Manual

Literature Number:SPRS230J

October2003–Revised September2007

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty.Production processing does not

necessarily include testing of all parameters.

Contents

TMS320F2809,TMS320F2808,TMS320F2806TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER 2003–REVISED SEPTEMBER 2007

Revision History ...........................................................................................................................91F280x,F2801x,C280x DSPs . (11)

1.1

Features .....................................................................................................................111.2

Getting Started (122)

Introduction (13)

2.1Pin Assignments ............................................................................................................152.2

Signal Descriptions (213)

Functional Overview (27)

3.1Memory Maps ...............................................................................................................283.2

Brief Descriptions ...........................................................................................................363.2.1C28x CPU .......................................................................................................363.2.2Memory Bus (Harvard Bus Architecture)....................................................................363.2.3Peripheral Bus ..................................................................................................363.2.4Real-Time JTAG and Analysis ................................................................................363.2.5Flash ..............................................................................................................373.2.6ROM ...............................................................................................................373.2.7M0,M1SARAMs ...............................................................................................373.2.8L0,L1,H0SARAMs ............................................................................................373.2.9Boot ROM ........................................................................................................373.2.10Security ..........................................................................................................393.2.11Peripheral Interrupt Expansion (PIE)Block ..................................................................403.2.12External Interrupts (XINT1,XINT2,XNMI)...................................................................403.2.13Oscillator and PLL ..............................................................................................403.2.14Watchdog ........................................................................................................403.2.15Peripheral Clocking .............................................................................................403.2.16Low-Power Modes ..............................................................................................403.2.17Peripheral Frames 0,1,2(PFn)..............................................................................413.2.18General-Purpose Input/Output (GPIO)Multiplexer .........................................................413.2.1932-Bit CPU-Timers (0,1,2)...................................................................................413.2.20Control Peripherals .............................................................................................413.2.21Serial Port Peripherals .........................................................................................423.3Register Map ................................................................................................................423.4Device Emulation Registers ...............................................................................................443.5Interrupts ....................................................................................................................443.5.1External Interrupts ..............................................................................................473.6

System Control .............................................................................................................483.6.1OSC and PLL Block ............................................................................................493.6.2Watchdog Block .................................................................................................523.7

Low-Power Modes Block (534)

Peripherals (54)

4.132-Bit CPU-Timers 0/1/2..................................................................................................544.2Enhanced PWM Modules (ePWM1/2/3/4/5/6)..........................................................................564.3Hi-Resolution PWM (HRPWM)...........................................................................................584.4Enhanced CAP Modules (eCAP1/2/3/4)................................................................................584.5Enhanced QEP Modules (eQEP1/2).....................................................................................614.6

Enhanced Analog-to-Digital Converter (ADC)Module ................................................................634.6.1ADC Connections if the ADC Is Not Used ...................................................................664.6.2ADC Registers ...................................................................................................674.7Enhanced Controller Area Network (eCAN)Modules (eCAN-A and eCAN-B).....................................684.8

Serial Communications Interface (SCI)Modules (SCI-A,SCI-B)....................................................

73

Contents 2

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TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER2003–REVISED SEPTEMBER2007

4.9Serial Peripheral Interface(SPI)Modules(SPI-A,SPI-B,SPI-C,SPI-D) (76)

4.10Inter-Integrated Circuit(I2C) (80)

4.11GPIO MUX (82)

5Device Support (86)

5.1Device and Development Support Tool Nomenclature (86)

5.2Documentation Support (88)

6Electrical Specifications (91)

6.1Absolute Maximum Ratings (91)

6.2Recommended Operating Conditions (92)

6.3Electrical Characteristics (92)

6.4Current Consumption (93)

6.4.1Reducing Current Consumption (97)

6.4.2Current Consumption Graphs (98)

6.5Emulator Connection Without Signal Buffering for the DSP (99)

6.6Timing Parameter Symbology (100)

6.6.1General Notes on Timing Parameters (100)

6.6.2Test Load Circuit (101)

6.6.3Device Clock Table (101)

6.7Clock Requirements and Characteristics (103)

6.8Power Sequencing (104)

6.8.1Power Management and Supervisory Circuit Solutions (104)

6.9General-Purpose Input/Output(GPIO) (107)

6.9.1GPIO-Output Timing (107)

6.9.2GPIO-Input Timing (108)

6.9.3Sampling Window Width for Input Signals (109)

6.9.4Low-Power Mode Wakeup Timing (110)

6.10Enhanced Control Peripherals (113)

6.10.1Enhanced Pulse Width Modulator(ePWM)Timing (113)

6.10.2Trip-Zone Input Timing (113)

6.10.3External Interrupt Timing (115)

6.10.4I2C Electrical Specification and Timing (116)

6.10.5Serial Peripheral Interface(SPI)Master Mode Timing (116)

6.10.6SPI Slave Mode Timing (120)

6.10.7On-Chip Analog-to-Digital Converter (123)

6.11Detailed Descriptions (128)

6.12Flash Timing (129)

6.13ROM Timing(C280x only) (130)

7Migrating From F280x Devices to C280x Devices (131)

7.1Migration Issues (131)

8Mechanical Data (132)

Contents3

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TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER2003–REVISED SEPTEMBER2007

List of Figures

2-1TMS320F2809,TMS320F2808100-Pin PZ LQFP(Top View) (16)

2-2TMS320F2806100-Pin PZ LQFP(Top View) (17)

2-3TMS320F2802,TMS320F2801,TMS320C2802,TMS320C2801100-Pin PZ LQFP

(Top View) (18)

2-4TMS320F2801x100-Pin PZ LQFP

(Top View) (19)

2-5TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801,

TMS320F28016,TMS320F28015,TMS320C2802,TMS320C2801

100-Ball GGM and ZGM MicroStar BGA?(Bottom View) (20)

3-1Functional Block Diagram (27)

3-2F2809Memory Map (28)

3-3F2808Memory Map (29)

3-4F2806Memory Map (30)

3-5F2802,C2802Memory Map (31)

3-6F2801,F28015,F28016,C2801Memory Map (32)

3-7External and PIE Interrupt Sources (45)

3-8Multiplexing of Interrupts Using the PIE Block (46)

3-9Clock and Reset Domains (48)

3-10OSC and PLL Block Diagram (49)

3-11Using a3.3-V External Oscillator (50)

3-12Using a1.8-V External Oscillator (50)

3-13Using the Internal Oscillator (50)

3-14Watchdog Module (52)

4-1CPU-Timers (54)

4-2CPU-Timer Interrupt Signals and Output Signal (55)

4-3Multiple PWM Modules in a280x System (56)

4-4ePWM Sub-Modules Showing Critical Internal Signal Interconnections (58)

4-5eCAP Functional Block Diagram (59)

4-6eQEP Functional Block Diagram (61)

4-7Block Diagram of the ADC Module (64)

4-8ADC Pin Connections With Internal Reference (65)

4-9ADC Pin Connections With External Reference (66)

4-10eCAN Block Diagram and Interface Circuit (69)

4-11eCAN-A Memory Map (70)

4-12eCAN-B Memory Map (71)

4-13Serial Communications Interface(SCI)Module Block Diagram (75)

4-14SPI Module Block Diagram(Slave Mode) (79)

4-15I2C Peripheral Module Interfaces (81)

4-16GPIO MUX Block Diagram (82)

4-17Qualification Using Sampling Window (85)

5-1Example of TMS320x280x Device Nomenclature (87)

List of Figures

4Submit Documentation Feedback

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TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER2003–REVISED SEPTEMBER2007 6-1Typical Operational Current Versus Frequency(F2808) (98)

6-2Typical Operational Power Versus Frequency(F2808) (98)

6-3Emulator Connection Without Signal Buffering for the DSP (99)

6-4 3.3-V Test Load Circuit (101)

6-5Clock Timing (104)

6-6Power-on Reset (105)

6-7Warm Reset (106)

6-8Example of Effect of Writing Into PLLCR Register (107)

6-9General-Purpose Output Timing (107)

6-10Sampling Mode (108)

6-11General-Purpose Input Timing (109)

6-12IDLE Entry and Exit Timing (110)

6-13STANDBY Entry and Exit Timing Diagram (111)

6-14HALT Wake-Up Using GPIOn (112)

6-15PWM Hi-Z Characteristics (113)

6-16ADCSOCAO or ADCSOCBO Timing (115)

6-17External Interrupt Timing (115)

6-18SPI Master Mode External Timing(Clock Phase=0) (118)

6-19SPI Master Mode External Timing(Clock Phase=1) (120)

6-20SPI Slave Mode External Timing(Clock Phase=0) (121)

6-21SPI Slave Mode External Timing(Clock Phase=1) (122)

6-22ADC Power-Up Control Bit Timing (124)

6-23ADC Analog Input Impedance Model (125)

6-24Sequential Sampling Mode(Single-Channel)Timing (126)

6-25Simultaneous Sampling Mode Timing (127)

List of Figures5

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TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER2003–REVISED SEPTEMBER2007

List of Tables

2-1Hardware Features(100-MHz Devices) (14)

2-2Hardware Features(60-MHz Devices) (15)

2-3Signal Descriptions (21)

3-1Addresses of Flash Sectors in F2809 (33)

3-2Addresses of Flash Sectors in F2808 (33)

3-3Addresses of Flash Sectors in F2806,F2802 (33)

3-4Addresses of Flash Sectors in F2801,F28015,F28016 (34)

3-5Impact of Using the Code Security Module (34)

3-6Wait-states (35)

3-7Boot Mode Selection (38)

3-8Peripheral Frame0Registers (43)

3-9Peripheral Frame1Registers (43)

3-10Peripheral Frame2Registers (44)

3-11Device Emulation Registers (44)

3-12PIE Peripheral Interrupts (46)

3-13PIE Configuration and Control Registers (47)

3-14External Interrupt Registers (47)

3-15PLL,Clocking,Watchdog,and Low-Power Mode Registers (49)

3-16PLLCR Register Bit Definitions (51)

3-17Possible PLL Configuration Modes (51)

3-18Low-Power Modes (53)

4-1CPU-Timers0,1,2Configuration and Control Registers (55)

4-2ePWM Control and Status Registers (57)

4-3eCAP Control and Status Registers (59)

4-4eQEP Control and Status Registers (62)

4-5ADC Registers (67)

4-6 3.3-V eCAN Transceivers (69)

4-7CAN Register Map (72)

4-8SCI-A Registers (74)

4-9SCI-B Registers (74)

4-10SPI-A Registers (77)

4-11SPI-B Registers (77)

4-12SPI-C Registers (78)

4-13SPI-D Registers (78)

4-14I2C-A Registers (81)

4-15GPIO Registers (83)

4-16F2808GPIO MUX Table (84)

6-1TMS320F2809,TMS320F2808Current Consumption by Power-Supply Pins at100-MHz SYSCLKOUT (93)

6-2TMS320F2806Current Consumption by Power-Supply Pins at100-MHz SYSCLKOUT (94)

List of Tables

6Submit Documentation Feedback

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TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER2003–REVISED SEPTEMBER2007 6-3TMS320F2802,TMS320F2801Current Consumption by Power-Supply Pins at100-MHz SYSCLKOUT (95)

6-4TMS320C2802,TMS320C2801Current Consumption by Power-Supply Pins at100-MHz SYSCLKOUT (96)

6-5Typical Current Consumption by Various Peripherals(at100MHz) (97)

6-6TMS320x280x Clock Table and Nomenclature(100-MHz Devices) (101)

6-7TMS320x280x Clock Table and Nomenclature(60-MHz Devices) (102)

6-8Input Clock Frequency (103)

6-9XCLKIN Timing Requirements-PLL Enabled (103)

6-10XCLKIN Timing Requirements-PLL Disabled (103)

6-11XCLKOUT Switching Characteristics(PLL Bypassed or Enabled) (103)

6-12Power Management and Supervisory Circuit Solutions (104)

6-13Reset(XRS)Timing Requirements (106)

6-14General-Purpose Output Switching Characteristics (107)

6-15General-Purpose Input Timing Requirements (108)

6-16IDLE Mode Timing Requirements (110)

6-17IDLE Mode Switching Characteristics (110)

6-18STANDBY Mode Timing Requirements (110)

6-19STANDBY Mode Switching Characteristics (111)

6-20HALT Mode Timing Requirements (111)

6-21HALT Mode Switching Characteristics (112)

6-22ePWM Timing Requirements (113)

6-23ePWM Switching Characteristics (113)

6-24Trip-Zone input Timing Requirements (113)

6-25High Resolution PWM Characteristics at SYSCLKOUT=(60-100MHz) (114)

6-26Enhanced Capture(eCAP)Timing Requirement (114)

6-27eCAP Switching Characteristics (114)

6-28Enhanced Quadrature Encoder Pulse(eQEP)Timing Requirements (114)

6-29eQEP Switching Characteristics (114)

6-30External ADC Start-of-Conversion Switching Characteristics (114)

6-31External Interrupt Timing Requirements (115)

6-32External Interrupt Switching Characteristics (115)

6-33I2C Timing (116)

6-34SPI Master Mode External Timing(Clock Phase=0) (117)

6-35SPI Master Mode External Timing(Clock Phase=1) (119)

6-36SPI Slave Mode External Timing(Clock Phase=0) (120)

6-37SPI Slave Mode External Timing(Clock Phase=1) (121)

6-38ADC Electrical Characteristics(over recommended operating conditions) (123)

6-39ADC Power-Up Delays (124)

6-40Current Consumption for Different ADC Configurations(at12.5-MHz ADCCLK) (124)

6-41Sequential Sampling Mode Timing (126)

6-42Simultaneous Sampling Mode Timing (127)

6-43Flash Endurance (129)

List of Tables7

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TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER2003–REVISED SEPTEMBER2007

6-44Flash Parameters at100-MHz SYSCLKOUT (129)

6-45Flash/OTP Access Timing (129)

6-46Minimum Required Flash/OTP Wait-States at Different Frequencies (130)

6-47ROM/OTP Access Timing (130)

6-48ROM/ROM(OTP area)Minimum Required Wait-States at Different Frequencies (130)

8-1F280x Thermal Model100-pin GGM Results (132)

8-2F280x Thermal Model100-pin PZ Results (132)

8-3C280x Thermal Model100-pin GGM Results (132)

8-4C280x Thermal Model100-pin PZ Results (132)

8-5F2809Thermal Model100-pin GGM Results (132)

8-6F2809Thermal Model100-pin PZ Results (133)

8Submit Documentation Feedback List of Tables

Revision History

TMS320F2809,TMS320F2808,TMS320F2806TMS320F2802,TMS320F2801TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER 2003–REVISED SEPTEMBER 2007

NOTE:Page numbers for previous revisions may differ from page numbers in the current version.

This data manual was revised from SPRS230I to SPRS230J.

This document has been reviewed for technical accuracy;the technical content is up to date as of the specified release date with the following changes:

Technical Changes Made for Revision J

Location

Additions,Deletions,Changes Section 2.1

Modified first paragraph in section on pin assignments Figure 2-3

Modified the TMS320F2802,TMS320F2801,TMS320C2802,TMS320C2801100-Pin PZ LQFP pinmap Figure 2-5

Added 2801x devices to title of pinmap for GGM and ZGM packages Table 2-3

Changed description of EPWM5A and EPWM6A Figure 3-5

Added a note to the 2802memory map Figure 3-6

Added a note to the 2801,2801x memory map Table 3-6

Modified Wait-states table Table 3-6

Modified section on ROM Section 3.2.10

Deleted part of note in section on security Section 3.2.19

Modified section on 32-bit CPU timers Figure 3-7

Modified External and PIE Interrupt Sources figure and added two paragraphs following figure Figure 4-2

Modified figure Section 4.3Deleted note in HRPWM section

Revision History 9元器件交易网bbad82442e3f5727a5e962a6

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TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER2003–REVISED SEPTEMBER2007

Revision History

10Submit Documentation Feedback

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1

F280x,F2801x,C280x DSPs

1.1

Features

TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER 2003–REVISED SEPTEMBER 2007

?

High-Performance Static CMOS Technology ?

Enhanced Control Peripherals –100MHz (10-ns Cycle Time)–Up to 16PWM Outputs

–60MHz (16.67-ns Cycle Time)

–Up to 6HRPWM Outputs With 150ps MEP Resolution

–Low-Power (1.8-V Core,3.3-V I/O)Design –Up to Four Capture Inputs

?JTAG Boundary Scan Support (1)

–Up to Two Quadrature Encoder Interfaces ?

High-Performance 32-Bit CPU (TMS320C28x)–Up to Six 32-bit/Six 16-bit Timers –16x 16and 32x 32MAC Operations ?

Serial Port Peripherals –16x 16Dual MAC

–Up to 4SPI Modules

–Harvard Bus Architecture –Up to 2SCI (UART)Modules –Atomic Operations

–Up to 2CAN Modules

–Fast Interrupt Response and Processing –One Inter-Integrated-Circuit (I2C)Bus –Unified Memory Programming Model ?

12-Bit ADC,16Channels

–Code-Efficient (in C/C++and Assembly)–2x 8Channel Input Multiplexer ?

On-Chip Memory

–Two Sample-and-Hold

–F2809:128K X 16Flash,18K X 16SARAM –Single/Simultaneous Conversions F2808:64K X 16Flash,18K X 16SARAM F2806:32K X 16Flash,10K X 16SARAM –Fast Conversion Rate:

F2802:32K X 16Flash,6K X 16SARAM 80ns -12.5MSPS (F2809only)F2801:16K X 16Flash,6K X 16SARAM 160ns -6.25MSPS (280x)F2801x:16K X 16Flash,6K X 16SARAM 267ns -3.75MSPS (F2801x)–1K x 16OTP ROM (Flash Devices Only)–Internal or External Reference –C2802:32K X 16ROM,6K X 16SARAM ?Up to 35Individually Programmable,

C2801:16K X 16ROM,6K X 16SARAM Multiplexed GPIO Pins With Input Filtering ?

Boot ROM (4K x 16)

?

Advanced Emulation Features

–With Software Boot Modes (via SCI,SPI,–Analysis and Breakpoint Functions CAN,I2C,and Parallel I/O)–Real-Time Debug via Hardware –Standard Math Tables ?

Development Support Includes

?

Clock and System Control

–ANSI C/C++Compiler/Assembler/Linker –Dynamic PLL Ratio Changes Supported –Code Composer Studio?IDE –On-Chip Oscillator

–DSP/BIOS?

–Watchdog Timer Module

–Digital Motor Control and Digital Power ?Any GPIO A Pin Can Be Connected to One of Software Libraries

the Three External Core Interrupts

?

Low-Power Modes and Power Savings

?Peripheral Interrupt Expansion (PIE)Block –IDLE,STANDBY,HALT Modes Supported That Supports All 43Peripheral Interrupts –Disable Individual Peripheral Clocks ?

128-Bit Security Key/Lock

?

Package Options

–Protects Flash/OTP/L0/L1Blocks

–Thin Quad Flatpack (PZ)

–Prevents Firmware Reverse Engineering –MicroStar BGA?(GGM,ZGM)?

Three 32-Bit CPU Timers

?

Temperature Options:

–A:-40C to 85C (PZ,GGM,ZGM)–S:-40C to 125C (PZ,GGM,ZGM)–Q:-40C to 125C (PZ)

(1)

IEEE Standard 1149.1-1990Standard Test Access Port and Boundary Scan Architecture

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.

Code Composer Studio,DSP/BIOS,MicroStar BGA,TMS320C28x,C28x,TMS320C2000are trademarks of Texas Instruments.eZdsp is a trademark of Spectrum Digital.

PRODUCTION DATA information is current as of publication date.Copyright ?2003–2007,Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.

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1.2Getting Started

TMS320F2809,TMS320F2808,TMS320F2806TMS320F2802,TMS320F2801TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER 2003–REVISED SEPTEMBER 2007This section gives a brief overview of the steps to take when first developing for a C28x device.For more detail on each of these steps,see the following:

?Getting Started With TMS320C28x?Digital Signal Controllers (literature number SPRAAM0).?C2000Getting Started Website (bbad82442e3f5727a5e962a6/c2000getstarted)

Step 1.Acquire the appropriate development tools

The quickest way to begin working with a C28x device is to acquire an eZdsp?kit for initial

development,which,in one package,includes:

?On-board JTAG emulation via USB or parallel port

?Appropriate emulation driver

?Code Composer Studio?IDE for eZdsp

Once you have become familiar with the device and begin developing on your own

hardware,purchase Code Composer Studio?IDE separately for software development and

a JTAG emulation tool to get started on your project.

Step 2.Download starter software

To simplify programming for C28x devices,it is recommended that users download and use

the C/C++Header Files and Example(s)to begin developing software for the C28x devices

and their various peripherals.

After downloading the appropriate header file package for your device,refer to the following

resources for step-by-step instructions on how to run the peripheral examples and use the

header file structure for your own software

?The Quick Start Readme in the /doc directory to run your first application.

?Programming TMS320x28xx and 28xxx Peripherals in C/C++Application Report

(literature number SPRAA85)

Step 3.Download flash programming software

Many C28x devices include on-chip flash memory and tools that allow you to program the

flash with your software IP.

?Flash Tools:C28x Flash Tools

?TMS320F281x Flash Programming Solutions (literature number SPRB169)

?Running an Application from Internal Flash Memory on the TMS320F28xx DSP (literature

number SPRA958)

Step 4.Move on to more advanced topics

For more application software and other advanced topics,visit the TI website at bbad82442e3f5727a5e962a6 or bbad82442e3f5727a5e962a6/c2000getstarted .

12F280x,F2801x,C280x DSPs Submit Documentation Feedback 元器件交易网bbad82442e3f5727a5e962a6

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2Introduction

TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER2003–REVISED SEPTEMBER2007

The TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801,TMS320F28015,

TMS320F28016,TMS320C2802,and TMS320C2801,devices,members of the TMS320C28x?DSP

generation,are highly integrated,high-performance solutions for demanding control applications.

Throughout this document,TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,

TMS320F2801,TMS320C2802,TMS320C2801,TMS320F28015,and TMS32028016are abbreviated as

F2809,F2808,F2806,F2802,F2801,F28015,F28016,C2802,and C2801,respectively.TMS320F28015

and TMS320F28016are abbreviated as F2801x.Table2-1provides a summary of features for each

device.

Submit Documentation Feedback Introduction13元器件交易网bbad82442e3f5727a5e962a6

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TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER2003–REVISED SEPTEMBER2007

Table2-1.Hardware Features(100-MHz Devices)

FEATURE F2809F2808F2806F2802F2801

Instruction cycle(at100MHz)10ns10ns10ns10ns10ns

18K18K

10K6K6K Single-access RAM(SARAM)(16-bit word)(L0,L1,M0,M1,(L0,L1,M0,M1,

(L0,L1,M0,M1)(L0,M0,M1)(L0,M0,M1)

H0)H0)

3.3-V on-chip flash(16-bit word)128K64K32K32K16K

On-chip ROM(16-bit word)–––––

Code security for on-chip flash/SARAM/OTP blocks Yes Yes Yes Yes Yes

Boot ROM(4K X16)Yes Yes Yes Yes Yes

One-time programmable(OTP)ROM

1K1K1K1K1K (16-bit word)

PWM outputs ePWM1/2/3/4/5/6ePWM1/2/3/4/5/6ePWM1/2/3/4/5/6ePWM1/2/3ePWM1/2/3

ePWM1A/2A/3A/ePWM1A/2A/ePWM1A/2A/

HRPWM channels ePWM1A/2A/3A ePWM1A/2A/3A

4A/5A/6A3A/4A3A/4A

32-bit CAPTURE inputs or auxiliary PWM outputs eCAP1/2/3/4eCAP1/2/3/4eCAP1/2/3/4eCAP1/2eCAP1/2

32-bit QEP channels(four inputs/channel)eQEP1/2eQEP1/2eQEP1/2eQEP1eQEP1

Watchdog timer Yes Yes Yes Yes Yes

12-Bit,16-channel ADC conversion time80ns160ns160ns160ns160ns

32-Bit CPU timers33333

Serial Peripheral Interface(SPI)SPI-A/B/C/D SPI-A/B/C/D SPI-A/B/C/D SPI-A/B SPI-A/B

Serial Communications Interface(SCI)SCI-A/B SCI-A/B SCI-A/B SCI-A SCI-A

Enhanced Controller Area Network(eCAN)eCAN-A/B eCAN-A/B eCAN-A eCAN-A eCAN-A

Inter-Integrated Circuit(I2C)I2C-A I2C-A I2C-A I2C-A I2C-A

Digital I/O pins(shared)3535353535

External interrupts33333

Supply voltage 1.8-V Core,3.3-V I/O Yes Yes Yes Yes Yes

100-Pin PZ Yes Yes Yes Yes Yes Packaging

100-Ball GGM,ZGM Yes Yes Yes Yes Yes

A:-40°C to85°C(PZ,GGM,ZGM)(PZ,GGM,ZGM)(PZ,GGM,ZGM)(PZ,GGM,ZGM)(PZ,GGM,ZGM)

Temperature options S:-40°C to125°C(PZ,GGM,ZGM)(PZ,GGM,ZGM)(PZ,GGM,ZGM)(PZ,GGM,ZGM)(PZ,GGM,ZGM)

Q:-40°C to125°C(PZ)(PZ)(PZ)(PZ)(PZ)

Product status(1)TMS TMS TMS TMS TMS

(1)See Section5.1,Device and Development Support Nomenclature for descriptions of device stages.

14Introduction

bbad82442e3f5727a5e962a6

2.1Pin Assignments

TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER2003–REVISED SEPTEMBER2007 Table2-2.Hardware Features(60-MHz Devices)

FEATURE F2802-60F2801-60F28016F28015

Instruction cycle(at60MHz)16.67ns16.67ns16.67ns16.67ns

6K6K6K6K Single-access RAM(SARAM)(16-bit word)

(L0,M0,M1)(L0,M0,M1)(L0,M0,M1)(L0,M0,M1)

3.3-V on-chip flash(16-bit word)32K16K16K16K

On-chip ROM(16-bit word)––––

Code security for on-chip flash/SARAM/OTP

Yes Yes Yes Yes blocks

Boot ROM(4K X16)Yes Yes Yes Yes

One-time programmable(OTP)ROM

1K1K1K1K (16-bit word)

PWM outputs ePWM1/2/3ePWM1/2/3ePWM1/2/3/4ePWM1/2/3/4

HRPWM channels ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A/4A ePWM1A/2A/3A/4A

32-bit CAPTURE inputs or auxiliary PWM

eCAP1/2eCAP1/2eCAP1/2eCAP1/2 outputs

32-bit QEP channels(four inputs/channel)eQEP1eQEP1--

Watchdog timer Yes Yes Yes Yes

No.of channels16161616

12-Bit ADC MSPS 3.75 3.75 3.75 3.75

Conversion time267ns267ns267ns267ns

32-Bit CPU timers3333

Serial Peripheral Interface(SPI)SPI-A/B SPI-A/B SPI-A SPI-A

Serial Communications Interface(SCI)SCI-A SCI-A SCI-A SCI-A

Enhanced Controller Area Network(eCAN)eCAN-A eCAN-A eCAN-A-

Inter-Integrated Circuit(I2C)I2C-A I2C-A I2C-A I2C-A

Digital I/O pins(shared)35353535

External interrupts3333

1.8-V Core, 1.8-V Core, 1.8-V Core, 1.8-V Core,

Supply voltage

3.3-V I/O 3.3-V I/O 3.3-V I/O 3.3-V I/O

100-Pin PZ Yes Yes Yes Yes Packaging

100-Ball GGM,ZGM Yes Yes Yes Yes

A:-40°C to85°C(PZ,GGM,ZGM)(PZ,GGM,ZGM)(PZ,GGM,ZGM)(PZ,GGM,ZGM)

Temperature options S:-40°C to125°C(PZ GGM,ZGM)(PZ,GGM,ZGM)(PZ,GGM,ZGM)(PZ,GGM,ZGM)

Q:-40°C to125°C(PZ)(PZ)(PZ)(PZ)

Product status(1)TMS TMS TMS TMS

(1)See Section5.1,Device and Development Support Nomenclature for descriptions of device stages.

The TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801,TMS320C2802,

TMS320C2801,TMS320F28015,and TMS320F28016100-pin PZ low-profile quad flatpack(LQFP)pin

assignments are shown in Figure2-1,Figure2-2,Figure2-3,and Figure2-4.The100-ball GGM and ZGM

ball grid array(BGA)terminal assignments are shown in Figure2-5.Table2-3describes the function(s)of

each pin.

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50494847464544434241403938373635343332313029282726

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GPIO0/EPWM1A T C K

T M S

T D I

G P I O 23/E Q E P 1I /S P I S T E C /S C I R X D B G P I O 22/E Q E P 1S /S P I C L K C /S C I T X D B

G P I O 11/E P W M 6B /S C I R X D B /E C A P 4G P I O 21/E Q E P 1B /S P I S O M I C /C A N R X B

X C L K O U T G P I O 20/E Q E P 1A /S P I S I M O C /C A N T X B G P I O 9/E P W M 5B /S C I T X D B /E C A P 3G P I O 7/E P W M 4B /S P I S T E D /E C A P 2

G P I O 19/S P I S T E A /S C I R X D B

G P I O 6/E P W M 4A /E P W M S Y N C I /E P W M S Y N C O G P I O 18/S P I C L K A /S C I T X D B

G P I O 5/E P W M 3B /S P I C L K D /E C A P 1G P I O 4/E P W M 3A

XRS

TRST V S S

V D D

V D D I O

G P I O 10/E P W M 6A /C A N R X B /A D C S O C B O

V S S

G P I O 8/E P W M 5A /C A N T X B /A D C S O C A O V D D

V S S

G P I O 17/S P I S O M I A /C A N R X B /T Z 6V SS

V SS V DD V DDIO

GPIO16/SPISIMOA/CANTXB/TZ5V DD2A18V SS2AGND V DDAIO

G P I O 12/T Z 1/C A N T X B /S P I S I M O B

V S S

V D D I O

G P I O 29/S C I T X D A /T Z 6

G P I O 33/S C L A /E P W M S Y N C O /A D C S O C B O G P I O 14T Z 3/S C I T X D B /S P I C L K B

V S S

V D D

V D D 1A 18

V S S 1A G N D

V S S A 2

V D D A 2

G P I O 15/T Z 4/S C I R X D B /S P I S T E B V S S A I O

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO13/TZ2/CANRXB/SPISOMIB

V DD3VFL

V SS

V DD

GPIO28/SCIRXDA/TZ5

V SS V SS V DD V SS V DDIO

GPIO26/ECAP3/EQEP2I/SPICLKB

TEST2

TEST1GPIO25/ECAP2/EQEP2B/SPISOMIB

XCLKIN

X1X2EMU1EMU0

GPIO24/ECAP1/EQEP2A/SPISIMOB

GPIO27/ECAP4/EQEP2S/SPISTEB

TDO G P I O 30/C A N R X A G P I O 31/C A N T X A A D C I N A 7

A D C I N A 6A D C I N A 5

A D C I N A 4

A D C I N A 3A D C I N A 2A D C I N A 1

A D C I N A 0

A D C L O

ADCINB0ADCINB1ADCINB2ADCINB3ADCINB4ADCINB5ADCINB6ADCINB7ADCREFIN ADCREFM ADCREFP ADCRESEXT GPIO34GPIO1/EPWM1B/SPISIMOD GPIO2/EPWM2A

GPIO3/EPWM2B/SPISOMID TMS320F2809,TMS320F2808,TMS320F2806TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER 2003–REVISED SEPTEMBER 2007

Figure 2-1.TMS320F2809,TMS320F2808100-Pin PZ LQFP (Top View)

Introduction

16Submit Documentation Feedback

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GPIO3/EPWM2B/SPISOMID GPIO0/EPWM1A GPIO2/EPWM2A

GPIO1/EPWM1B/SPISIMOD GPIO34ADCRESEXT ADCREFP ADCREFM ADCREFIN ADCINB7ADCINB6ADCINB5ADCINB4ADCINB3ADCINB2ADCINB1ADCINB0C K

M S

D I

P I O 23/E Q E P 1I /S P I S T E C /S C I R X D B P I O 22/E Q E P 1S /S P I C L K C /S C I T X D B

C L K O U T P I O 20/E Q E P 1A /S P I S I M O C P I O 9/E P W M 5B /S C I T X

D B /

E C A P 3

P I O 7/E P W M 4B /S P I S T E D /E C A P 2

P I O 19/S P I S T E A /S C I R X D B

P I O 6/E P W M 4A /E P W M S Y N C I /E P W M S Y N C O P I O 18/S P I C L K A /S C I T X D B

P I O 5/E P W M 3B /S P I C L K D /E C A P 1P I O 4/E P W M 3A

G P I O 30/C A N R X A

G P I O 31/C A N T X A D C I N A 7

A D C I N A 6

A D C I N A 5

A D C I N A 4

A D C I N A 3

A D C I N A 2

A D C I N A 1

A D C I N A 0A D C L O P I O 11/E P W M 6

B /S

C I R X

D B /

E C A P 4P I O 21/E Q E P 1B /S P I S O M I C

V SS

SS DD V DDIO

GPIO16/SPISIMOA/TZ5DD2A18SS2AGND V DDAIO

S S

D D

D D I O

P I O 10/E P W M 6A /A D C S O C B O

S S

P I O 8/E P W M 5A /A D C S O C A O D D

S S

P I O 17/S P I S O M I A T Z 6

G P I O 12T Z 1/S P I S I M O B G P I O 29/S C I T X D A T Z 6

G P I O 33/S C L A /E P W M S Y N C O A D C S O C B O

G P I O 14T Z 3/S C I T X D B /S P I C L K B

V D D

V D D 1A 18

V S S 1A G N D

V S S A 2

V D D A 2

G P I O 15T Z 4/S C I R X D B /S P I S T E B V S S A I O

V S S

V D D I O

V S S

TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER 2003–REVISED SEPTEMBER 2007

Figure 2-2.TMS320F2806100-Pin PZ LQFP (Top View)

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GPIO0/EPWM1A GPIO2/EPWM2A GPIO1/EPWM1B GPIO34ADCRESEXT ADCREFP ADCREFM ADCREFIN ADCINB7ADCINB6ADCINB5ADCINB4ADCINB3ADCINB2ADCINB1ADCINB0C K

M S

D I X C L K O U T G P I G P I XRS

TRST

S P I S I M O G P I O 29/G P I O 33/S C L A /E P W M S Y N C GPIO32/SDAA/EPWMSYNCI/ADSOCAO

SPISOMIB/GPIO13/TZ2

V DD3VFL (A)

V SS V DD GPIO28/SCIRXDA/TZ5

V SS V SS V DD P I O 21/E Q E P 1B

V S S

V D D

P I O 23/E Q E P 1I

P I O 22/E Q E P 1S

D D I O

P I O 10A D C S O C B O

G P I O 20/E Q E P 1A V S S

P I O 9

P I O 8A D C S O C A O V D D

P I O 7/E C A P 2

P I O 19/S P I S T E A P I O 6/E P W M S Y N C I /E P W M S Y N C O G P I O 11V S S

P I O 18/S P I C L K A P I O 5/E P W M 3B /E C A P 1

P I O 17/S P I S O M I A /T Z 6

G P I O 4/E P W M 3A

V SS

V SS V DD V DDIO

GPIO16/SPISIMOA/TZ5GPIO3/EPWM2B V DD2A18V SS2AGND V DDAIO

S P I C L K S P I S T E V SS

V DDIO

SPISIMOB/GPIO24/ECAP1

SPICLKB/GPIO26

TEST2

TEST1XCLKIN

X1X2EMU1EMU0

TDO TMS320F2809,TMS320F2808,TMS320F2806TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER 2003–REVISED SEPTEMBER 2007

A.

On the C280x devices,the V DD3VFL pin is V DDIO .

Figure 2-3.TMS320F2802,TMS320F2801,TMS320C2802,TMS320C2801100-Pin PZ LQFP

(Top View)

Introduction

18Submit Documentation Feedback

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504948474645444342414039383736353433323130292827

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GPIO0/EPWM1A GPIO2/EPWM2A GPIO1/EPWM1B GPIO34ADCRESEXT ADCREFP ADCREFM ADCREFIN ADCINB7ADCINB6ADCINB5ADCINB4ADCINB3ADCINB2ADCINB1ADCINB0T C K

T M S

T D I X C L K O U T G P I O 30/C A N R X A

G P I O 31/C A N T X A A D C I N A 7

A D C I N A 6

A D C I N A 5

A D C I N A 4

A D C I N A 3

A D C I N A 2

A D C I N A 1

A D C I N A 0

A D C L O TRST G P I O 12T Z 1

V S S

V D D I O

G P I O 29/S C I T X D A /T Z 6

G P I O 33/S C L A /E P W M S Y N C O /A D C S O C B O G P I O 14/T Z 3V S S

V D D

V D D 1A 18

V S S 1A G N D

V S S A 2

V D D A 2

GPIO32/SDAA/EPWMSYNCI/ADSOCAO

GPIO13/TZ2V DD3VFL (A)

V SS

V DD GPIO28/SCIRXDA/TZ5

V SS V SS V DD G P I O 21

V S S

V D D

G P I O 23

G P I O 22V D D I O

G P I O 10/A D C S O C B O

G P I O 20V S S

G P I O 9

G P I O 8A D C S O C A O V D D

G P I O 7/E P W M 4B /E C A P 2

G P I O 19/S P I S T E A

G P I O 6/E P W M 4A /E P W M S Y N C I /E P W M S Y N C O G P I O 11V S S

G P I O 18/S P I C L K A G P I O 5/E P W M 3B /E C A P 1

G P I O 17/S P I S O M I A /T Z 6

G P I O 4/E P W M 3A

V SS

V SS V DD V DDIO

GPIO16/SPISIMOA/TZ5GPIO3/EPWM2B V DD2A18V SS2AGND V DDAIO

G P I O 15T Z 4

V SS GPIO27V DDIO

GPIO24/ECAP1

V S S A I O

GPIO25/ECAP2

GPIO26

TEST2

TEST1XCLKIN

X1X2EMU1EMU0

TDO TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801

TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER 2003–REVISED SEPTEMBER 2007

A.CANTXA (pin 7)and CANRXA (pin 6)pins are not applicable for the TMS320F28015.

Figure 2-4.TMS320F2801x 100-Pin PZ LQFP

(Top View)

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Introduction 19

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Bottom View

TMS320F2809,TMS320F2808,TMS320F2806TMS320F2802,TMS320F2801TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER 2003–REVISED SEPTEMBER 2007Figure 2-5.TMS320F2809,TMS320F2808,TMS320F2806,TMS320F2802,TMS320F2801,TMS320F28016,TMS320F28015,TMS320C2802,TMS320C2801

100-Ball GGM and ZGM MicroStar BGA?(Bottom View)

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2.2Signal Descriptions

TMS320F2809,TMS320F2808,TMS320F2806

TMS320F2802,TMS320F2801 TMS320C2802,TMS320C2801,and TMS320F2801x DSPs

SPRS230J–OCTOBER2003–REVISED SEPTEMBER2007

Table2-3describes the signals on the280x devices.All digital inputs are TTL-compatible.All outputs are

3.3V with CMOS levels.Inputs are not5-V tolerant.

Table2-3.Signal Descriptions

PIN NO.

GGM/

NAME DESCRIPTION(1)

PZ

ZGM

PIN#

BALL#

JTAG

JTAG test reset with internal pulldown.TRST,when driven high,gives the scan system control of

the operations of the device.If this signal is not connected or driven low,the device operates in its

functional mode,and the test reset signals are ignored.

NOTE:Do not use pullup resistors on TRST;it has an internal pull-down device.TRST is an active

high test pin and must be maintained low at all times during normal device operation.In a low-noise TRST84A6

environment,TRST may be left floating.In other instances,an external pulldown resistor is highly

recommended.The value of this resistor should be based on drive strength of the debugger pods

applicable to the design.A2.2-k?resistor generally offers adequate protection.Since this is

application-specific,it is recommended that each target board be validated for proper operation of

the debugger and the application.(I,↓)

TCK75A10JTAG test clock with internal pullup(I,↑)

JTAG test-mode select(TMS)with internal pullup.This serial control input is clocked into the TAP TMS74B10

controller on the rising edge of TCK.(I,↑)

JTAG test data input(TDI)with internal pullup.TDI is clocked into the selected register(instruction TDI73C9

or data)on a rising edge of TCK.(I,↑)

JTAG scan out,test data output(TDO).The contents of the selected register(instruction or data) TDO76B9

are shifted out of TDO on the falling edge of TCK.(O/Z8mA drive)

Emulator pin0.When TRST is driven high,this pin is used as an interrupt to or from the emulator

system and is defined as input/output through the JTAG scan.This pin is also used to put the

device into boundary-scan mode.With the EMU0pin at a logic-high state and the EMU1pin at a

logic-low state,a rising edge on the TRST pin would latch the device into boundary-scan mode.

EMU080A8(I/O/Z,8mA drive↑)

NOTE:An external pullup resistor is recommended on this pin.The value of this resistor should be

based on the drive strength of the debugger pods applicable to the design.A2.2-k?to4.7-k?

resistor is generally adequate.Since this is application-specific,it is recommended that each target

board be validated for proper operation of the debugger and the application.

Emulator pin1.When TRST is driven high,this pin is used as an interrupt to or from the emulator

system and is defined as input/output through the JTAG scan.This pin is also used to put the

device into boundary-scan mode.With the EMU0pin at a logic-high state and the EMU1pin at a

logic-low state,a rising edge on the TRST pin would latch the device into boundary-scan mode.

EMU181B7(I/O/Z,8mA drive↑)

NOTE:An external pullup resistor is recommended on this pin.The value of this resistor should be

based on the drive strength of the debugger pods applicable to the design.A2.2-k?to4.7-k?

resistor is generally adequate.Since this is application-specific,it is recommended that each target

board be validated for proper operation of the debugger and the application.

FLASH

3.3-V Flash Core Power Pin.This pin should be connected to3.3V at all times.On the ROM

V DD3VFL96C4

parts(C280x),this pin should be connected to V DDIO.

TEST197A3Test Pin.Reserved for TI.Must be left unconnected.(I/O)

TEST298B3Test Pin.Reserved for TI.Must be left unconnected.(I/O)

CLOCK

Output clock derived from SYSCLKOUT.XCLKOUT is either the same frequency,one-half the

frequency,or one-fourth the frequency of SYSCLKOUT.This is controlled by the bits1,0 XCLKOUT66E8(XCLKOUTDIV)in the XCLK register.At reset,XCLKOUT=SYSCLKOUT/4.The XCLKOUT signal

can be turned off by setting XCLKOUTDIV to3.Unlike other GPIO pins,the XCLKOUT pin is not

placed in high-impedance state during a reset.(O/Z,8mA drive).

External Oscillator Input.This pin is to feed a clock from an external3.3-V oscillator.In this case, XCLKIN90B5the X1pin must be tied to GND.If a crystal/resonator is used(or if an external1.8-V oscillator is

used to feed clock to X1pin),this pin must be tied to GND.(I)

(1)I=Input,O=Output,Z=High impedance,OD=Open drain,↑=Pullup,↓=Pulldown

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