质量和可靠性(IBM)

可靠性

ASIC Products Application Note

IBM

Quality and Reliability

Revision 3

SA14-2280-03

可靠性

IBM

Notices:

Beforeusingthisinformationandtheproductitsupports,besuretoreadthegeneralinformationontheback cover of this application note.

Trademarks:

ThefollowingaretrademarksorregisteredtrademarksofInternationalBusinessMachinesCorporationinthe United States, or other countries, or both:

IBM

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Other company, product, or service names may be trademarks or service marks of others.

© International Business Machines Corporation 1999. All rights reserved.

可靠性

ASIC Products Application Note

Quality and Reliability

Abstract

Superior integrated circuit device reliability is attained when it is an integral part of process development,design,andmanufacturing.ThisapplicationnotedescribesthemethodologyusedbyIBMtoachieverobustASICdesignsbeforemarketintroduction,andtoensurehighqualityandreliabilityduringvolumeproduction.

Introduction

The typical time distribution of reliability failures is described by the “bathtub” curve shown in Figure 1. Thecurveisdividedintothreesegments:aninfantmortalityperiod,markedbyarapidlydecreasingfailurerate;astable,usefullifeperiod,wherethefailureratecontinuestodecrease;andaperiodofincreasingfailureraterepresenting the onset of product wear-out. Infant mortality and useful life failures are caused by defectsintroduced during the manufacturing process. Defective components are removed by efficient reliability

screens.Wear-outfailuresareavoidedbycarefultechnologydevelopmentandproductdesign,andbyusingeffective process monitors during production.Figure 1. Bathtub Curve

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ASIC Products Application NoteReliability fails are a combination of three problem types: wear-out mechanisms, which shorten useful life;systematic defects caused by process variation beyond acceptable limits; and random defects created byprocess deficiencies. IBM manages all three problem types by emphasizing reliability in all design proce-dures. Early design and qualification activities eliminate wear-out failure mechanisms (such as hot carriersand electromigration) and establish technology and process limits that minimize design sensitivity to manu-facturing defects. Process control and tooling improvements, combined with efficient burn-in and Maverickscreens, provide continuous defect reduction. Attributes of the IBM reliability management system are sum-marized in Table 1.

Table 1.Reliability Management System

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AnoverviewoftheIBMqualificationprocess,fromtechnologyinceptiontofullproduction,isshowninTable2.

Table 2.IBM Quali cation Process

Reliability management begins with the start of a new technology, when design models are developed andusedtoevaluatenewfeatures,andreliabilityteststructuresaredefined.Acceleratedtestsareperformedtoinvestigatepotentialwear-outmechanisms,includinghotcarriers,dielectricintegrity,ionicsandtemperaturestability, mechanical stability, stress-induced metal voiding, and electromigration. The technology qualifica-tion process (T0, T1) establishes adequate control of wear-out mechanisms. Stress results are utilized todefine the chip and technology design ground rules, application specification limits, and process controlsrequired to avoid wear-out. Wafer screen and burn-in design requirements are verified.

Upon successful completion of the technology qualification phase, early component samples are subjectedtoafullseriesoftests(T2).Theseincludefunctionalityteststoevaluateelectricalperformanceandtodefinetest margins, functional and environmental stresses to measure product reliability, mechanical tests to eval-uate the package fitness for use, and tests to evaluate product robustness against latch-up, soft errors, andelectrostatic discharge (ESD).

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ASIC Products Application Notepriate process and design engineering areas with the goal of eliminating all failure mechanisms.

Withnewtechnologies,productfunctionalstressesareconductedatmultiplevoltageandtemperaturecondi-tions to develop acceleration models. These models are then used to predict product reliability performancecompared to program objectives. The acceleration model development process is shown schematically inFigure 2.

Figure 2. Acceleration Model Development Process

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hardware test evaluation. The objective of this evaluation is to confirm that the product has adequate perfor-mance margins over the application specification limits. A list of qualification tests used by IBM is shown inTable 3.Table 3.

IBM Component Quali cation Tests

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ASIC Products Application NoteAcceleration Factors

Product reliability data is typically composed of several different failure mechanisms which may contributefailuresdifferentlyasafunctionofvoltageandtemperature.Whenprojectingreliabilityperformanceatactualuse conditions from accelerated test data, the contribution of individual defect mechanisms with unique volt-ageandtemperaturekineticsbehaviormustbeacknowledged.Thisisparticularlyimportantwhentheaccel-erated stress failure mix includes mechanisms with relatively low acceleration. In the absence of such

mechanisms, it is common practice to use voltage and temperature acceleration factors which combine allmechanisms into a composite model. Temperature acceleration for semiconductor failure mechanisms isusually determined by the Arrhenius equation:

AFT= exp[(Ea/k) x (1/Tu - 1/Ts)]

where: k is Boltzmann’s constant (8.617e-5 eV/ K)

Tuand Ts are use and stress temperatures, expressed in KEa is the activation energy in eV.

Frommodelingevaluationsconductedduringourproductqualifications,voltageaccelerationisdescribedby:

AFV = exp(β x (Vs - Vu))

where: Vs and Vu are stress and use voltages, expressed in volts

βis the voltage acceleration term in 1/V.

Voltageandtemperatureaccelerationconstantshavebeendeterminedthroughmultipleproductevaluationsand are summarized in the table shown below.

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ASIC Products Application Note

Failure rates at use conditions are calculated from accelerated stress data by converting the data to equiva-lentusehoursusingstresstimeandthevoltageandtemperatureaccelerationfactorspreviouslydescribed.Theseestimatesofequivalentusehoursarewellbeyondtheend-of-lifehoursassociatedwithmostapplica-tions when assuming an exponential distribution. The relationship between failure rate (expressed in FITs)and the Chi-squared distribution is shown in the equations that follow.

λ = (χ2 x 109) / (2 x D.H.)where:λ = failure rate

D.H. = device-hours representing equivalent use hours (sample size x stress time in hours x AFT x AFV)χ2 = the Chi-Squared distribution for a

given confidence interval =χ2(α, d.f.) where:

α = the Chi-squared confidence intervald.f. = degrees of freedom (2r + 2)r = number of observed failures

Failureratecalculationsfordatashowninthisreportareperformedfora60 Cjunctiontemperatureata60%confidencelevel.Chi-squaredvaluesforuptofiveproductfailuresat60%and90%confidenceintervalsareshown in the table below.

Product Reliability

IBM CMOS design systems offer three reliability levels: Grade 1, Grade 2, and Grade 3. (Grade 1 has thelowest failure rates.) The different grades of reliability are achieved through the use of process screens andburn-in. Higher reliability drives increased manufacturing cost; therefore, reliability testing and burn-in areexercised only to meet specific customer requirements.

The reliability objectives of the CMOS design system products are fully competitive with similar products inthe semiconductor industry. Contact your IBM representative for more information on product reliabilityunder specific operating conditions not covered in Table 4 on page 9. The three reliability grades areintended to provide our customers with the choice of reliability required for their application.

CMOS 5S ASIC products have been designed and qualified with model simulations and hardware stressestoprovideausefullifeperiodofatleast100,000power-onhours(POH)at150MHzand100 Cjunctiontem-perature (Tj). Longer useful life periods are possible at derated operating frequency and temperature. Oper-

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ASIC Products Application Notederating curve does not include the effect of burn-in that can reduce useful life by as much as 10,000 POH.Applicationsexceedingthemaximumoperatingfrequencyforthedesiredusefullifeperiodrequireadditionalanalysisandmayrequireuniquedesignandtestguardbandsthatcanresultinnonrecurringexpense(NRE)chargesorunit-costadders.Theusefullifeperiodmayalsobeaffectedbyagivenpackagetypebecauseofthe operating temperature, frequency limits, and reliability grades offered in that package.Figure 3. IBM CMOS Product Reliability Derating Curves

Burn-In

All Grade 1 IBM ASICs are screened by in-situ burn-in (for example, dynamic stress with functional tests tomonitor outputs while devices are undergoing burn-in). All failures occurring during burn-in, including thoseat high voltage and temperature conditions, are identified. In-situ burn-in is highly efficient, ensures productfunctionality at the burn-in conditions, finds equipment or contact problems (if they arise), and identifies

uniquefailuresduringstress.Becauseitprovidesreliabilityinformationforeachproductionlot,in-situburn-inis an important part of the Maverick control strategy.

Along with effective design-for-reliability and process control practices, in-situ burn-in enables IBM to

achieve exceptionally good ASIC reliability. Early-life behavior is dominated by burn-in escapes (for exam-ple,failureswhich,forequipmentandotherreasons,escapethefullburn-inprocessbutareminimizedbyin-situ burn-in).

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predefinedsubsetsofpins.Forexample,allburn-insignalsmustbeplacedwithinasetof64specificmodulepinsidentifiedoneachmodulesize.Ifaparticulardesignisunabletomeettheconstraintforusingstandardburn-inboards,thereliabilityissupportedwithcustomboardsatahighercostandpossiblydelayedproductshipment.

a.Assumptions:40KPOH,1250on/offcycles,andachiptemperatureof60 C.Thistabledoesnot

include the card attach failure rate.b.c.

Early Failure Rate (0.0 hours to one year of use).

FailuresinTime;equivalenttoPPM/KPOH.ValuesinthistablearereferencedtoTjof60 Candnominal voltage.

d.Average Failure Rate (0.0 hours to 40,000 Power on Hours) in FITs.

e.Reliability grade 2 is not available on SA-12, SA-12E, SA-27, and SA-27E without eDRAM tech-nologies.f.

Burn-inmayberequiredforASICsthatcontainembeddedDRAMtoachievecustomerreliabilityobjectives.AdditionaltechnicaldataisrequiredtodeterminetheaccurateFITrateforASICwithembeddedDRAM.IBMwillbeworkingjointlywiththecustomertodeterminetheactualFITratewith and without burn-in.

Figure 4 shows the effect of Power on Hours and junction temperature on reliability. (Note that the x-factorsare in parts per million (PPM).)

Figure 4. Reliability X-Factors in PPM for Selected Power on Hours and Junction Temperature

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ASIC Products Application Note1.VoltageScreenatwafer naltest.Voltagescreenimprovesreliabilityandmaybeimplementeddifferentlyto satisfy different reliability requirements. Both dynamic and enhanced voltage screens are applied.2.In-situ burn-in uses ABIST, LBIST or WRP methodology for Grade 1 and Grade 2 reliability offerings.Grade 1 reliability requires greater than 99.2 percent logic-node toggle and 100 percent array-node tog-gle. Grade 2 reliability requires greater than 94 percent logic-node toggle and 100 percent array-nodetoggle.3.In-line and BEOL Maverick Controls are used for the Grade 1 reliability offering; a reduced Maverickscreen may be used for the Grade 2 and Grade 3 reliability offerings.4.BTV Site Group C Strategy will be followed.

5.IDD screens will be implemented at both wafer and module test. An IDD test input must be provided toinhibit any functional current during this test. It is possible for customers to design unique dc currentbooks.6.WaferandmodulethermalcycleforGrade1andGrade2reliabilityproducts.Onlywaferthermalcycleisavailable for Grade 3 reliability.

Quality Monitor Program

Onceinfullproduction,productchipandassemblytestmonitorsareestablishedtoprovideanongoingmea-surement of line quality. Samples are drawn from products representing each major process and packagingtechnology. A quarterly report summarizing monitor results is available upon request. IBM uses the data tomeasure overall product quality and reliability problems, and to verify corrective actions.

Process/Design Requali cation

Requalification is required whenever major process or design changes occur, and appropriate tests andstresses are performed. Figure 5 on page 11 summarizes the requalification process. All changes are

reviewed by a Technical Review Board (TRB) for potential impacts to the product form, fit, function, or reli-ability.

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ASIC Products Application Note

Figure 5. Process/Design Requali cation Process

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ASIC Products Application NoteIn-line and end-of-line critical parameters have been established to measure and control manufacturingoperations that may affect quality and reliability performance. Parametric trends are routinely monitored viaStatisticalProcessControl(SPC),andcorrectiveactionsaretakenasrequired.AcomprehensivesystemofMaverick limits has also been defined that detects systematic process and defect problems with known orpossibleadversereliabilityorqualityimpact,andprovidesappropriatedispositionofproductcontainingsuchproblems. These actions help drive continuous improvements in process control, which in turn, result in bet-ter quality. The Maverick control process is summarized in Figure 6 on page 13. A diagram illustrating theuse of in-situ burn-in data for Maverick control follows in Figure 7 on page 14.

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Figure 6. Maverick Control Process

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ASIC Products Application NoteFigure 7. In-Situ Burn-In for the Maverick Control Process

Customer Feedback

The customer feedback process is a key component of the IBM quality program. IBM semiconductor manu-facturingfacilitieshavealonghistoryofworkingcloselywithcardandsystemmanufacturingsites.Thisfeed-back helps IBM attain and maintain higher-quality, reliable products.

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Summary

Device reliability is an integral part of IBM’s process development, design, and manufacturing. The method-ology, described in this application note, explains how IBM achieves reliable and high-quality, robust ASICdesigns.

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IBM

®

© International Business Machines Corporation 1999Printed in the United States of America 12/8/9912/8/99

All Rights Reserved

All information contained in this document is subject to change without notice. The products described in this document are NOTintended for use in implantation or other life support applications where malfunction may result in injury or death to persons. Theinformation contained in this document does not affect or change IBM’s product speci cations or warranties. Nothing in this docu-ment shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. Allinformation contained in this document was obtained in speci c environments, and is presented as illustration. The resultsobtained in other operating environments may vary.

THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will IBM be liable forany damages arising directly or indirectly from any use of the information contained in this document.IBM Microelectronics Division1580 Route 52, Bldg. 504

Hopewell Junction, NY 12533-6531The IBM home page can be found at

The IBM Microelectronics Division home page can be found at Document No. SA14-2280-03

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