SKEA128PB

Freescale SemiconductorProduct Brief

Document Number:SKEA128PBRev 1.1, 02/2014

Supports all SKEA128 devices

Product Brief

Contents

1Kinetis EA series

Kinetis EA series provide the highly scalable portfolio ofARM? Cortex?-M0+ MCUs in the automotive industry. With2.7–5.5 V supply and focus on exceptional EMC/ESD

robustness, Kinetis EA series devices are well suited to a widerange of applications in electrical harsh environments, and isoptimized for cost-sensitive applications offering low pin-count option. The Kinetis EA series offers a broad range ofmemory, peripherals, and package options. They sharecommon peripherals and pin counts allowing developers tomigrate easily within an MCU family or among the MCUfamilies to take advantage of more memory or feature

integration. This scalability allows developers to standardizeon the Kinetis EA series for their end product platforms,maximising hardware and software reuse and reducing time-to-market.

Following are the general features of the Kinetis EA seriesMCUs.

?32-bit ARM Cortex-M0+ core

?Scalable memory footprints from 8 KB flash / 1 KBSRAM to 128 KB flash / 16 KB SRAM

?Precision mixed-signal capability with on chip analogcomparator and 12-bit ADC

?Powerful timers for a broad range of applicationsincluding motor control

?Serial communication interfaces such as UART, SPI,I2C, and others.

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Kinetis EA series.......................................................1KEA128 sub-family introduction.............................2Block diagram...........................................................3Features.....................................................................4

KEA128 sub-family introduction?High security and safety with internal watchdog and programmable CRC module

?Single power supply (2.7–5.5 V) with full functional flash program/erase/read operations?Ambient operation temperature range: –40 °C ~ 125 °C

Kinetis EA series MCU families are supported by a market-leading enablement bundle from Freescale and numerous ARMthird-party ecosystem partners. The KEA128 can be running at 48 MHz and is pin-compatible within EA series and with theFreescale's 8-bit S08RN family.

2KEA128 sub-family introduction

This sub-family includes a powerful array of analog, communication, and timing and control peripherals with specific flashmemory size and the pin count.?Core and architecture:

?ARM Cortex-M0+ core running up to 48 MHz at 125 °C with zero wait state execution from memories

?Single-cycle access to I/O: Up to 50 percent faster than standard I/O, improves reaction time to externalevents allowing bit manipulation and software protocol emulation

?Two-stage pipeline: Reduced number of cycles per instruction (CPI), enabling faster branch instruction andISR entry, and reducing power consumption

?Excellent code density in comparison to 8-bit and 16-bit MCUs: Reduced flash size, system cost, andpower consumption

?Optimized access to program memory: Accesses on alternate cycles reduces power consumption?100 percent compatible with ARM Cortex-M0 and a subset ARM Cortex-M3/M4: Reuse existingcompilers and debug tools

?Simplified architecture: 56 instructions and 17 registers enable easy programming and efficient packagingof 8/16/32-bit data in memory

?Linear 4 GB address space removes the need for paging/banking, reducing software complexity?ARM third-party ecosystem support: Software and tools to help minimize development time/cost?Bus clock running up to 24 MHz

?Bit-band: Enhanced SRAM bit operation by aliased SRAM bit-band region with Cortex-M0+ core

?BME: Bit manipulation engine reduces code size and cycles for bit-oriented operations to peripheral registers andSRAM memory eliminating traditional methods where the core would need to perform read-modify-writeoperations.

?Power-saving:

?Low-power ARM Cortex-M0+ core with excellent energy efficiency?Supports three power modes: Run, Wait and Stop

?Supports clock gating for unused modules, and specific peripherals remain working in Stop mode?Memory:

?Up to 128 KB program flash, 16 KB SRAM

?Embedded 32 B flash cache for optimizing bus bandwidth and flash execution performance?Support bit operation on SRAM domain through aliased bit-band region or BME?Clocks

?Oscillator (OSC) - supports 32.768 kHz crystal or 4 MHz to 24 MHz crystal or ceramic resonator; choice of lowpower or high gain oscillators

?Internal clock source (ICS) - internal FLL with internal or external reference, 37.5 kHz pretrimmed internalreference for 48 MHz system clock

?Internal 1 kHz low-power oscillator (LPO)?Mixed-signal analog:

?Up to 16 channels of 12-bit analog-to-digital conversion (ADC) with 2.5 μs conversion time, 1.7 mV/°Ctemperature sensor, internal bandgap reference channel, supporting automatic compare, optional hardwaretrigger, and operating in Stop mode

?Up to two analog comparators (ACMP) with both positive and negative inputs, separately selectable interrupt onrising and falling comparator output

?Human-machine interface (HMI):

?Up to two 32-bit keyboard interrupt modules (KBI)

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Block diagram?Connectivity and communications:

?Up to three serial communications interface (UART) modules with optional 13-bit break, full duplex non-returnto zero (NRZ) and LIN extension support

?Up to two serial peripheral interface (SPI) modules with full-duplex or single-wire bidirectional and master orslave mode

?Up to two Inter-integrated circuit ( I2C) modules with support of system management bus and I2C0 supports 4-wire interface feature

?One Freescale's scalable controller area network (MSCAN) conforming to CAN2.0A/B specification?Reliability, safety and security:

?Internal watchdog with independent clock source

?Cyclic redundancy check (CRC) with programmable 16- or 32-bit polynomial generator?Timing and control:

?FlexTimer module (FTM) including one 6-channel FTM with deadtime insertion and fault detection, and up totwo 2-channel FTMs backward compatible with TPM modules. Each channel can be configured for inputcapture, output compare, edge- or center-aligned PWM mode.

?Periodic interrupt timer (PIT) for RTOS task scheduler time base or trigger source for ADC conversion and timermodules

?16-bit pulse width timer (PWT) for positive, negative and period capture with selectable driving clock?FTM and PWT modules support separate timer clock from core and bus, up to 48 MHz?16-bit real timer counter (RTC)?I/O and package:

?Up to 71 GPIO pins with interrupt functionality?Up to 2 true open-drain output pins

?Up to 8 high current drive pins supporting 20 mA source/sink current?Multiple package options from 64-pin to 80-pinThe family acts as a low-power, high-robustness, and cost-effective microcontroller to provide developers an appropriateentry-level 32-bit solution. The family is next generation MCU solution with enhanced EMC/ESD performance for cost-sensitive, high-reliability devices applications used in high electrical noise environments.

3Block diagram

The following figure shows a superset block diagram of the device. Other devices within the family have a subset of thefeatures.

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FeaturesKinetis KEA128 Family

??ARM Cortex -M0+CoreSystemWatchdogMemories and Memory InterfacesFlashClocksFrequency-locked loopInternaloscillatorSerial wiredebug interfacesNVICBMERAM InternalreferenceclocksSecurityand IntegrityCRCx1Analog12-bit ADCx1TimersFTMs2x2ch 1x6chCommunication Human-MachineInterface (HMI)InterfacesICx2UARTx3SPIx2MSCANx12GPIOsACMPx2PITx1KBIx2RTCx1PWTx1Figure 1. KEA128 family block diagram4Features

4.1Feature summary

All devices within the KEA128 sub-family have a minimum of the following features.

Table 1.Common features among all KEA128 devicesOperating characteristics?2.7 V to 5.5 V?Temperature range (TA) -40 °C to 125 °C?Three operation modes: Run, Wait, Stop?Next generation 32-bit ARM Cortex M0+ coreTable continues on the next page...Core featuresProduct Brief, Rev 1.1, 02/2014

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FeaturesTable 1.Common features among all KEA128 devices (continued)?Supports up to 32 interrupt request sources?Nested vectored interrupt controller (NVIC)?2-pin serial wire debug (SWD) interfaceSystem and power management?Watchdog?Integrated bit manipulation engine (BME)?Power management controller with three differentpower modes?Non-maskable interrupt (NMI)?80-bit unique identification (ID) number?External crystal oscillator or resonator?Up to DC-48 MHz external square wave input clock?Internal clock references?31.25–39.063 kHz oscillator?1 kHz oscillator?Frequency-locked loop with the range of?40–50 MHz?Up to 128 KB flash memory?Up to 16 KB SRAM?Watchdog (WDOG)?Cyclic redundancy check (CRC) module?One 12-bit analog-to-digital converter (ADC)?Two analog comparators (ACMP) with internal 6-bitdigital-to-analog converter (DAC)?????One 6-channel and two 2-channel 16-bit FTM modules32-bit programmable interrupt timer (PIT)Pulse width timer (PWT)Real-time clock (RTC)System tick timer (SYSTICK)ClocksMemory and memory interfacesSecurity and integrityAnalogTimersCommunications?Two serial peripheral interfaces (SPI)?Two inter-integrated circuit (I2C) modules?Three universal asynchronous receiver/transmitter(UART) modules?One Freescale's scalable controller area network(MSCAN) module?Up to 71 GPIO pins?Up to two 32-bit keyboard interface (KBI) modules?Interrupt (IRQ)Human-machine interface4.2Memory and package options

The following table summarizes the memory and package options for the KEA128 family. All devices which share acommon package are pin-for-pin compatible.

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FeaturesTable 2.KEA128 family summaryPerformance (MHz)Memory64 QFP (10x10)Flash (KB)Package80 LQFP(14x14)++Sub-FamilyKEA1284864128SRAM(KB)816++4.3Part numbers and packaging

Q KEA A C FFF M T PP (N)

Qualification status

Tape and Reel (T&R)

FamilyKey attributeCAN available

Flash size

Package identifier

Temperature range (°C)Maskset revision

Figure 2. Part numbers diagramsTable 3.Part number field descriptionFieldQKEAACFFFMTPPNQualification statusKinetis E automotive familyKey attributeCAN availabilityProgram flash memory sizeMaskset revisionTemperature range (°C)Package identifierPackaging typeDescriptionValues?S = Automotive Qualified?P = Prequalification?KEA?Z = Cortex-M0+?N = CAN not available?(Blank) = CAN available?64 = 64 KB?128 = 128 KB?F0 = 1st Fab version?F1 = Revision after 1st version?M = –40 to 125?LH = 64 LQFP (10 mm x 10 mm)?LK = 80 LQFP (14 mm x 14 mm)?R = Tape and reel?(Blank) = TraysProduct Brief, Rev 1.1, 02/2014

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Features4.4KEA128 family features

The following sections list the differences among the various devices available within the KEA128 family.The features listed below each part number specify the maximum configuration available on that device. The signalmultiplexing configuration determines which modules can be used simultaneously.

4.4.1KEA128 family features (48 MHz performance)

The following table lists the differences among the various devices available within the KEA128 family. The features listedbelow each part number specify the maximum configuration available on that device. The signal multiplexing configurationdetermines which modules can be used simultaneously.

Table 4.KEA128 48 MHz performance tableSKEAZ128AMLH(R)SKEAZ128AMLK(R)48 MHz80LQFP128 KB16 KB--YES-YESYES-YESFLLYESYESYESSKEAZ64AMLH(R)SKEAZ64AMLK(R)48 MHz80LQFP64 KB8 KB--YES-YESYES-YESFLLYESYESYESSC part numberGeneralCPU frequencyPin countPackageFlashSRAMEEPROMROMDebug-SWDMTBWatchdog /w ind. clockPMCDMABME (bit manipulation engine)ICSMain OSC (32 kHz, 4-20 MHz)IRC (~32 kHz)LPO (~1 kHz)48 MHz64LQFPMemories and memory interfaces64 KB8 KB--Core modulesYES-System modulesYESYES-YESClock modulesFLLYESYESYESTable continues on the next page...FLLYESYESYESYESYES-YESYES-128 KB16 KB--48 MHz64LQFPProduct Brief, Rev 1.1, 02/2014

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FeaturesTable 4.KEA128 48 MHz performance table (continued)SKEAZ128AMLH(R)SKEAZ128AMLK(R)1YES12bit, 1x16ch221121x2ch132-21--71822.7-5.5 V2.7 V-40 to 125 °CSKEAZ64AMLH(R)SKEAZ64AMLK(R)1YES12bit, 1x16ch221121x2ch132-21--71822.7-5.5 V2.7 V-40 to 125 °CSC part number16-bit RTCCRCADC with 8 buffer entry6-bit DACACMPBandgap Vref (no pin-out)16-bit FTM (6-ch)16-bit FTM (2-ch)PIT (32-bit)PWTUART (LIN slave capable)SPI (8-bit)SPI (16-bit )I2C (400 kb/s)CANSegment LCDTSI (capacitive touch)Total GPIOs20 mA high-drive GPIOTrue open-drainVoltage rangeFlash write VTemperature range1Security and integrityYESAnalog12bit, 1x16ch221Timers121x2ch1Communication interfaces32-21Human-machine interface--5882Operating characteristics2.7-5.5 V2.7 V-40 to 125 °C1YES12bit, 1x16ch221121x2ch132-21--58822.7-5.5 V2.7 V-40 to 125 °C4.5Module-by-module feature list

The following sections describe the high-level module features for the family's superset device. See KEA128 family features(48 MHz performance) for differences among the subset devices.

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Core modules4.5.1Core modules

4.5.1.1

?Up to 48 MHz core frequency from 2.7 V to 5.5 V across temperature range of –40 °C to 125 °C?Supports up to 32 interrupt request sources

?2-stage pipeline microarchitecture for reduced power consumption and improved architectural performance (cycles perinstruction)

?Binary compatible instruction set architecture with the Cortex-M0 core?Thumb instruction set combines high code density with 32-bit performance?Serial wire debug (SWD) reduces the number of pins required for debugging?Single cycle 32 bits by 32 bits multiply

ARM Cortex-M0+ core

4.5.1.2Nested Vectored Interrupt Controller (NVIC)

Following are the features of the NVIC module.?Up to 32 interrupt sources

?Includes a single non-maskable interrupt

4.5.1.3Asynchronous Wake-up Interrupt Controller (AWIC)

The features of the AWIC module are given below.

?Supports interrupt handling when system clocking is disabled in low-power modes

?Takes over and emulates the NVIC behavior when correctly primed by the NVIC on entry to very deep sleep mode.?A rudimentary interrupt masking system with no prioritization logic signals for wake-up as soon as a non-maskedinterrupt is detected

?Contains no programmer’s model visible state and is therefore invisible to end users of the device other than throughthe benefits of reduced power consumption while sleeping

4.5.1.4

?2-pin serial wire debug (SWD) provides external debugger interface

Debug controller

4.5.2System modules

4.5.2.1

?????????

Power Management Control (PMC) unit

The features of the PMC module are listed below.

Separate digital (regulated) and analog (referenced to digital) supply outputsProgrammable power saving modes

No output supply decoupling capacitors required

Available wake-up from power saving modes via RTC and external inputsIntegrated power-on-reset (POR)

Integrated low voltage detect (LVD) with reset (brownout) capabilitySelectable LVD trip points

Programmable low-voltage warning (LVW) interrupt capabilityBuffered bandgap reference voltage output

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Memories and memory interfaces?Factory programmed trim for bandgap and LVD?1 kHz low-power oscillator (LPO)

4.5.2.2Watchdog (WDOG) module

The features of the Watchdog module are described as follows.?Independent clock source input (independent from CPU/bus clock)?Choice between clock sources

?1 kHz internal low-power oscillator (LPOCLK)?Internal 32 kHz reference clock (ICSIRCLK)?External clock (OSCERCLK)?Bus clock

4.5.2.3System clocks

The following clock sources can be used as system clocks.

?System oscillator (OSC)—Loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 to 39.0625 kHz(low-range mode) or 4-24 MHz (high-range mode)?Internal clock source (ICS)

?Frequency-locked loop (FLL) controlled by internal or external reference

?40 MHz~50 MHz FLL output

?Internal reference clocks—Can be used as a clock source for the other on-chip peripherals

?On-chip RC oscillator range of 31.25 to 39.0625 kHz oscillator as the reference of FLL input.

4.5.3Memories and memory interfaces

4.5.3.1

On-chip memory

?48 MHz performance devices

?Up to 128 KB flash memory?Up to 16 KB SRAM

?Security circuitry to prevent unauthorized access to RAM and flash contents

4.5.4Analog

4.5.4.1

Analog-to-Digital Converter (ADC)

The features of the ADC module are given below.

?Linear successive approximation algorithm with 8-, 10-, or 12-bit resolution

?Up to 16 external analog inputs, and 5 internal analog inputs including internal bandgap, temperature sensor, andreferences

?Output formatted in 8-, 10-, or 12-bit right-justified unsigned format

?Single or continuous conversion (automatic return to idle after single conversion)?Supports up to eight result FIFO with selectable FIFO depth?Configurable sample time and conversion speed/power?Conversion complete flag and interrupt

?Input clock selectable from up to four sources

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Timer????Operation in Wait or Stop modes for lower noise operationAsynchronous clock source for lower noise operationSelectable asynchronous hardware conversion trigger

Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value

4.5.4.2

??????

Analog Comparator (ACMP)

The ACMP module has the following features.

Operational over the whole supply range of 2.7–5.5 V

On-chip 6-bit resolution DAC with selectable reference voltage from VDD or internal bandgapConfigurable hysteresis

Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator outputSelectable inversion on comparator output

Up to four selectable comparator inputs; one of these is fixed and connected to built-in DAC output while the others areexternally mapped on pinouts.?Operational in Stop mode

4.5.5Timer

4.5.5.1

????????????

FlexTimers (FTM)

The FlexTimer module exhibits the following features.

Selectable FTM source clock, supporting separate timer clock from core and bus, up to 48 MHzProgrammable prescaler

16-bit counter supporting free-running or initial/final value, and counting is up or up-downInput capture, output compare, and edge-aligned and center-aligned PWM modesInput capture and output compare modes

Operation of FTM channels as pairs with equal outputs, pairs with complimentary outputs, or independent channelswith independent outputs

Deadtime insertion is available for each complementary pairGeneration of hardware triggersSoftware control of PWM outputs

Up to four fault inputs for global fault controlConfigurable channel polarity

Programmable interrupt on input capture, reference compare, overflowed counter, or detected fault condition

4.5.5.2

????

Periodic Interrupt Timer (PIT)

The features of the PIT module are given below.

Two general-purpose interrupt timers

One interrupt timer for triggering ADC conversions32-bit counter resolution

Clocked by bus clock frequency

4.5.5.3Real-Time Clock (RTC)

Following are the features of the real-time clock.?16-bit up-counter

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Communication interfaces?16-bit modulo match limit

?Software controllable periodic interrupt on match

?Software selectable clock sources for input to prescaler with programmable 16 bit prescaler

?OSC 32.768 kHz nominal?LPO (~1 kHz)?Bus clock

?Internal reference clock

4.5.5.4

The pulse width timer (PWT) includes the following features:

?Automatic measurement of pulse width with 16 bit resolution?Separate positive and negative pulse width measurements?Programmable triggering edge for starting measurement

?Programmable measuring time between successive alternating edges, rising edges or falling edges?Programmable prescaler from clock input as 16 bit counter time base

?Two selectable clock sources, supporting separate timer clock up to 48 MHz?Four selectable pulse inputs

?Programmable interrupt generation upon pulse width value updated and counter overflow

Pulse Width Timer (PWT)

4.5.6Communication interfaces

4.5.6.1

???????????

Inter-Integrated Circuit (I2C)

The features of the I2C module are as follows.

Compatible with I2C bus standard

Up to 100 kbit/s with maximum bus loadingMultimaster operation

Software programmable for one of 64 different serial clock frequenciesProgrammable slave address and glitch input filterInterrupt-driven byte-by-byte data transfer

Arbitration lost interrupt with automatic mode switching from master to slaveCalling address identification interrupt

Bus busy detection broadcast and 10-bit address extension

Address matching causes wake-up when processor is in low-power mode.I2C0 supports 4-wire interface

4.5.6.2

????

Universal Asynchronous Receiver/Transmitter (UART)

The UART module has the following features.

Full-duplex, standard non-return-to-zero (NRZ) format

Double-buffered transmitter and receiver with separate enablesProgrammable baud rates (13-bit modulo divider)Interrupt-driven or polled operation:

?Transmit data register empty and transmission complete?Receive data register full

?Receive overrun, parity error, framing error, and noise error?Idle receiver detect

?Active edge on receive pin?Break detect supporting LIN

?Hardware parity generation and checking

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Human machine interface?????Programmable 8-bit or 9-bit character lengthProgrammable 1-bit or 2-bit stop bits

Receiver wake-up by idle-line or address-mark

Optional 13-bit break character generation / 11-bit break character detectionSelectable transmitter output polarity

4.5.6.3

??????????

Serial Peripheral Interface (SPI)

The features of the SPI module are listed below.

Master and slave mode

Full-duplex, three-wire synchronous transfersProgrammable transmit bit rate

Double-buffered transmit and receive data registersSerial clock phase and polarity optionsSlave select output

Mode fault error flag with CPU interrupt capabilityControl of SPI operation during Wait modeSelectable MSB-first or LSB-first shiftingReceive data buffer hardware match feature

4.5.6.4Freescale's scalable controller area network (MSCAN)

The features of the MSCAN module are listed below.

?Implementation of the CAN protocol - Version 2.0A/B

?Standard and extended data frames

?Zero to eight bytes data length Introduction?Programmable bit rate up to 1 Mbps1?Support for remote frames

?Five receive buffers with FIFO storage scheme

?Three transmit buffers with internal prioritization using a \

?Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four 16-bit filters, oreight 8-bit filters

?Programmable wake-up functionality with integrated low-pass filter?Programmable loopback mode supports self-test operation?Programmable listen-only mode for monitoring of CAN bus?Programmable bus-off recovery functionality

?Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive,bus-off)

?Programmable MSCAN clock source either bus clock or oscillator clock?Internal timer for time-stamping of received and transmitted messages?Three low-power modes: sleep, power down, and MSCAN enable?Global initialization of configuration registers

4.5.7Human machine interface

4.5.7.1

General-Purpose Input/Output (GPIO)

The features of the GPIO module are listed below.

1.Depending on the actual bit timing and the clock jitter of the clock source.

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Human machine interface????Hysteresis and configurable pull up device on all input pinsConfigurable drive strength on some output pins

Independent pin value register to read logic level on digital pinFast IO access in single-cycle core clock

4.5.7.2Keyboard Interrupts (KBI)

The KBI features include:

?Up to eight keyboard interrupt pins with individual pin enable bits?Each keyboard interrupt pin is programmable as:

?falling-edge sensitivity only?rising-edge sensitivity only

?both falling-edge and low-level sensitivity?both rising-edge and high-level sensitivity?One software-enabled keyboard interrupt?Exit from low-power modes

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freescale.com/supportInformation in this document is provided solely to enable system andsoftware implementers to use Freescale products. There are no expressor implied copyright licenses granted hereunder to design or fabricateany integrated circuits based on the information in this document.

Freescale reserves the right to make changes without further notice toany products herein.

Freescale makes no warranty, representation, or guarantee regardingthe suitability of its products for any particular purpose, nor doesFreescale assume any liability arising out of the application or use ofany product or circuit, and specifically disclaims any and all liability,including without limitation consequential or incidental damages.“Typical” parameters that may be provided in Freescale data sheetsand/or specifications can and do vary in different applications, andactual performance may vary over time. All operating parameters,

including “typicals,” must be validated for each customer application bycustomer's technical experts. Freescale does not convey any licenseunder its patent rights nor the rights of others. Freescale sells productspursuant to standard terms and conditions of sale, which can be foundat the following address: freescale.com/SalesTermsandConditions.Freescale, the Freescale logo, and Kinetis are trademarks of FreescaleSemiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product orservice names are the property of their respective owners. ARM andCortex-M0+ are the registered trademarks of ARM Limited.?2013-2014 Freescale Semiconductor, Inc.

Document Number SKEA128PB

Revision 1.1, 02/2014

Preliminary

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