MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP0163.3V / 5V ECL 8-Bit

Synchronous Binary UpCounter

Description

The MC10/100EP016 is a high-speed synchronous, presettable,cascadeable 8-bit binary counter. Architecture and operation are thesame as the MC10E016 in the ECLinPS family.

(Terminal Count Load) pin. When TCLD is LOW (or left open, ingoing LOW to indicate an all-one state. When TCLD is HIGH, the TCfeedback causes the counter to automatically reload upon TC = LOW,thus functioning as a programmable counter. The Qn outputs do notneed to be terminated for the count function to operate properly. Tominimize noise and power, unused Q outputs should be leftunterminated.

non-cascadedfor a counter or divider cascade chain output.

A differential clock input has also been added to improveperformance.

The 100 Series contains temperature compensation.

Features

500 ps Typical Propagation Delay

PECL Mode Operating Range: VCC = 3.0 V to 5.5 V

with VEE = 0 V

NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State Safety Clamp on Inputs

8-Bit

Differential Clock Input VBB Output

Asynchronous Master Reset

Pb-Free Packages are Available*

ORDERING INFORMATION

See detailed ordering and shipping information in the packagedimensions section on page 13 of this data sheet.

*For additional information on our Pb-Free strategy and soldering details, pleasedownload the ON Semiconductor Soldering and Mounting TechniquesReference Manual, SOLDERRM/D.

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP016

VCC

Q2

Q1

Q0VEEMR

VCCQ3Q4Q5Q6Q7

P6

P5

VCCQ3Q4Q5Q6Q7VExposed Pad

(EP)VBBCLK

VEE

COUTVCCP7P6P5

Warning: All VCC and VEE pins must be externally connected toPower Supply to guarantee proper operation.

Figure 1. 32-Lead LQFP Pinout (Top View)

Table 1. PIN DESCRIPTION

PinP0-P7*Q0-Q7MR*TCLD*VCCVEEVBBEP

ECL Parallel Data (Preset) InputsECL Data Outputs

ECL Count Enable Control InputECL Parallel Load Enable Control InputECL Master ResetECL Differential ClockECL Terminal Count OutputECL TC-Load Control InputECL Differential OutputPositive SupplyNegative Supply

Reference Voltage Output

The exposed pad (EP) on the QFN-32 package bottom is thermally connected to the die for improved heat transfer outof the package. THe exposed pad must be attached to a heat-sinking conduit. The pad is electrically connected to VEE.

Function

*Pins will default LOW when left open.

P0P1P2P3P4

VCC

VEE

COUTVCCP7

Figure 2. 32-Lead QFN Pinout (Top View)

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP016

ZZ = Clock Pulse (High-to-Low)Z = Clock Pulse (Low-to-High)

Table 3. FUNCTION TABLE

FunctionLoad Count

LHHHHLHHHHHHHHX

XLLLLXHHLLLLLLX

MRLLLLLLLLLLLLLLH

TCLDXLLLLXXXHHHHHHX

CLKZZZZZZZZZZZZZZX

P7-P4HXXXXHXXHHHHHHX

P3HXXXXHXXLLLLLLX

P2HXXXXHXXHHHHHHX

P1LXXXXLXXHHHHHHX

P0LXXXXLXXLLLLLLX

Q7-Q4HHHHLHHHHHHHHHL

Q3HHHHLHHHHHHLLHL

Q2HHHHLHHHHHHHHLL

Q1LLHHLLLLLHHHHLL

Q0LHLHLLLLHLHLHLL

HHHLHHHHHHLHHHH

HHHLHHHHHHLHHHH

COUTLLLHLLLLLLHLLLL

Load Hold

Load on Terminal Count

Reset

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP016

Note that this diagram is provided for understanding of logic operation only.

It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.

Figure 3. 8-BIT Binary Counter Logic Diagram

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP016

Table 4. ATTRIBUTES

Characteristics

Internal Input Pulldown ResistorInternal Input Pullup ResistorESD Protection

Human Body Model

Machine Model

Charged Device Model

Pb PkgLevel 2N/A

Value75 kWN/A> 2 kV> 100 V> 2 kV

Pb-Free PkgLevel 2Level 1

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

LQFP-32QFN-32

Flammability RatingTransistor Count

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test1.For additional information, see Application Note AND8003/D.

Oxygen Index: 28 to 34

UL 94 V-0 @ 0.125 in

897 Devices

Table 5. MAXIMUM RATINGS)

SymbolVCCVEEVIIoutIBBTATstgqJAqJCqJAqJCTsol

Parameter

PECL Mode Power SupplyNECL Mode Power SupplyPECL Mode Input VoltageNECL Mode Input VoltageOutput CurrentVBB Sink/Source

Operating Temperature RangeStorage Temperature Range

Thermal Resistance (Junction-to-Ambient)Thermal Resistance (Junction-to-Case)Thermal Resistance (Junction-to-Ambient)Thermal Resistance (Junction-to-Case)Wave Solder

PbPb-Free

0 lfpm500 lfpmStandard Board0 lfpm500 lfpm(Note 2)

32 LQFP32 LQFP32 LQFPQFN-32QFN-32QFN-32

Condition 1VEE = 0 VVCC = 0 VVEE = 0 VVCC = 0 VContinuousSurge

VI VCCVI VEE

Condition 2

Rating6-66-650100± 0.5-40 to +85-65 to +150

805512 to 17312712265265

UnitVVVVmAmAmA°C°C°C/W°C/W°C/W°C/W°C/W°C/W°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.

2.JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with y8 filled thermal vias under exposed pad.

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP016

Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)

-40°C

SymbolIEEVOHVOLVIHVILVBBVIHCMR

Characteristic

Power Supply CurrentOutput HIGH Voltage (Note 4)Output LOW Voltage (Note 4)Input HIGH Voltage (Single-Ended)Input LOW Voltage (Single-Ended)Output Voltage Reference

Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 5)

Input HIGH CurrentInput LOW Current

0.5Min120216513652090136517902.0

1890Typ16022901490

Max200241516152415169019903.3

Min120223014302155146018552.0

195525°CTyp16023551555

Max200248016802480175520553.3

Min120229014902215149019152.0

201585°CTyp16024151615

Max200254017402540181521153.3

UnitmAmVmVmVmVmVV

IIHIIL

150

0.5

150

0.5

150mAmA

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

3.Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.4.All loading with 50 W to VCC - 2.0 V.

5.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 7. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)

-40°C

SymbolIEEVOHVOLVIHVILVBBVIHCMR

Characteristic

Power Supply Current (Note 7)Output HIGH Voltage (Note 8)Output LOW Voltage (Note 8)Input HIGH Voltage (Single-Ended)Input LOW Voltage (Single-Ended)Output Voltage Reference

Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 9)

Input HIGH CurrentInput LOW Current

0.5Min120386530653790306534902.0

3590Typ16039903190

Max200411533154115339036905.0

Min120393031303855313035552.0

365525°CTyp16040553255

Max200418033804180345537555.0

Min120399031903915319036152.0

371585°CTyp16041153315

Max200424034404240351538155.0

UnitmAmVmVmVmVmVV

IIHIIL

150

0.5

150

0.5

150mAmA

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

6.Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.

7.Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermalprotection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V.8.All loading with 50 W to VCC - 2.0 V.

9.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP016

Table 8. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 10)

-40°C

SymbolIEEVOHVOLVIHVILVBBVIHCMR

Characteristic

Power Supply Current (Note 11)Output HIGH Voltage (Note 12)Output LOW Voltage (Note 12)Input HIGH Voltage (Single-Ended)Input LOW Voltage (Single-Ended)Output Voltage Reference

Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 13)

Input HIGH CurrentInput LOW Current

0.5Min120-1135-1935-1210-1935-1510

-1410Typ160-1010-1810

Max200-885-1685-885-1610-13100.0

Min120-1070-1870-1145-1870-1445

-134525°CTyp160-945-1745

Max200-820-1620-820-1545-12450.0

Min120-1010-1810-1085-1810-1385

-128585°CTyp160-885-1685

Max200-760-1560-760-1485-11850.0

UnitmAmVmVmVmVmVV

VEE+2.0VEE+2.0VEE+2.0

IIHIIL

150

0.5

150

0.5

150mAmA

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

10.Input and output parameters vary 1:1 with VCC.

11.Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermalprotection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V.12.All loading with 50 W to VCC - 2.0 V.

13.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 14)

-40°C

SymbolIEEVOHVOLVIHVILVBBVIHCMR

Characteristic

Power Supply Current

Output HIGH Voltage (Note 15)Output LOW Voltage (Note 15)Input HIGH Voltage (Single-Ended)Input LOW Voltage (Single-Ended)Output Voltage Reference

Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 16)

Input HIGH CurrentInput LOW Current

0.5Min120215513552075135517752.0

1875Typ16022801480

Max200240516052420167519753.3

Min120215513552075135517752.0

187525°CTyp16022801480

Max200240516052420167519753.3

Min120215513552075135517752.0

187585°CTyp16022801480

Max200240516052420167519753.3

UnitmAmVmVmVmVmVV

IIHIIL

150

0.5

150

0.5

150mAmA

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

14.Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V.15.All loading with 50 W to VCC - 2.0 V.

16.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP016

Table 10. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 17)

-40°C

SymbolIEEVOHVOLVIHVILVBBVIHCMR

Characteristic

Power Supply Current (Note 18)Output HIGH Voltage (Note 19)Output LOW Voltage (Note 19)Input HIGH Voltage (Single-Ended)Input LOW Voltage (Single-Ended)Output Voltage Reference

Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 20)

Input HIGH CurrentInput LOW Current

0.5Min120385530553775305534752.0

3575Typ16039803180

Max200410533054120337536755.0

Min120385530553775305534752.0

357525°CTyp16039803180

Max200410533054120337536755.0

Min120385530553775305534752.0

357585°CTyp16039803180

Max200410533054120337536755.0

UnitmAmVmVmVmVmVV

IIHIIL

150

0.5

150

0.5

150mAmA

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

17.Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V.

18.Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermalprotection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V.19.All loading with 50 W to VCC - 2.0 V.

20.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 11. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5 V to -3.0 V (Note 21)

-40°C

SymbolIEEVOHVOLVIHVILVBBVIHCMR

Characteristic

Power Supply Current (Note 22)Output HIGH Voltage (Note 23)Output LOW Voltage (Note 23)Input HIGH Voltage (Single-Ended)Input LOW Voltage (Single-Ended)Output Voltage Reference

Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 24)

Input HIGH CurrentInput LOW Current

0.5Min120-1145-1945-1225-1945-1525

-1425Typ160-1020-1820

Max200-895-1695-880-1625-13250.0

Min120-1145-1945-1225-1945-1525

-142525°CTyp160-1020-1820

Max200-895-1695-880-1625-13250.0

Min120-1145-1945-1225-1945-1525

-142585°CTyp160-1020-1820

Max200-895-1695-880-1625-13250.0

UnitmAmVmVmVmVmVV

VEE+2.0VEE+2.0VEE+2.0

IIHIIL

150

0.5

150

0.5

150mAmA

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

21.Input and output parameters vary 1:1 with VCC.

22.Required 500 lfpm air flow when using -5 V power supply. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermalprotection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V.23.All loading with 50 W to VCC - 2.0 V.

24.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP016

Table 12. AC CHARACTERISTICS VEE = -3.0 V to -5.5 V; VCC = 0 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 25)

-40°C

SymbolfCOUNT

Characteristic

Maximum Frequency

Propagation Delay(10)

(10)(10)(10)(10)(10)(100)(100)(100)(100)(100)(100)Setup Time

CLK to QMR to QCLK to COUTMR to COUT

CLK to QMR to QCLK to COUTMR to COUT

PnTCLDPnTCLD

300300350250400300350400350400400450100500500500100500500500

> 1> 800460400420350470400500550500550550600-50300300300-503003003002.6

200550120

80300210

3208.5

200550120

600500550450650550650700650700750800

350400400350450400400450400450450500100500500500100500500500

> 1> 800500500500450550500550590550590600640-50300300300-503003003002.580300220

3208.0

200550150

650600600550700650700750700750800850

400450400400450450480520480520530570100500500500100500500500

> 1> 800560580550510600560630670630670680720-50300300300-503003003002.580300250

4508.0700700700600800700780820780820880920

GHzMHzps

Min

Typ

Max

Min

25°CTyp

Max

Min

85°CTyp

Max

Unit

tPLHtPHL

tS

ps

tH

Hold Timeps

tJITTERtRRtPWtrtf

Clock Random Jitter

(RMS >1000 Waveforms)Reset Recovery Time

Minimum Pulse Width CLK, MROutput Rise/Fall Times20% - 80%

pspspsps

NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

25.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V.

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP016

APPLICATIONS INFORMATION

Cascading Multiple EP016 Devices

For applications which call for larger than 8-bit countersmultiple EP016s can be tied together to achieve very widecascading of EP016 devices. Two EP016s can be cascadedwithout the need for external gating, however for counterswider than 16 bits external OR gates are necessary forcascade implementations.

Figure 4 below pictorially illustrates the cascading of 4EP016s to build a 32-bit high frequency counter. Note theEP01 gates used to OR the terminal count outputs of thelower order EP016s to control the counting operation of thehigher order bits. When the terminal count of the precedingdevice (or devices) goes low (the counter reaches an all 1sstate) the more significant EP016 is set in its count mode andwill count one binary digit upon the next positive clocktransition. In addition, the preceding devices will also count

one bit thus sending their terminal count outputs back to ahigh state disabling the count operation of the moresignificant counters and placing them back into hold modes.Therefore, for an EP016 in the chain to count, all of the lowerorder terminal count outputs must be in the low state. The bitwidth of the counter can be increased or decreased by simplyadding or subtracting EP016 devices from Figure 4 andmaintaining the logic pattern illustrated in the same figure.The maximum frequency of operation for a cascadeddelay through the OR gate controlling it (for 16-bit counterssetup time). Figure 4 shows EP01 gates used to control thecount enable inputs, however, if the frequency of operation isslow enough, a LVECL OR gate can be used. Using the worstcase guarantees for these parameters.

LOAD

CLK

Figure 4. 32-Bit Cascaded EP016 Counter

case estimates of these delays need to be added to thecalculations.

Programmable Divider

The EP016 has been designed with a control pin whichmakes it ideal for use as an 8-bit programmable divider. TheTCLD pin (load on terminal count) when asserted reloads thedata present at the parallel input pin (Pn's) upon reachingterminal count (an all 1s state on the outputs). Because thisfeedback is built internal to the chip, the programmabledivision operation will run at very nearly the same frequencyas the maximum counting frequency of the device. Figure 5below illustrates the input conditions necessary for utilizingthe EP016 as a programmable divider set up to divide by 113.

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP016

Applications Information (continued)

Table 13. PRESET VALUES FOR VARIOUS DIVIDERATIOS

DivideRatio

2345w

P7HHHHw HHH LLL

P6HHHH LLL LLL

Preset Data InputsP5HHHH LLL LLL

P4HHHH HLL LLL

P3HHHH LHH LLL

P2HHHL LHH LLL

P1H

LLH LHH HLL

P0LHLH LHL LHL

Figure 5. Mod 2 to 256 Programmable Divider

w112113114 254255256

To determine what value to load into the device toaccomplish the desired division, the designer simplysubtracts the binary equivalent of the desired divide ratiofrom the binary value for 256. As an example for a divideratio of 113:

Pn's = 256 - 113 = 8F16 = 1000 1111where:

P0 = LSB and P7 = MSB

Forcing this input condition as per the setup in Figure 5output is used as the divide output and the pulse duration isequal to a full clock period. For even divide ratios, twice theoutput can feed the clock input of a toggle flip flop to createa signal divided as desired with a 50% duty cycle.

A single EP016 can be used to divide by any ratio from 2to 256 inclusive. If divide ratios of greater than 256 areneeded multiple EP016s can be cascaded in a manner similarto that already discussed. When EP016s are cascaded tobuild larger dividers the TCLD pin will no longer provide ameans for loading on terminal count. Because one does notwant to reload the counters until all of the devices in thepins must be used for multiple EP016 divider chains.

CLK

Figure 6. Divide by 113 EP016 Programmable Divider Waveforms

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP016

Applications Information (continued)

Figure 7. 32-Bit Cascaded EP016 Programmable Divider

Figure 7 shows a typical block diagram of a 32-bit dividerchain. Once again to maximize the frequency of operationEP01 OR gates were used. For lower frequency applicationsa slower OR gate could replace the EP01. Note that for a16-bitenable) input CANNOT be replaced by a wire OR tie as theoutputs were OR tied the cascaded count operation would

feedback is external and requires external gating, themaximum frequency of operation will be significantly lessthan the same operation in a single device.

Maximizing EP016 Count Frequency

The EP016 device produces 9 fast transitioningsingle-ended outputs, thus VCC noise can becomesignificant in situations where all of the outputs switchsimultaneously in the same direction. This VCC noise cannegatively impact the maximum frequency of operation ofthe device. Since the device does not need to have the Qoutputs terminated to count properly, it is recommended thatif the outputs are not going to be used in the rest of the systemthey should be left unterminated. In addition, if only a subsetof the Q outputs are used in the system only those outputsshould be terminated. Not terminating the unused outputswill not only cut down the VCC noise generated but will alsosave in total system power dissipation. Following theseguidelines will allow designers to either be more aggressivein their designs or provide them with an extra margin to thepublished data book specifications.

VTT

VTT = VCC - 2.0 V

Figure 8. Typical Termination for Output Driver and Device Evaluation(See Application Note AND8020/D - Termination of ECL Logic Devices.)

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP016

ORDERING INFORMATION

Device

MC10EP016FAMC10EP016FAGMC10EP016FAR2MC10EP016MNGMC10EP016MNR4GMC10EP016FAR2GMC100EP016FAMC100EP016FAGMC100EP016FAR2MC100EP016MNGMC100EP016MNR4G

PackageLQFP-32LQFP-32(Pb-Free)LQFP-32QFN32(Pb-Free)QFN32(Pb-Free)LQFP-32(Pb-Free)LQFP-32LQFP-32(Pb-Free)LQFP-32QFN32(Pb-Free)QFN32(Pb-Free)

Shipping 250 Units / Tray250 Units / Tray2000 / Tape & Reel74 Units / Tray1000 / Tape & Reel2000 / Tape & Reel250 Units / Tray250 Units / Tray2000 / Tape & Reel74 Units / Tray1000 / Tape & Reel

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/DAN1406/DAN1503/DAN1504/DAN1568/DAN1672/DAND8001/DAND8002/DAND8020/DAND8066/DAND8090/D

-----------ECL Clock Distribution TechniquesDesigning with PECL (ECL at +5.0 V)ECLinPSt I/O SPiCE Modeling KitMetastability and the ECLinPS FamilyInterfacing Between LVDS and ECLThe ECL Translator GuideOdd Number Counters DesignMarking and Date CodesTermination of ECL Logic DevicesInterfacing with ECLinPS

AC Characteristics of ECL Devices

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP016

PACKAGE DIMENSIONS

0.20 (0.008)

ACT-UZ

32 LEAD LQFPCASE 873A-02

MC10EP016FAR2G,MC10EP016FAG,MC10EP016FAR2, 规格书,Datasheet 资料

MC10EP016, MC100EP016

PACKAGE DIMENSIONS

QFN32 5*5*1 0.5 PCASE 488AM-01

ISSUE O

2 X

*For additional information on our Pb-Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

本文来源：https://www.bwwdw.com/article/xby4.html