1.5寸彩色-UG-2828GDEDF11-topwin

Product Specification(Preliminary) Part Name: OEL Display Module Part ID: UG-2828GDEDF11 Doc No.: SAS1-D038-A
Customer:Approved by
From: Topwin Technology Inc.Approved by

R e v i s e d H i s t o r y

Part Number Revision Revision Content Revised on

2008 UG-2828GDEDF11 A New October

15,

C o n t e n t s

R e v i s i o n H i s t o r y (i)

N o t i c e (ii)

C o n t e n t s (iii)

1.B a s i c S p e c i f i c a t i o n s..................................................................................1~6

1.1 Display Specifications (1)

1.2 Mechanical Specifications (1)

1.3 Active Area & Pixel Construction (1)

1.4 Mechanical Drawing (2)

1.5 Pin Definition (3)

1.6 Block Diagram (6)

2.A b s o l u t e M a x i m u m R a t i n g s (7)

3.O p t i c s&E l e c t r i c a l C h a r a c t e r i s t i c s.........................................................8~12

3.1 Optics Characteristics (8)

3.2 DC Characteristics (8)

3.3 AC Characteristics (9)

3.3.1 68XX-Series MPU Parallel Interface Timing Characteristics (9)

3.3.2 80XX-Series MPU Parallel Interface Timing Characteristics (10)

3.3.3 Serial Interface Timing Characteristics (4-wire SPI) (11)

3.3.4 Serial Interface Timing Characteristics (3-wire SPI) (12)

4.F u n c t i o n a l S p e c i f i c a t i o n.......................................................................13~14

4.1 Commands (13)

4.2 Power down and Power up Sequence (13)

4.2.1 Power up Sequence (13)

4.2.2 Power down Sequence (13)

4.3 Reset Circuit (13)

4.4 Actual Application Example (14)

5.R e l i a b i l i t y (15)

5.1 Contents of Reliability Tests (15)

5.2 Lifetime (15)

5.3 Failure Check Standard (15)

6.O u t g o i n g Q u a l i t y C o n t r o l S p e c i f i c a t i o n s..............................................16~20

6.1 Environment Required (16)

6.2 Sampling Plan (16)

6.3 Criteria & Acceptable Quality Level (16)

6.3.1 Cosmetic Check (Display Off) in Non-Active Area (16)

6.3.2 Cosmetic Check (Display Off) in Active Area (19)

6.3.3 Pattern Check (Display On) in Active Area (20)

7.P a c k a g e S p e c i f i c a t i o n s (21)

8.P r e c a u t i o n s W h e n U s i n g T h e s e O E L D i s p l a y M o d u l e s.......................22~24

8.1 Handling Precautions (22)

8.2 Storage Precautions (23)

8.3 Designing Precautions (23)

8.4 Precautions when disposing of the OEL display modules (24)

8.5 Other Precautions (24)

1. B a s i c S p e c i f i c a t i o n s

1.1 Display Specifications

1) Display Mode:

Passive Matrix

2) Display Color: 262,144 Colors (Maximum) 3) Drive Duty:

1/128 Duty

1.2 Mechanical Specifications

1) Outline Drawing:

According to the annexed outline drawing 2) Number of Pixels: 128 (RGB) × 128 3) Panel Size: 33.80 × 34.00 × 1.60 (mm) 4) Active Area: 26.855 × 26.864 (mm) 5) Pixel Pitch: 0.07 × 0.21 (mm) 6) Pixel Size: 0.045 × 0.194 (mm) 7) Weight:

3.75 (g)

1.3 Active Area & Pixel Construction

P 0.21x 12

1.5 Pin Definition Pin Number

Symbol Type Function

P o w e r S u p p l y

27 VCI P P o w e r S u p p l y f o r O p e r a t i o n

This is a voltage supply pin. It must be connected to external source & always be equal to or higher than VDD & VDDIO. 26 VDD P

P o w e r S u p p l y f o r C o r e L o g i c C i r c u i t

This is a voltage supply pin which is regulated internally from VCI. A capacitor should be connected between this pin & VSS under all circumstances.

4 VDDIO P P o w e r S u p p l y f o r I /O P i n This pin is a power supply pin of I/O buffer. It should be connected to VCI or external source. All I/O signal should have VIH reference to VDDIO. When I/O signal pins (BS0~BS1, D0~D7, control signals…) pull high,they should be connected to VDDIO.

28 VSS P G r o u n d o f O E L S y s t e m

This is a ground pin. It also acts as a reference for the logic pins, the OEL driving voltages, and the analog circuits. It must be connected to external ground. 2 VCC P P o w e r S u p p l y f o r O E L P a n e l This is the most positive voltage supply pin of the chip.It must be connected to external source.

D r i v e r

22 IREF I C u r r e n t R e f e r e n c e f o r B r i g h t n e s s A d j u s t m e n t This pin is segment current reference pin. A resistor should be connected between this pin and VSS. Set the current lower than 12.5uA.

3 VCOMH P V o l t a g e O u t p u t H i g h L e v e l f o r C O M S i g n a l

This pin is the input pin for the voltage output high level for COM signals. A tantalum capacitor should be connected between this pin and VSS.

5 VSL P V o l t a g e O u t p u t L o w L e v e l f o r S E G S i g n a l This is segment voltage reference pin.

When external VSL is not used, this pin should be left open.

When external VSL is used, this pin should connect with resistor and diode to ground.

E x t e r n a l I C C o n t r o l

24

23

GPIO0 GPIO1 I/O G e n e r a l P u r p o s e I n p u t /O u t p u t

These pins could be left open individually or have signal inputted/outputted. They are able to use as the external DC/DC converter circuit enabled/disabled control or other applications.

41.5 Pin Definition (Continued) Pin Number

Symbol I/O Function

I n t e r f a c e

17

18 BS0 BS1 I C o m m u n i c a t i n g P r o t o c o l S e l e c t

These pins are MCU interface selection input. See the following table: BS0 BS1 3-wire SPI 1 0 4-wire SPI 0 0 68XX-parallel (8-bit) 1 1 80XX-parallel (8-bit)

0 1 21 RES# I P o w e r R e s e t f o r C o n t r o l l e r a n d D r i v e r This pin is reset signal input. When the pin is low,initialization of the chip is executed. 19 CS# I C h i p S e l e c t This pin is the chip select input. The chip is enabled for MCU communication only when CS# is pulled low. 20 D/C# I D a t a /C o m m a n d C o n t r o l

This pin is Data/Command control pin. When the pin is pulled high, the input at D7~D0is treated as display data.When the pin is pulled low, the input at D7~D0 will be transferred to the command register. For detail relationship to MCU interface signals, please refer to the Timing Characteristics Diagrams.

When 3-wire serial mode is selected, this pin must be connected to VSS.

15 E/RD# I R e a d /W r i t e E n a b l e o r R e a d

This pin is MCU interface input. When interfacing to a 68XX-series microprocessor, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled high and the CS# is pulled low. When connecting to an 80XX-microprocessor, this pin receives the Read (RD#) signal. Data read operation is initiated when this pin is pulled low and CS# is pulled low.

When serial mode is selected, this pin must be connected to VSS.

16 R/W# I R e a d /W r i t e S e l e c t o r W r i t e

This pin is MCU interface input. When interfacing to a 68XX-series microprocessor, this pin will be used as Read/Write (R/W#) selection input. Pull this pin to “High” for read mode and pull it to “Low” for write mode.

When 80XX interface mode is selected, this pin will be the Write (WR#) input. Data write operation is initiated when this pin is pulled low and the CS# is pulled low. When serial mode is selected, this pin must be connected to VSS.

7~14 D7~D0 I/O H o s t D a t a I n p u t /O u t p u t B u s

These pins are 8-bit bi-directional data bus to be connected to the microprocessor’s data bus. When serial

mode is selected, D1 will be the serial data input SDIN and D0 will be the serial clock input SCLK.

Unused pins must be connected to VSS except for D2.

1.5 Pin Definition (Continued)

Pin Number Symbol I/O Function R e s e r v e

6, 25, 29 N.C. - R e s e r v e d P i n

The N.C. pins between function pins are reserved for compatible and flexible design.

1, 30 N.C. (GND)- R e s e r v e d P i n(S u p p o r t i n g P i n)

The supporting pins can reduce the influences from stresses on the function pins. These pins must be connected to external ground.

1.6 Block Diagram

MCU Interface Selection: BS0 and BS1

Pins connected to MCU interface: D7~D0, E/RD#, R/W#, CS#, D/C#, and RES# C1, C5: 0.1μF

C2: 4.7μF

C6: 10μF

C3, C4: 1μF

C7: 4.7uF / 25V Tantalum Capacitor

R1: 560kΩ, R1 = (V oltage at IREF – VSS) / IREF

R2: 50Ω, 1/4W

D1: ≤1.4V, 0.5W

2.A b s o l u t e M a x i m u m R a t i n g s

Notes

Max

Unit

Min

Parameter Symbol

2 Supply V oltage for Operation V CI -0.

3

4 V 1,

2 Supply V oltage for Logic V DD -0.5 2.75 V 1,

2 Supply V oltage for I/O Pins V DDIO -0.5 V CI V 1,

2 Supply V oltage for Display V CC -0.5 16 V 1,

Operating Temperature T OP -30 70 °C -

Storage Temperature T STG -40 80 °C - Note 1: All the above voltages are on the basis of “VSS = 0V”.

Note 2: When this module is used beyond the above absolute maximum ratings, permanent breakage of the module may occur. Also, for normal operations, it

is desirable to use this module under the conditions according to Section 3.

“Optics & Electrical Characteristics”. If this module is used beyond these

conditions, malfunctioning of the module can occur and the reliability of the

module may deteriorate.

3.O p t i c s&E l e c t r i c a l C h a r a c t e r i s t i c s

3.1 Optics Characteristics

Characteristics Symbol Conditions Min Typ

Max

Unit

Brightness (White) L br With Polarizer

(Note 3)

70 90 - cd/m2

C.I.E. (White) (x)

(y)

With Polarizer

0.26

0.29

0.30

0.33

0.34

0.37

C.I.E. (Red) (x)

(y)

With Polarizer

0.60

0.30

0.64

0.34

0.68

0.38

C.I.E. (Green) (x)

(y)

With Polarizer

0.27

0.58

0.31

0.62

0.35

0.66

C.I.E. (Blue) (x)

(y)

With Polarizer

0.10

0.12

0.14

0.16

0.18

0.20

Dark Room Contrast CR - >2000:1 - View Angle >160- - degree * Optical measurement taken at V CI = 2.8V, V CC = 13V.

Software configuration follows Section 4.4 Initialization.

3.2 DC Characteristics

Characteristics Symbol Conditions Min Typ Max Unit Supply Voltage for Operation V CI 2.4 2.8 3.5 V

Supply Voltage for Logic V DD 2.4 2.5 2.6 V

Supply Voltage for I/O Pins V DDIO 1.65 1.8

V CI V Supply Voltage for Display V CC Note

3 12.513

13.5

V High Level Input V IH0.8×V DDIO- V DDIO V

Low Level Input V IL0 -

0.2×V DDIO V

High Level Output V OH I out = 100μA, 3.3MHz0.9×V DDIO- V DDIO V

Low Level Output V OL I out = 100μA, 3.3MHz0 -

0.1×V DDIO V

Operating Current for V CI I CI-

240

300

μA

Note 4 - 23.2 29.0 mA Operating Current for V CC I CC

Note 5 - 33.4 41.8 mA Sleep Mode Current for V CI I CI, SLEEP -

1

5

μA Sleep Mode Current for V CC I CC, SLEEP -

1

5

μA Note 3: Brightness (L br) and Supply Voltage for Display (V CC) are subject to the change of the panel characteristics and the customer’s request.

Note 4: V CI = 2.8V, V CC = 13V, 50% Display Area Turn on.

Note 5: V CI = 2.8V, V CC = 13V, 100% Display Area Turn on.

* Software configuration follows Section 4.4 Initialization.

3.3 AC Characteristics

3.3.1 68XX-Series MPU Parallel Interface Timing Characteristics:

Symbol Description Min Max Unit

t cycle Clock Cycle Time 300 - ns

t AS Address Setup Time 10 - ns

t AH Address Hold Time 0 - ns

t DSW Write Data Setup Time 40 - ns

t DHW Write Data Hold Time 7 - ns

t DHR Read Data Hold Time 20 - ns

t OH Output Disable Time - 70 ns

Time - 140 ns t ACC Access

Chip Select Low Pulse Width (Read) 120

- ns PW CSL

Chip Select Low Pulse Width (Write) 60

Chip Select High Pulse Width (Read) 60

- ns PW CSH

Chip Select High Pulse Width (Write) 60

Time - 15 ns t R Rise

Time - 15 ns t F Fall

* (V DD - V SS = 2.4V to 2.6V, V DDIO = 1.65V, V CI = 2.8V, T a = 25°C)

* (1) When 8-bit Used: D[7:0] Instead

3.3.2 80XX-Series MPU Parallel Interface Timing Characteristics:

Symbol Description Min Max Unit

t cycle Clock Cycle Time 300 - ns

t AS Address Setup Time 10 - ns

t AH Address Hold Time 0 - ns

t DSW Write Data Setup Time 40 - ns

t DHW Write Data Hold Time 7 - ns

t DHR Read Data Hold Time 20 - ns

t OH Output Disable Time - 70 ns

t ACC Access

Time - 140 ns t PWLR Read Low Time 150 - ns

t PWLW Write Low Time 60 - ns

t PWHR Read High Time 60 - ns

t PWHW Write High Time 60 - ns

t CS Chip Select Setup Time 0 - ns

t CSH Chip Select Hold Time to Read Signal0 - ns

t CSF Chip Select Hold Time 20 - ns

Time - 15 ns t R Rise

Time - 15 ns t F Fall

* (V DD - V SS = 2.4V to 2.6V, V DDIO = 1.65V, V CI = 2.8V, T a = 25°C)

* (1) When 8-bit Used: D[7:0] Instead

3.3.3 Serial Interface Timing Characteristics: (4-wire SPI)

Symbol Description Min Max Unit

t cycle Clock Cycle Time 50 - ns

t AS Address Setup Time 15 - ns

t AH Address Hold Time 15 - ns

t CSS Chip Select Setup Time 20 - ns

t CSH Chip Select Hold Time 10 - ns

t DSW Write Data Setup Time 15 - ns

t DHW Write Data Hold Time 15 - ns

t CLKL Clock Low Time 20 - ns

t CLKH Clock High Time 20 - ns

Time - 15 ns t R Rise

Time - 15 ns t F Fall

* (V DD - V SS = 2.4V to 2.6V, V DDIO = 1.65V, V CI = 2.8V, T a = 25°C)

3.3.4 Serial Interface Timing Characteristics: (3-wire SPI)

Symbol Description Min Max Unit

t cycle Clock Cycle Time 50 - ns

t CSS Chip Select Setup Time 20 - ns

t CSH Chip Select Hold Time 10 - ns

t DSW Write Data Setup Time 15 - ns

t DHW Write Data Hold Time 15 - ns

t CLKL Clock Low Time 20 - ns

t CLKH Clock High Time 20 - ns

Time - 15 ns t R Rise

Time - 15 ns t F Fall

* (V DD - V SS = 2.4V to 2.6V, V DDIO = 1.65V, V CI = 2.8V, T a = 25°C)

4. F u n c t i o n a l S p e c i f i c a t i o n

4.1. Commands

Refer to the Technical Manual for the SSD1351

4.2 Power down and Power up Sequence

To protect OEL panel and extend the panel life time, the driver IC power up/down routine should include a delay period between high voltage and low voltage power sources during turn on/off. It gives the OEL panel enough time to complete the action of charge and discharge before/after the operation.

4.2.1 Power up Sequence:

1. Power up V CI & V DDIO

2. Send Display off command

3. Initialization

4. Clear Screen

5. Power up V CC

6. Delay 100ms

(when V CC is stable)

7. Send Display on command

4.2.2 Power down Sequence:

1. Send Display off command

2. Power down V CC

3. Delay 100ms

(when V CC is reach 0 and panel is completely discharges) 4. Power down V CI & V DDIO

4.3 Reset Circuit

When RES# input is low, the chip is initialized with the following status:

1. Display is OFF

2. 128(RGB)×128 Display Mode

3. Normal segment and display data column and row address mapping (SEG0 mapped to column address 00h and COM0 mapped to row address 00h)

4. Display start line is set at display RAM address 0

5. Column address counter is set at 0

6. Normal scan direction of the COM outputs

7. Command A2h, B1h, B3h, BBh, BEh are locked by command FDh

D i s p l a y o n

V CI /V DDIO V C I ,V D D I O o n

V C C o n

V SS /Ground

V CC V C I ,V D D I O o f f

V CI /V DDIO D i s p l a y o f f

V C C o f f

V SS /Ground

V CC

4.4 Actual Application Example

Command usage and explanation of an actual example

If the noise is accidentally occurred at the displaying window during the operation, please reset the display in order to recover the display function.

5.R e l i a b i l i t y

5.1 Contents of Reliability Tests

Item Conditions

Criteria High Temperature Operation 70°C, 240 hrs

Low Temperature Operation -30°C, 240 hrs

High Temperature Storage 80°C, 240 hrs

Low Temperature Storage -40°C, 240 hrs

High Temperature/Humidity Operation60°C, 90% RH, 120 hrs Thermal Shock -40°C ? 85°C, 24 cycles

60 mins dwell The operational functions work.

* The samples used for the above tests do not include polarizer.

* No moisture condensation is observed during tests.

5.2 Lifetime

End of lifetime is specified as 50% of initial brightness.

Parameter Min Max Unit Condition Notes Operating Life Time 10,000- hr 90

cd/m2, 50% Checkerboard 6 Storage Life Time 20,000- hr T a = 25°C, 50% RH - Note 6: T he average operating lifetime at room temperature is estimated by the accelerated operation at high temperature conditions.

5.3 Failure Check Standard

After the completion of the described reliability test, the samples were left at room temperature for 2 hrs prior to conducting the failure test at 23±5°C; 55±15% RH.

6.O u t g o i n g Q u a l i t y C o n t r o l S p e c i f i c a t i o n s

6.1 Environment Required

Customer’s test & measurement are required to be conducted under the following

conditions:

± 5°C

Temperature: 23

Humidity: 55

± 15 %RH

Fluorescent Lamp: 30W

Distance between the Panel & Lamp: ≥ 50 cm

Distance between the Panel & Eyes of the Inspector: ≥ 30 cm

Finger glove (or finger cover) must be worn by the inspector.

Inspection table or jig must be anti-electrostatic.

6.2 Sampling Plan

Level II, Normal Inspection, Single Sampling, MIL-STD-105E

6.3 Criteria & Acceptable Quality Level

Partition AQL Definition

Major 0.65 Defects in Pattern Check (Display On)

Minor 1.0 Defects in Cosmetic Check (Display Off)

6.3.1 Cosmetic Check (Display Off) in Non-Active Area

6.3.1 Cosmetic Check (Display Off) in Non-Active Area (Continued)

Cupper Exposed (Even Pin or Film) Not Allowable by Naked Eye

Inspection

Not Allowable

Not Allowable

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