c单片机论文英文文献翻译

英文原文

Description

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atm-el’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51 instruction set and pin out. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atm-el AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.

Features:

Compatible with MCS-51 Products

4K Bytes of In-System Reprogrammable Flash Memory

Endurance: 1,000 Write/Erase Cycles

Fully Static Operation: 0 Hz to 24 MHz

Three-Level Program Memory Lock

128 x 8-Bit Internal RAM

32 Programmable I/O Lines

Two 16-Bit Timer/Counters

Six Interrupt Sources

Programmable Serial Channel

Low Power Idle and Power Down Modes

The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

Block Diagram

Pin Description:

VCC Supply voltage.

GND Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs.

Port 0 may also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming, and outputs

the code bytes during program verification. External pull-ups are required during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.

Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups.

Port 3 also serves the functions of various special features of the AT89C51 as listed below:

receives some control

signals for Flash

programming and

verification.

RST

Reset input. A high

on this pin for two

machine cycles while

the oscillator is

running resets the

device.

ALE/PROG

Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.

In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the micro-controller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external program memory.

When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program executions.

This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.

It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two

machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

mode Program memory ALE ^pens Port

0 Port

1

Port

2

Por

t3

idle internal 1

1 data data data Dat

a

Idle External 1

1 floa

t

Data data Dat

a

Power down Internal 0 0 Data Data Data Dat

a

Power down External 0 0 floa

t data Data dat

a

In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SF-Rs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

Program Memory Lock Bits

On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:

Program lock bits Protection type

Lb1 Lb2 Lb3

and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.

– Reserved bits.

. Reset value depends on reset source.

中文原文

描述

AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes 的快速可擦写的只读程序存储器（PEROM）和128 bytes 的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flesh存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。

主要性能参数：

与MCS-51产品指令系统完全兼容

4K字节可重复写flash闪速存储器

1000次擦写周期

全静态操作：0HZ－24MHZ

三级加密程序存储器

128*8字节内部RAM

32个可编程I/O口

2个16位定时／计数器

6个中断源

可编程串行UART通道

低功耗空闲和掉电模式

功能特性概述

AT89C51提供以下标准功能：4K 字节flesh闪速存储器，128字节内部RAM，32个I/O口线，两个16位定时／计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89C51可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时／计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。

方框图

引脚功能说明

Vcc：电源电压

GND：地

P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复位口。作为输出口用时，每位能吸收电流的方式驱动8个逻辑门电路，对端口写“1”可作为高阻抗输入端用。

在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间激活内部上拉电阻。

P1口：P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可做熟出口。做输出口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（Ail）.

Flash编程和程序校验期间，P1接受低8位地址。

P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部地山拉电阻把端口拉到高电平，此时可作为输出口，作输出口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（Ail）。

在访问外部程序存储器获16位地址的外部数据存储器（例如执行 MOVX @DPTR 指令）时，P2口送出高8位地址数据。在访问8位地址的外部数据存储器（如执行 MOVX @RI指令）时，P2口线上的内容（也即特殊功能寄存器（SFR）区中R2寄存器的内容），在整个访问期间不改变。

Flash编程或校验时，P2亦接受高地址和其它控制信号。

P3口：P3口是一组带有内部上拉电阻的8位双向I/O口。P3口输出缓冲级可驱

动（吸收或输出电流）4个TTL逻辑门电路。对P3口写入“1”时，他们被内部上拉

电阻拉高并可作为输出口。做输出端时，被外部拉低的P3口将用上拉电阻输出电流

（Ail）。P3口除了作为一般的I/O口线外，更重要的用途是它的第二功能，如下表所

示：

flash闪速存储器编程和

程序校验的控制信号。

RST：复位输入。当振

荡器工作时，RST引脚出现

两个机器周期以上高电平

将使单片机复位。

ALE/PROG：当访问外

部程序存储器或数据存储

器时，ALE（地址所存允许）

输出脉冲用于所存地址的

低8位字节。即使不访问外部存储器，ALE仍以时钟振荡频率的1/6输出固定的正脉

冲信号，因此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存

储器时将跳过一个ALE脉冲。

对flash存储器编程期间，该引脚还用于输入编程脉冲（^PROG）。

如有不要，可通过对特殊功能寄存器（SFR）区中的8EH单元的D0位置位，可禁

止ALE操作。该外置位后，只要一条MOVX和MOVC指令ALE才会被激活。此外，该引

脚会被微弱拉高，单片机执行外部程序时，应设置ALE无效。

^PSEN：程序存储允许（^PSEN）输出是外部程序存储器的读选通信号，当AT89C51

由外部程序存储器取指令（或数据）时，每个机器周期两个^PSEN有效，即输出两个

脉冲。在此期间，当访问外部数据存储器，这两次有效的^PSEN信号不出现。

EA/VPP:外部访问允许。欲使CPU仅访问外部程序存储器（地址为0000H---FFFFH），

EA端必须保持低电平（接地）。需注意的是; 如果加密位LB1被编程，复位时内部会

锁存EA端状态。

如 EA端为高电平（接VCC端），CPU则执行内部程序存储器中的指令。

Flash存储器编程时，该引脚加上+12V的编程允许电源VPP，当然这必须是该器

件是使用12V编程电压VPP.

XTAL1:振荡器反相放大器的及内部时钟发生器的输出端。

XTAL2:振荡器反相放大器的输出端。

时钟振荡器：

AT89C51中有一个用于构成内部振荡器的高增益反相放大器，引脚XTAL1和XTAL2分别是该放大器的输入端和输出端。这个放大器与作为反馈的片外石英晶体或陶瓷谐振器一起构成自激振荡器，振荡电路参见图5。

外接石英晶体（或陶瓷谐振器）及电容C1、C2接在放大器的反馈回路中构成并联振荡电路。对外接电容C1、C2虽然没有十分严格的要求，但电容容量的大小会轻微影响振荡频率的高低、振荡器的稳定性、起振的难易程度及温度稳定性，如果使用石英晶体，我们推荐电容使用30PF+10PF，而如使用陶瓷谐振器建议选择40PF+10PF。

用户也可以采用外部时钟。采用外部时钟的电路如图5右所示。这种情况下，外部时钟脉冲接到XTAL1端，即内部时钟发生器的输入端，XTAL2则悬空由于外部时钟信号是通过一个2分频触发器后作为内部时钟信号的，所以对外部时钟信号的占空比没有特殊要求，但最小高电平持续时间和最大的低电平持续时间应符合产品技术要求。

空闲模式

在空闲工作模式状态，CPU保持睡眠状态而所有片内的外设仍保持激活状态，这种方式由软件产生。此时，片内RAM和所有特殊功能寄存器的内容保持不变。空闲模式可由任何允许的中断请求或硬件复位终止。

终止空闲工作模式的方法有两种，其一是任何一条被允许中断的事件被激活，即可终止空闲工作模式。程序会首先响应中断，进入中断服务程序，执行完中断服务程序并仅随终端返回指令，下一条要执行的指令就是使单片机进入空闲模式那条指令后面的一条指令。其二是通过硬件复位也可将空闲工作模式终止，需要注意的是，当由硬件复位来终止空闲模式时，CPU通常是从激活空闲模式那条指令的下一条指令开始继续执行程序的，要完成内部复位操作，硬件复位脉冲要保持两个机器周期（24个时钟周期）有效，在这种情况下，内部禁止CPU访问片内RAM，而允许访问其它端口。为了避免可能对端口产生以外写入，激活空闲模式的那条指令后一条指令不应该是一条对端口或外部存储器的写入指令。

掉电模式

在掉电模式下，震荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内RAM和特殊功能寄存器的内容在终止掉电模式前被冻结。退出掉电模式的唯一方

法是硬件复位，复位后将重新定义全部特殊功能寄存器但不改变RAM中的内容，在VCC 恢复到正常工作电平前，复位应无效，且必须保持一定时间以使振荡器重启动并稳定工作。

程序存储器的加密：AT89C51可使用对芯片上的3个加密位进行编程（P）或不编程（U）来得到如下表所示的功能：

当加密位LB1被编程时，在复位期间，EA端的逻辑电平被采样并锁存，如果单片机上电后一直没有复位，则锁存起的初始值是一个随机数，且这个随机数会一直保持到真正复位为止。为使单片机能正常工作，被锁存的EA电平值必须与该引脚当前的逻辑电平一致。此外，加密位只能通过整片擦除的方法清除。

注：带“*”号的SFR 可位寻址。“－”表示保留位

复位值由复位源确定。

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