ACT-SF41632N-39P5C中文资料

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ACT-SF41632 High Speed128Kx32 SRAM / 512Kx32 Flash

Multichip Module

FEATURES

4 – 128K x 8 SRAMs & 4 – 512K x 8 Flash Die in One MCM

sAccess Times of 25ns, 35ns (SRAM) and 60ns, 70ns, 90ns (Flash)

sOrganized as 128K x 32 of SRAM and 512K x 32 of Flash Memory with Common Data BussLow Power CMOS

sInput and Output TTL Compatible DesignsMIL-PRF-38534 Compliant MCMs Available

sDecoupling Capacitors and Multiple Grounds for Low Noise

sCommercial, Industrial and Military Temperature Ranges

sIndustry Standard Pinouts

sTTL Compatible Inputs and Outputs sPackaging – Hermetic Ceramic

q 66–Lead, PGA-Type, 1.385"SQ x 0.245"max, Aeroflex code# "P1,P5 with/without shoulders)"q 68–Lead, Dual-Cavity CQFP(F2), 0.88"SQ x .20"max (.18 max thickness available, contact factory for details) (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint)

s

s

FLASH MEMORY FEATURES

Sector Architecture (Each Die)

q 8 Equal Sectors of 64K bytes each

q Any combination of sectors can be erased with one command sequence. s+5V Programing, +5V Supply

sEmbedded Erase and Program AlgorithmssHardware and Software Write Protection

sPage Program Operation and Internal Program Control Time.

s10,000 Erase/Program Cycles

AERO

F

LE

XLA

B

SINC.

C

9001

E

RTIFIED

Absolute Maximum Ratings

SymbolTCTSTGVGTLParameter

Flash Data Retention

Flash Endurance (Write/Erase Cycles)

10 Years10,000

Case Operating TemperatureStorage Temperature

Maximum Signal Voltage to GroundMaximum Lead Temperature (10 seconds)

Rating

Range-55 to +125-65 to +150-0.5 to +7300

Units°C°CV°C

Normal Operating Conditions

SymbolVCCVIHVIL

Parameter

Power Supply VoltageInput High VoltageInput Low Voltage

Minimum+4.5+2.2-0.5

Maximum+5.5VCC + 0.3+0.8

UnitsVVV

Capacitance

(VIN = 0V, f = 1MHz, TA = 25°C)

SymbolParameterCADCOECWE1-4CCECI/O

A0 – A18 Capacitance F/S Write Enable CapacitanceF/S Chip Enable CapacitanceI/O0 – I/O31 Capacitance

Maximum

8080305030

UnitspFpFpFpFpF

This parameter is guaranteed by design but not tested

DC Characteristics

(VCC = 5.0V, VSS = 0V, Tc = -55°C to +125°C)

Parameter

Input Leakage CurrentOutput Leakage Current

SymILIILO

Conditions

VCC = Max, VIN=0toVCCIHIH, VOUT=0toVCC

Min

MaxUnits1010500800.4

2.4

2603000.45

0.85 x VCC3.2

4.2

µAµAmAmAVVmAmAVVV

SRAM Operating Supply Current x 32 Ix32ILIH, f = 5MHz, VCC =

CC

IH Mode

Standby Current

SRAM Output Low VoltageSRAM Output High Voltage

Flash Vcc Active Current for Read (1)Flash Vcc Active Current for Program

or Erase (2)

Flash Output Low VoltageFlash Output High VoltageFlash Low Vcc Lock Out Voltage

ISBVOLVOHICC1ICC2VOLVOH1VLKO

IH, IH, f = 5MHz, VCC = Max

IOL = 8 mA, VCCIHIOH = -4.0 mA, , VCCIHILIHIHILIHIHIOL = 12 mA, VCCIHIOH = -2.5 mA, , VCCIH

Notes: 1) The ICC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The IH 2) ICC active while Embedded Algorithim (program or erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V

SRAM AC Characteristics

(VCC = 5.0V, VSS= 0V, TC = -55°C to +125°C)

Read Cycle

ParameterRead Cycle TimeAddress Access Time Chip Select Access Time

Output Hold from Address ChangeOutput Enable to Output ValidChip Select to Output in Low Z * Output Enable to Output in Low Z * Chip Deselect to Output in High Z * Output Disable to Output in High Z *

* Parameters guaranteed by design but not tested

SymboltRCtAAtACEtOHtOEtCLZtOLZtCHZtOHZ

30

1212

15

30

2020

Min Max25

2525

20

Min Max35

3535

Unitsnsnsnsnsnsnsnsnsns

Write Cycle

Parameter Write Cycle Time

Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse WidthAddress Setup Time

Output Active from End of Write * Write to Output in High Z * Data Hold from Write TimeAddress Hold Time

* Parameters guaranteed by design but not tested

SymboltWCtCWtAWtDWtWPtAStOWtWHZtDHtAH

00Min Max252020152000

10

00Min Max352525202500

20

Unitsnsnsnsnsnsnsnsnsnsns

SRAM Truth Table

ModeStandbyReadOutput Disable

Write

HLLL

XLHX

XHHL

Data I/OHigh ZData OutHigh ZData In

PowerStandbyActiveActiveActive

元器件交易网

Timing Diagrams— SRAMRead Cycle Timing Diagrams Read Cycle 1 (SCE= OE= VIL, SWE= VIH)tRC A0-18 tAA tOH DI/O Previous Data Valid Data Valid SCE tAS SWESEE NOTE

Write Cycle Timing Diagrams Write Cycle (SWE Controlled, OE= VIH)tWC A0-18 tAW tCW tAH

tWP

tWHZ

tDW Data Valid

tOW tDH

DI/O

Read Cycle 2 (SWE= VIH)tRC A0-18 tAA SCE tACE tCLZSEE NOTE

Write Cycle (SCE Controlled, OE= VIH )tWC A0-18 tAW tCHZSEE NOTE

tAH tCW

tAS SCE

OE tWP tOE tOLZSEE NOTE

tOHZSEE NOTE

SWE tDW DI/O Data Valid tDH

DI/O

High

Z

Data Valid

UNDEFINED

DON’T CARE

Note: Guaranteed by design, but not tested.

AC Test CircuitCurrent Source IOL

AC Test ConditionsParameter Typical 0– 3.0 5 1.5 Units V ns V

To Device Under Test CL= 50 pF

VZ~ 1.5 V (Bipolar Supply)

Input Pulse Level Input Rise and Fall Input and Output Timing Reference Level

IOH Current Source

Notes: 1) VZ is programmable from -2V to+7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance ZO= 75 . 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance.4

Aeroflex Circuit Technology

SCD3851 REV A 5/21/98

Plainview NY (516) 694-6700

Flash AC Characteristics – Read Only Operations

(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)

Parameter

Read Cycle TimeAddress Access Time Chip Enable Access TimeOutput Enable to Output ValidChip Enable to Output High Z (1)Output Enable High to Output High Z(1)

Note 1. Guaranteed by design, but not tested

Symbol–60–70–90

Units

JEDEC Stand’dMin MaxMin MaxMin Max

tAVAVtAVQVtELQVtGLQVtEHQZtGHQZtAXQX

tRCtACCtCEtOEtDFtDFtOH

060

6060302020

070

7070352020

090

9090352020

nsnsnsnsnsnsns

(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)

Parameter

Write Cycle TimeChip Enable Setup Time Write Enable Pulse Width Address Setup TimeData Setup TimeData Hold TimeAddress Hold Time

Write Enable Pulse Width High

Duration of Byte Programming OperationSector Erase Time

Read Recovery Time before WriteVcc Setup TimeChip Programming TimeChip Enable Hold Time Chip Erase Time

1. Toggle and Data Polling only.

Symbol

JEDEC Stand’d

tAVACtELWLtWLWHtAVWLtDVWHtWHDXtWLAXtWHWLtWHWH1tWHWH2

tWCtCEtWPtAStDStDHtAHtWPH

–60–70–90Min MaxMin MaxMin Max

6004004004520140

TYP30

50

50

5010

120

120

10

50

5010

120

700450450452014

TYP30

50

900450450452014

TYP30

Units

nsnsnsnsnsnsnsnsµsSecµsµsSecnsSec

tGHWL

tVCEtOEH 1

tWHWH3

(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)

Parameter

Write Cycle TimeWrite Enable Setup Time Chip Enable Pulse Width Address Setup TimeData Setup TimeData Hold TimeAddress Hold Time

Chip Enable Pulse Width HighDuration of Byte ProgrammingSector Erase TimeRead Recovery Time Chip Programming TimeChip Erase Time

Symbol

JEDEC Stand’d

tAVACtWLELtELEHtAVELtDVEHtEHDXtELAXtEHELtWHWH1tWHWH2

tWCtWStCPtAStDStDHtAHtCPH

–60–70–90Min MaxMin MaxMin Max

6004004004520140

50120TYP30

50120700450450452014

TYP30

50120900450450452014

TYP30

Units

nsnsnsnsnsnsnsnsµsSecnsSecSec

tGHEL

tWHWH3

元器件交易网

AC Waveforms for Flash Memory Read Operations

tRCAddresses Addresses Stable

tACCFCE

tDFOE

tOE

FWE

tCEOutputs High Z

tOHOutput Valid High Z

Write/Erase/Program Operation for Flash Memory, FWE ControlledData Polling Addresses 5555H tWC FCE tGHWL OE tWP FWE tCE tDH AOH Data tDS PD D7 DOUT tOH tOE tWPH tDF tWHWH1 tAS PA tAH PA tRC

5.0V tCENotes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the 0utput of the complement of the data written to the deviced. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.

Aeroflex Circuit Technology

6

SCD3851 REV A 5/21/98

Plainview NY (516) 694-6700

元器件交易网

AC Waveforms Chip/Sector Erase Operations for Flash MemorytAH Addresses 5555H tAS 2AAAH Data Polling 5555H 5555H 2AAAH SA

FCE tGHWL OE tWP FWE tCE Data tWPH tDH AAH tDS VCC 55H 80H AAH 55H 10H/30H

tVCENotes: 1. SA is the sector address for sector erase.

AC Waveforms for Data Polling During Embedded Algorithm Operations for Flash Memory

tCHFCE

tDF tOEOE

tOEHFWE

tCE tOH *DQ7 DQ7 DQ7= Valid Data High Z

tWHWH1 or 2DQ0-DQ6 DQ0–DQ6=InvalidDQ0–DQ6 Valid Data

tOE* DQ7=Valid Data (The device has completed the Embedded operation).

Aeroflex Circuit Technology

7

SCD3851 REV A 5/21/98

Plainview NY (516) 694-6700

Addresses

5555HtWC

tGHWL

tCP

tWS

CPH

tDH

AOH

Data

tDS

PD

DOUT

tWHWH1

AS

PA

tAH

PA

5.0V

Notes:

1. PA is the address of the memory location to be programmed.2. PD is the data to be programmed at byte address.

4. DOUT is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

66 Pins — PGA-Type

Pin #1234567891011121314151617

FunctionI/O8I/O9I/O10A14A16A11A0A18I/O0I/O1I/O222GNDI/O11A10A9

Pin #1819202122232425262728293031323334

FunctionA15VccI/O3I/O15I/O14I/O13I/O12A171I/O7I/O6I/O5I/O4I/O24

Pin #3536373839404142434445464748495051

FunctionI/O25I/O26A7A121A13A8I/O16I/O17I/O18VCC44I/O27A4A5A6

Pin #525354555657585960616263646566

Function33GNDI/O19I/O31I/O30I/O29I/O28A1A2A3I/O23I/O22I/O21I/O20

"P1" — 1.385" SQ PGA Type Package Standard (with shoulders on Pins 1, 11, 56 & 66) "P5" — 1.385" SQ PGA Type Special Order Package (without shoulders)

Bottom View (P1 & P5)

Side View (P1)

.245MAX.025.035

Side View (P5)

.220MAX

Pin 56

1.400 SQMAX1.000TYP.600TYP

Pin 1

.100TYP.020.016.145MIN

.100 TYP

1.000TYP

.020.016Pin 66

.165MIN

Pin 11

.100 TYP

All dimensions in inches

元器件交易网

Pin Numbers& Functions68 Pins— Dual-Cavity CQFPPin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Function GND SWE3 A5 A4 A3 A2 A1 A0 NC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Pin# 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Function GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 Vcc A11 A12 A13 A14 A15 A16 FCE Pin# 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Function OE SWE2 A17 FWE2 FWE3 FWE4 A18 SCE SWE1 FI/O31 FI/O30 FI/O29 FI/O28 FI/O27 FI/O26 FI/O25 FI/O24 Pin# 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Function GND FI/O23 FI/O22 FI/O21 FI/O20 FI/O19 FI/O18 FI/O17 FI/O16 VCC A10 A9 A8 A7 A6 FWE1 SWE4

Package Outline— Dual-Cavity CQFP"F2" Top View.990 SQ±.010 .890 SQ MAX

Pin 9 Pin 10

Pin 61 Pin 60 .015±.002

*.200 MAX

.010 REF

.010±.002 .010 R REF+3°/-3° .050 TYP Pin 26 Pin 27 .800 REF Pin 44 Pin 43 See Detail“A” *.180 MAX available, call factory for details .040±.005 Detail“A” .010±.005

All dimensions in inches

Aeroflex Circuit Technology

10

SCD3851 REV A 5/21/98

Plainview NY (516) 694-6700

CRCUT EGY

Ordering Information

Model Number

ACT-SF41632N–26P1XACT-SF41632N–37P1XACT-SF41632N–39P1XACT-SF41632N–26F2XACT-SF41632N–37F2XACT-SF41632N–39F2X

Note: (S) = Speed for SRAM, (F) = Speed for FLASH

DESC Part Number

TBDTBDTBDTBDTBDTBD

Speed

25(S) / 60(F) ns35(S) / 70(F) ns35(S) / 90(F) ns25(S) / 60(F) ns35(S) / 70(F) ns35(S) / 90(F) ns

Package

1.385"sq PGA-Type1.385"sq PGA-Type1.385"sq PGA-Type.88"sq CQFP.88"sq CQFP.88"sq CQFP

Part Number Breakdown

ACT–SF41632N–26P1M

Aeroflex CircuitTechnology

Memory Type

SF = SRAM Flash Combo Module Memory Depth, Locations

4 = 4M SRAM, 16 = 16M FlashMemory Width, BitsPinout Options N = None

Screening

C = Commercial Temp, 0°C to +70°C I = Industrial Temp, -40°C to +85°CT = Military Temp, -55°C to +125°C

M = Military Temp, -55°C to +125°C Screened *Q = MIL-PRF-38534 Compliant/SMD

Package Types & SizesSurface Mount Packages

F2 = 0.88"SQ 68 Leads Dual-Cavity CQFPThru-Hole Packages

P1 = 1.385"SQ PGA 66 Pins W/ShoulderP5 = 1.385"SQ PGA 66 Pins WO/Shoulder

Memory Speed (Code)

26 = 25ns SRAM & 60ns FLASH37 = 35ns SRAM & 70ns FLASH39 = 35ns SRAM & 90ns FLASH

* Screened to the individual test methods of MIL-STD-883

Specifications subject to change without notice.

Aeroflex Circuit Technology 35 South Service Road

Plainview New York 11830

FAX: (516) 694-6715

Toll Free Inquiries: 1-(800) 843-1553

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