交通灯信号控制器VHDL文本输入设计

交通灯信号控制器VHDL文本输入设计

--Cnt05s.vhd LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT05S IS PORT(CLK,EN05M,EN05B:IN STD_LOGIC; DOUT5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY CNT05S;

ARCHITECTURE ART OF CNT05S IS SIGNAL CNT3B:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN PROCESS(CLK,EN05M,EN05B) IS BEGIN IF(CLK'EVENT AND CLK='1') THEN IF EN05M='1' THEN CNT3B<=CNT3B+1; ELSIF EN05B='1' THEN CNT3B<=CNT3B+1; ELSIF EN05B='0' THEN CNT3B<=CNT3B-CNT3B-1; END IF; END IF; END PROCESS; PROCESS(CNT3B) IS BEGIN CASE CNT3B IS WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN OTHERS=>DOUT5<=\ END CASE; END PROCESS;

END ARCHITECTURE ART;

--Cnt25s.vhd LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT25S IS PORT(SB,SM,CLK,EN25:IN STD_LOGIC; DOUT25M,DOUT25B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY CNT25S;

ARCHITECTURE ART OF CNT25S IS SIGNAL CNT5B:STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN PROCESS(SB,SM,CLK,EN25) IS BEGIN IF (SB='0'OR SM='0')THEN CNT5B<=CNT5B-CNT5B-1; ELSIF(CLK'EVENT AND CLK='1') THEN IF EN25='1' THEN CNT5B<=CNT5B+1; ELSIF EN25='0' THEN CNT5B<=CNT5B-CNT5B-1; END IF; END IF; END PROCESS; PROCESS(CNT5B) IS BEGIN

CASE CNT5B IS WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN OTHERS=>DOUT25M<=\ END CASE; END PROCESS;

END ARCHITECTURE ART;

--Cnt45s.vhd LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT45S IS PORT(SB,CLK,EN45:IN STD_LOGIC; DOUT45M,DOUT45B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY CNT45S;

ARCHITECTURE ART OF CNT45S IS SIGNAL CNT6B:STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN PROCESS(SB,CLK,EN45) IS BEGIN IF SB='0' THEN CNT6B<=CNT6B-CNT6B-1; ELSIF(CLK'EVENT AND CLK='1') THEN IF EN45='1' THEN CNT6B<=CNT6B+1; ELSIF EN45='0' THEN CNT6B<=CNT6B-CNT6B-1; END IF; END IF; END PROCESS; PROCESS(CNT6B) IS BEGIN CASE CNT6B IS WHEN\ WHEN\ WHEN\ WHEN\

WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN OTHERS=>DOUT45M<=\ END CASE; END PROCESS;

END ARCHITECTURE ART;

--Cskz.vhd

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CSKZ IS PORT(INA:IN STD_LOGIC; OUTA:OUT STD_LOGIC); END ENTITY CSKZ;

ARCHITECTURE ART OF CSKZ IS BEGIN PROCESS(INA) IS BEGIN

IF INA='1'THEN OUTA<='1'; ELSE OUTA<='0'; END IF; END PROCESS;

END ARCHITECTURE ART;

--Jtdkz.vhd

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY JTDKZ IS PORT(CLK,SM,SB:IN STD_LOGIC; MR,MY0,MG0,BR,BY0,BG0:OUT STD_LOGIC); END ENTITY JTDKZ;

ARCHITECTURE ART OF JTDKZ IS TYPE STATE_TYPE IS(A,B,C,D); SIGNAL STATE:STATE_TYPE; BEGIN CNT:PROCESS(CLK) IS VARIABLE S:INTEGER RANGE 0 TO 45; VARIABLE CLR,EN:BIT; BEGIN IF(CLK'EVENT AND CLK='1') THEN IF CLR='0' THEN S:=0; ELSIF EN='0' THEN S:=S; ELSE S:=S+1; END IF; CASE STATE IS WHEN A=>MR<='0';MY0<='0';MG0<='1';BR<='1';BY0<='0';BG0<='0'; IF(SB AND SM)='1' THEN IF S=45 THEN STATE<=B;CLR:='0';EN:='0'; ELSE STATE<=A;CLR:='1';EN:='1'; END IF; ELSIF(SB AND (NOT SM))='1' THEN STATE<=B;CLR:='0';EN:='0'; ELSE STATE<=A;CLR:='1';EN:='1'; END IF; WHEN B=>MR<='0';MY0<='1';MG0<='0';BR<='1';BY0<='0';BG0<='0'; IF S=5 THEN STATE<=C;CLR:='0';EN:='0'; ELSE STATE<=B;CLR:='1';EN:='1'; END IF; WHEN C=>MR<='1';MY0<='0';MG0<='0';BR<='0';BY0<='0';BG0<='1'; IF(SB AND SM)='1' THEN IF S=25 THEN STATE<=D;CLR:='0';EN:='0'; ELSE STATE<=C;CLR:='1';EN:='1'; END IF; ELSIF SB='0' THEN STATE<=A;CLR:='0';EN:='0'; ELSE STATE<=C;CLR:='1';EN:='1'; END IF; WHEN D=>MR<='1';MY0<='0';MG0<='0';BR<='0';BY0<='1';BG0<='0'; IF S=5 THEN STATE<=A;CLR:='0';EN:='0'; ELSE STATE<=D;CLR:='1';EN:='1'; END IF; END CASE; END IF; END PROCESS CNT; END ARCHITECTURE ART;

--Xskz.vhd

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY XSKZ IS PORT(EN45,EN25,EN05M,EN05B:IN STD_LOGIC; AIN45M,AIN45B,AIN25M,AIN25B,AIN05:IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUTM,DOUTB:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY XSKZ;

ARCHITECTURE ART OF XSKZ IS BEGIN PROCESS(EN45,EN25,EN05M,EN05B,AIN45M,AIN45B,AIN25M,AIN25B,AIN05) IS BEGIN IF EN45='1' THEN DOUTM<=AIN45M(7 DOWNTO 0);DOUTB<=AIN45B(7 DOWNTO 0); ELSIF EN05M='1' THEN DOUTM<=AIN05(7 DOWNTO 0);DOUTB<=AIN05(7 DOWNTO 0); ELSIF EN25='1' THEN DOUTM<=AIN25M(7 DOWNTO 0);DOUTB<=AIN25B(7 DOWNTO 0); ELSIF EN05B='1' THEN DOUTM<=AIN05(7 DOWNTO 0);DOUTB<=AIN05(7 DOWNTO 0); END IF; END PROCESS;

END ARCHITECTURE ART;

--Jtkzq.vhd

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JTKZQ IS PORT(CLK,SM,SB:IN STD_LOGIC; MR,MG,MY,BY,BR,BG:OUT STD_LOGIC; DOUT1,DOUT2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY JTKZQ;

ARCHITECTURE ART OF JTKZQ IS COMPONENT JTDKZ IS PORT(CLK,SM,SB:IN STD_LOGIC; MR,MY0,MG0,BR,BY0,BG0:OUT STD_LOGIC); END COMPONENT JTDKZ; COMPONENT CSKZ IS PORT(INA:IN STD_LOGIC; OUTA:OUT STD_LOGIC); END COMPONENT CSKZ; COMPONENT CNT45S IS PORT(SB,CLK,EN45:IN STD_LOGIC; DOUT45M,DOUT45B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END COMPONENT CNT45S; COMPONENT CNT05S IS PORT(CLK,EN05M,EN05B:IN STD_LOGIC; DOUT5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END COMPONENT CNT05S; COMPONENT CNT25S IS PORT(SB,SM,CLK,EN25:IN STD_LOGIC; DOUT25M,DOUT25B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END COMPONENT CNT25S; COMPONENT XSKZ IS PORT(EN45,EN25,EN05M,EN05B:IN STD_LOGIC; AIN45M,AIN45B,AIN25M,AIN25B,AIN05:IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUTM,DOUTB:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END COMPONENT XSKZ; SIGNAL EN1,EN2,EN3,EN4:STD_LOGIC; SIGNAL S45M,S45B,S05,S25M,S25B:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN

U1:JTDKZ PORT MAP(CLK=>CLK,SM=>SM,SB=>SB,MR=>MR,MY0=>EN2,MG0=>EN1,BR=>BR,BY0=>EN4,BG0=>EN3); U2:CSKZ PORT MAP(INA=>EN1,OUTA=>MG); U3:CSKZ PORT MAP(INA=>EN2,OUTA=>MY); U4:CSKZ PORT MAP(INA=>EN3,OUTA=>BG); U5:CSKZ PORT MAP(INA=>EN4,OUTA=>BY);

U6:CNT45S PORT MAP(CLK=>CLK,SB=>SB,EN45=>EN1,DOUT45M=>S45M,DOUT45B=>S45B); U7:CNT05S PORT MAP(CLK=>CLK,EN05M=>EN2,DOUT5=>S05,EN05B=>EN4); U8:CNT25S PORT MAP(CLK=>CLK,SM=>SM,SB=>SB,EN25=>EN3,DOUT25M=>S25M,DOUT25B=>S25B); U9:XSKZ PORT MAP(EN45=>EN1,EN05M=>EN2,EN25=>EN3,EN05B=>EN4, AIN45M=>S45M,AIN45B=>S45B,AIN25M=>S25M,AIN25B=>S25B,AIN05=>S05, DOUTM=>DOUT1,DOUTB=>DOUT2); END ARCHITECTURE ART;

若SM 1 SB 1 LCK 时钟信号

若SM 时钟信号(4) SB 时钟信号(2) LCK 时钟信号(1)

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