单时钟周期单时钟周期数据通路设计 - 图文

实验五 单时钟周期数据通路设计

实验目的

通过实现MIPS核心指令集的单时钟周期数据通路，了解单周期数据通路的原理与实现。

实验设备

1. 装有ISE10.1的PC机一台 2. EDK-3SAISE实验箱一台

实验内容

用verilog描述如下的单时钟周期数据通路，先完成行为仿真，再加载到实验箱运行。

加载到实验箱运行时，要求输入clk,rst,pausen，输出pc[5:2]、aluout[7:0]。 1.模块代码

module CPUsec(clk,rst ,pcin,pcout,inst,bdata,aluout,signextout,memout,pcp4,

waddr,regdest,zero,aluctrl,aluop,jump,brance,memread,memtoreg,memwrite,alusrc,regwrite,beqaddrout,bzaddr,rdata1,rdata2,wdata,jaddr); input clk,rst;

output[31:0]pcin,pcout,inst,bdata,aluout,signextout,memout,pcp4,beqaddrout,bzaddr,rdata1,rdata2,wdata,jaddr;

output [4:0] waddr;

output regdest,zero,jump,brance,memread,memtoreg,memwrite,alusrc,regwrite; output [2:0] aluctrl; output [1:0] aluop; wire [31:0] pcin,pcout;

Pc pc(clk,rst,pcin,pcout); module IMem(rst,addr,inst); IMem imem(rst,pcout,inst);

RegFile rfile(clk,rst,inst[25:21],inst[20:16],waddr,rdata1,rdata2,wdata,regwrite); NBitMux2to1 muxregdest(inst[15:11],inst[20:16],regdest,waddr); defparam muxregdest.n=5;

Alu alu(rdata1,bdata,aluctrl,aluout,zero); SignExt signext(inst[15:0],signextout);

NBitMux2to1 muxbdata(signextout,rdata2,alusrc,bdata);

AluCtrl aluc(aluop,inst[5:0],aluctrl);

DMem dmem(clk,rst,memwrite,memread,aluout,rdata2,memout); NBitMux2to1 muxmemtoreg(aluout,memout,memtoreg,wdata); PcPlus4 pcplus4(pcout,pcp4);

BeqAddr beqaddr(pcp4,signextout,beqaddrout);

NBitMux2to1 muxbzaddr(pcp4,beqaddrout,bz,bzaddr); and(bz,branch,zero);

assign jaddr={pcp4[31:28],inst[25:0]<<2};

Controller

ctroller(inst[31:26],regdest,jump,brance,memread,memtoreg,aluop,memwrite,alurc,regwrite);

endmodule

功能仿真测试代码

功能仿真测试时序图

1. 模块代码

module CPU(clkin,rst,pausen,pc4,alu8); input clkin,rst,pausen; output [3:0] pc4;

output [7:0] alu8;

wire[31:0]pcin,pcout,inst,bdata,aluout,signextout,memout,pcp4,beqaddrout,bzaddr,rdata1,rdata2 ,wdata,jaddr; wire [4:0] waddr;

wire regdest,zero,jump,brance,memread,memtoreg,memwrite,alusrc,regwrite; wire [2:0] aluctrl; wire [1:0] aluop;

//输出pc[5:2]

assign pc4=pcout[5:2]; assign alu8=aluout[7:0]; assign clkout=clkin; and(clk,clkout,pausen);//暂停时钟 //module Pc(clk,rst,ipc,opc); Pc pc(clk,rst,pcin,pcout);

//module IMem(rst,addr,inst); IMem imem(rst,pcout,inst);

//module

RegFile(clk,rst,ReadAddr1,ReadAddr2,WriteAddr,ReadData1,ReadData2,WriteData,we);

RegFile rfile(clk,rst,inst[25:21],inst[20:16],waddr,rdata1,rdata2,wdata,regwrite);

//module NBitMux2to1(A,B,sel,F);

NBitMux2to1 muxregdest(inst[15:11],inst[20:16],regdest,waddr); defparam muxregdest.n=5;

//module Alu(A,B,Ctrl,F,zero);

Alu alu(rdata1,bdata,aluctrl,aluout,zero);

//module SignExt(In,Out);

SignExt signext(inst[15:0],signextout);

//module NBitMux2to1(A,B,sel,F);

NBitMux2to1 muxbdata(signextout,rdata2,alusrc,bdata);

//module AluCtrl(AluOp,Func,Ctrl); AluCtrl aluc(aluop,inst[5:0],aluctrl);

//module DMem(clk,rst,we,re,addr,din,dout);

DMem dmem(clk,rst,memwrite,memread,aluout,rdata2,memout);

//module NBitMux2to1(A,B,sel,F);

NBitMux2to1 muxmemtoreg(aluout,memout,memtoreg,wdata);

//module PcPlus4(ipc,opc); PcPlus4 pcplus4(pcout,pcp4);

//module BeqAddr(pcp4,imm32,addr);

BeqAddr beqaddr(pcp4,signextout,beqaddrout);

//module NBitMux2to1(A,B,sel,F);

NBitMux2to1 muxbzaddr(pcp4,beqaddrout,bz,bzaddr);

and(bz,branch,zero);

assign jaddr={pcp4[31:28],inst[25:0]<<2};

//module NBitMux2to1(A,B,sel,F);

NBitMux2to1 muxjump(bzaddr,jaddr,jump,pcin);

//module

Controller(op,regdest,jump,branch,memread,mem2reg,aluop,memwrite,alusrc,regwrite);

Controller

ctroller(inst[31:26],regdest,jump,brance,memread,memtoreg,aluop,memwrite,alusrc,regwrite); endmodule

2. 功能仿真测试代码

3. 功能仿真测试时序图

一、实验小结

本文来源：https://www.bwwdw.com/article/wvud.html