MAX1322ECM中文资料

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19-3157; Rev 2; 8/04

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input Ranges

General Description

FeaturesThe MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326 14-bit, analog-to-digital converters (ADCs) offer?8-/4-/2-Channel, 14-Bit ADCs

±1.5 LSB INL, ±1 LSB DNL, No Missing Codestwo, four, or eight independent input channels.90dBc SFDR, -86dBc THD, 76.5dB SINAD, 77dBIndependent track/hold (T/H) circuitry provides simultane-ous sampling for each channel. The MAX1316/SNR at 100kHz InputMAX1317/MAX1318 have a 0 to +5V input range with?On-Chip T/H Circuit for Each Channel

±6.0V fault-tolerant inputs. The MAX1320/MAX1321/10ns Aperture Delay

MAX1322 have a ±5V input range with ±16.5V fault-toler-50ps Channel-to-Channel T/H Matchingant inputs. The MAX1324/MAX1325/MAX1326 have a?Fast Conversion Time

±10V input range with ±16.5V fault-tolerant inputs. TheseOne Channel in 1.6μsADCs convert two channels in 2μs, and up to eight chan-Two Channels in 1.9μsnels in 3.8μs, and have an 8-channel throughput ofFour Channels in 2.5μs250ksps per channel. Other features include a 10MHzEight Channels in 3.7μsT/H input bandwidth, internal clock, internal (+2.5V) orexternal (+2.0V to +3.0V) reference, and power-?High Throughput

saving modes.

526ksps/ch for One Channel455ksps/ch for Two ChannelsA 16.6MHz, 14-bit, bidirectional, parallel interface pro-357ksps/ch for Four Channelsvides the conversion results and accepts digital config-250ksps/ch for Eight Channels

uration inputs.

These devices operate from a +4.75V to +5.25V analog?Flexible Input Ranges

supply and a separate +2.7V to +5.25V digital supply,0 to +5V (MAX1316/MAX1317/MAX1318)and consume less than 50mA total supply current.

±5V (MAX1320/MAX1321/MAX1322)±10V (MAX1324/MAX1325/MAX1326)These devices come in a 48-pin TQFP package and oper-ate over the extended -40°C to +85°C temperature range.

?No Calibration Needed

Applications

?14-Bit, High-Speed, Parallel Interface?Internal or External Clock

Multiphase Motor Control?+2.5V Internal Reference or +2.0V to +3.0VPower-Grid Synchronization

External ReferencePower-Factor Monitoring and Correction?+5V Analog Supply, +3V to +5V Digital Supply

Vibration and Waveform Analysis

46mA Analog Supply Current (typ)1.6mA Digital Supply Current (max)Shutdown and Power-Saving ModesSelector Guide?48-Pin TQFP Package (7mm ?7mm Footprint)

PARTINPUT RANGE (V)CHANNEL COUNTOrdering InformationMAX1316ECM0 to +58PARTTEMP RANGEPIN-PACKAGEMAX1317ECM0 to +54MAX1318ECM0 to +52MAX1316ECM-40°C to +85°C48 TQFPMAX1320ECM±58MAX1317ECM-40°C to +85°C48 TQFPMAX1321ECM±54MAX1318ECM-40°C to +85°C48 TQFPMAX1322ECM±52MAX1320ECM-40°C to +85°C48 TQFPMAX1324ECM±108MAX1321ECM-40°C to +85°C48 TQFPMAX1325ECM±104MAX1322ECM-40°C to +85°C48 TQFPMAX1326ECM±102MAX1324ECM-40°C to +85°C48 TQFPMAX1325ECM-40°C to +85°C48 TQFPPin Configurations and Typical Operating Circuits appear atMAX1326ECM-40°C to +85°C48 TQFPend of data sheet.

*Future product—contact factory for availability.

________________________________________________________________Maxim Integrated Products

1

For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326元器件交易网www.cecb2b.com

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326ABSOLUTE MAXIMUM RATINGS

AVDD to AGND.........................................................-0.3V to +6VDVDDto DGND.........................................................-0.3V to +6VAGND to DGND.....................................................-0.3V to +0.3VCH0–CH7, I.C. to AGND (MAX1316/MAX1317/MAX1318)...±6.0VCH0–CH7, I.C. to AGND (MAX1320/MAX1321/MAX1322).±16.5VCH0–CH7, I.C. to AGND (MAX1324/MAX1325/MAX1326).±16.5VINTCLK/EXTCLKto AGND.......................-0.3V to (AVDD + 0.3V)EOC, EOLC, WR, RD, CSto DGND.........-0.3V to (DVDD + 0.3V)CONVST, CLK, SHDN,

ALLON to DGND..................................-0.3V to (DVDD + 0.3V)MSV, REFMS, REF to AGND.....................-0.3V to (AVDD + 0.3V)

REF+, COM, REF- to AGND.....................-0.3V to (AVDD + 0.3V)D0–D13 to DGND....................................-0.3V to (DVDD+ 0.3V)Maximum Current into Any Pin Except AVDD, DVDD,

AGND, DGND...............................................................±50mAContinuous Power Dissipation

TQFP (derate 22.7mW/°C above +70°C)...................1818mWOperating Temperature Range...........................-40°C to +85°CJunction Temperature......................................................+150°CStorage Temperature Range.............................-65°C to +150°CLead Temperature (soldering, 10s).................................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(AVDD= +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1μF, CREF+=CREF-= 0.1μF, CREF+-to-REF-= 2.2μF || 0.1μF, CCOM= 2.2μF || 0.1μF, CMSV= 2.2μF || 0.1μF (unipolar devices, MAX1316/MAX1317/MAX1318), MSV = AGND (bipolar devices, MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326), fCLK = 10MHz,50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = TMINto TMAX, unless otherwise noted. Typical val-ues are at TA= +25°C.)PARAMETERSTATIC PERFORMANCE (Note 1)ResolutionIntegral NonlinearityDifferential NonlinearityOffset ErrorOffset DriftChannel Offset MatchingGain ErrorChannel Gain-Error MatchingGain Temperature CoefficientDYNAMIC PERFORMANCE (at fIN = 100kHz, -0.4dB FS)Signal-to-Noise RatioSignal-to-Noise and DistortionRatioSpurious-Free Dynamic RangeTotal Harmonic DistortionChannel-to-Channel IsolationANALOG INPUTS (CH0–CH7)MAX1316/MAX1317/MAX1318Input Voltage RangeMAX1320/MAX1321/MAX1322MAX1324/MAX1325/MAX13260-5-10+5+5+10VSNRSINADSFDRTHD83UnipolarBipolarUnipolarBipolar74.57574.575837676.57676.593-90-83dBdBdBcdBcdBNINLDNL(Note 2)No missing codes (Note 2)Unipolar devicesBipolar devicesUnipolar devicesBipolar devicesUnipolar devices between all channelsBipolar devices between all channels(Note 3)Between all channels3-4-43525±88060±402514±0.8±0.5±2.0±1±40±40BitsLSBLSBLSBppm/°CLSBLSBLSBppm/°CSYMBOLCONDITIONSMINTYPMAXUNITS2_______________________________________________________________________________________元器件交易网www.cecb2b.com

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input Ranges

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1μF, CREF+=CREF-= 0.1μF, CREF+-to-REF-= 2.2μF || 0.1μF, CCOM= 2.2μF || 0.1μF, CMSV= 2.2μF || 0.1μF (unipolar devices, MAX1316/MAX1317/MAX1318), MSV = AGND (bipolar devices, MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326), fCLK = 10MHz,50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = TMINto TMAX, unless otherwise noted. Typical val-ues are at TA= +25°C.)

PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSMAX1316/MAX1317/MAX1318VIN = +5V0.540.72VIN = 0V-0.157-0.12Input Current (Note 4)MAX1320/MAX1321/MAX1322VIN = +5V0.290.39VIN = -5V-1.16-0.87mAMAX1324/MAX1325/MAX1326VIN = +10V0.560.74VIN = -10V-1.13-0.85MAX1316/MAX1317/MAX13187.58Input Resistance (Note 4)MAX1320/MAX1321/MAX13228.66?MAX1324/MAX1325/MAX132614.26Input Capacitance15pFTRACK/HOLDOne channel526External-Clock Throughput RateTwo channels455(Note 5)Four channels357kspsEight channels250One channel (INTCLK/EXTCLK = AVDD)526Internal-Clock Throughput RateTwo channels (INTCLK/EXTCLK = AVDD)455(Note 5)Four channels (INTCLK/EXTCLK = AVkspsDD)357Eight channels (INTCLK/EXTCLK = AVDD)250Small-Signal Bandwidth10MHzFull-Power Bandwidth10MHzAperture Delay16nsAperture Jitter50psRMSAperture-Delay Matching100psINTERNAL REFERENCEREFMS VoltageVREFMS2.4752.5002.525VREF VoltageVREF2.4752.5002.525VREF Temperature Coefficient30ppm/°CEXTERNAL REFERENCE (REFMS AND REF EXTERNALLY DRIVEN)Input Current-250+250μAREFMS Input Voltage RangeVREFMSUnipolar devices2.02.53.0VREF Voltage Input RangeVREF2.02.53.0VREF Input Capacitance15pFREFMS Input Capacitance15pFDIGITAL INPUTS (D0–D7, RD, WR, CS, CLK, SHDN, ALLON, CONVST)Input-Voltage HighVIH0.7 xDVDDV_______________________________________________________________________________________3MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326元器件交易网www.cecb2b.com

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326ELECTRICAL CHARACTERISTICS (continued)

(AVDD= +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1μF, CREF+=CREF-= 0.1μF, CREF+-to-REF-= 2.2μF || 0.1μF, CCOM= 2.2μF || 0.1μF, CMSV= 2.2μF || 0.1μF (unipolar devices, MAX1316/MAX1317/MAX1318), MSV = AGND (bipolar devices, MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326), fCLK = 10MHz,50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = TMINto TMAX, unless otherwise noted. Typical val-ues are at TA= +25°C.)

PARAMETERInput-Voltage LowInput HysteresisInput CapacitanceInput CurrentCINIINVIN = 0V or DVDD0.7 xAVDD0.3 xAVDDDVDD -0.60.40.06154.752.70MAX1316/MAX1317/MAX1318, all channelsselectedAnalog-Supply CurrentIAVDDMAX1320/MAX1321/MAX1322, all channelsselectedMAX1324/MAX1325/MAX1326, all channelsselectedMAX1316/MAX1317/MAX1318,all channels selectedDigital-Supply Current (Note 6)IDVDDCLOAD =100pFMAX1320/MAX1321/MAX1322,all channels selectedMAX1324/MAX1325/MAX1326,all channels selectedShutdown Current (Note 7)Power-Supply Rejection RatioIAVDDIDVDDPSRRVSHDN = DVDD, VCH = floatVRD = VWR = DVDD, VSHDN = DVDDSYMBOLVILCONDITIONSMINTYPMAX0.3 xDVDDUNITSVmVpF1515±1μACLOCK-SELECT INPUT (INTCLK/EXTCLK)Input-Voltage HighInput-Voltage LowDIGITAL OUTPUTS (D0–D13, EOC, EOLC)Output-Voltage HighOutput-Voltage LowTri-State Leakage CurrentTri-State Output CapacitancePOWER SUPPLIESAnalog-Supply VoltageDigital-Supply VoltageAVDDDVDD5.255.254646461115151511.61.61.6100.1502μAdBmAmAVVVOHVOLISOURCE = 0.8mAISINK = 1.6mARD ≥ VIH or CS ≥ VIHRD ≥ VIH or CS ≥ VIHVVμApFVV1AVDD = +4.75V to +5.75V (Note 8)4_______________________________________________________________________________________

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input Ranges

TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3)

PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInternal clock1.61.8μsTime-to-First-Conversion ResulttCONVExternal clock, Figure 616ClockcyclesInternal clock0.30.36μsTime-to-Next-Conversion ResulttNEXTExternal clock, Figure 63ClockcyclesCONVST Pulse-Width Low(Acquisition Time)tACQ(Note 9)0.16100μsCS Pulse Widtht230nsRD Pulse-Width Lowt330nsRD Pulse-Width Hight430nsWR Pulse-Width Lowt530nsCS to WRt6(Note 10)nsWR to CSt7(Note 10)nsCS to RDt8(Note 10)nsRD to CSt9(Note 10)nsData-Access Time(RD Low to Valid Data)t1030nsBus-Relinquish Time (RD High)t1130nsInternal clock80nsEOC Pulse Widtht12External clock, Figure 61ClockcyclesInput-Data Setup Timet1410nsInput-Data Hold Timet1510nsExternal-Clock Periodt160.0810.00μsExternal-Clock High Periodt17Logic sensitive to rising edges20nsExternal-Clock Low Periodt18Logic sensitive to rising edges20nsExternal-Clock Frequency(Note 11)0.112.5MHzInternal-Clock Frequency10MHzCONVST High to CLK Edget1920(Note 12)nsEOC Low to RDt200nsNote 1:For the MAX1316/MAX1317/MAX1318, VIN= 0 to +5V. For the MAX1320/MAX1321/MAX1322, VIN= -5V to +5V. For theMAX1324/MAX1325/MAX1326, VIN= -10V to +10V.

Note 2:All channel performance is guaranteed by correlation to a single channel test.Note 3:Offset nulled.

Note 4:The analog input resistance is terminated to an internal bias point. Calculate the analog input current using:

ICH_=

VCH_?VBIAS

RCH_

for VCHwithin the input voltage range.

Note 5:Throughput rate is given per channel. Throughput rate is a function of clock frequency (fCLK= 10MHz). See the DataThroughputsection for more information.

Note 6:

All analog inputs are driven with an FS 100kHz sine wave.

_______________________________________________________________________________________5

MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3) (continued)

Note 7:

Shutdown current is measured with analog input floating. The large amplitude of the maximum shutdown current specifi-cation is due to automatic test equipment limitations.

Note 8:Defined as the change in positive full scale caused by ±5% variation in the nominal supply voltage.

Note 9:CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor

droop.

Note 10:CS-to-WRand CS-to-RDpins are internally AND together. Setup and hold times do not apply.

Note 11:Minimum clock frequency is limited only by the internal T/H droop rate. Limit the time between the falling edge of CONVST

to the falling edge of EOLC to a maximum of 0.25ms.

Note 12:To avoid T/H droop degrading the sampled analog input signals, the first clock pulse should occur within 10μs of the ris-ing edge of CONVST, and have a minimum clock frequency of 100kHz.

Typical Operating Characteristics

(AVDD = +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), see the Typical Operating Circuits sec-tion, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)

INTEGRAL NONLINEARITYvs. DIGITAL OUTPUT CODE

MAX1316 toc01DIFFERENTIAL NONLINEARITYvs. DIGITAL OUTPUT CODE

0.750.50DNL (LSB)0.250-0.25-0.50-0.75-1.00

30

0

4096

8192

12288

16384

4.75

MAX1316 toc02ANALOG SUPPLY CURRENTvs. SUPPLY VOLTAGE

MAX1316 toc031.000.750.50INL (LSB)0.250-0.25-0.50-0.75-1.00

0

4096

8192

12288

1.0050

SUPPLY CURRENT (mA)45

40

35

fSAMPLE = 250kspsALL 8 CHANNELSDRIVEN WITH FULL-SCALE SINE WAVES4.87

5.00

5.12

5.25

16384

DIGITAL OUTPUT CODEDIGITAL OUTPUT CODESUPPLY VOLTAGE (V)

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

MAX1316 toc04SHUTDOWN CURRENTvs. SUPPLY VOLTAGE

MAX1316 toc05SHUTDOWN CURRENTvs. TEMPERATURE

MAX1316 toc06500.80.8

SHUTDOWN CURRENT (μA)SUPPLY CURRENT (mA)45

fSAMPLE = 250kspsALL 8 CHANNELSDRIVEN WITH FULL-SCALE SINE WAVES0.6

ANALOG SHUTDOWN CURRENTSHUTDOWN CURRENT (μA)0.6

ANALOG SHUTDOWN CURRENT400.4

DIGITALSHUTDOWN CURRENT0.4

DIGITALSHUTDOWN CURRENT350.20.2

30-40

-15

10

35

60

85

TEMPERATURE (°C)

02.5

3.5

4.5

5.5

SUPPLY VOLTAGE (V)

0-40

-15

10

35

60

85

TEMPERATURE (°C)

6_______________________________________________________________________________________

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input Ranges

Typical Operating Characteristics (continued)(AVDD = +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), see the Typical Operating Circuits sec-tion, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)

INTERNAL REFERENCE VOLTAGEINTERNAL REFERENCE VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

vs. TEMPERATURE

OFFSET ERROR vs. SUPPLY VOLTAGE

2.500472.50481.59000ccoocott t66 62.500312.50311331.03111XXAAXMMAM2.50022.502)BS0.52.50012.501L( ))VVR((O FER2.5000 FR0ERR2.500EVV TE2.49992.499S-0.5FFO2.49982.498-1.02.49972.497-1.52.4996

2.496

NORMALIZED AT T-2.0

A = +25°C4.7

4.8

4.9

5.05.1

5.2

5.3

-40-15103560854.75

4.85

4.95

5.05

5.15

5.25

AVDD (V)

TEMPERATURE (°C)

AVDD (V)

OFFSET ERROR vs. TEMPERATURE

GAIN ERROR vs. SUPPLY VOLTAGE

GAIN ERROR vs. TEMPERATURE

0.0401610.09

2111cccooottt 6660.0311131533111XX0.08XAAAMMM)R0.02)0.07S)RFB14%SSF(0.01L (%0.06R ( ORRRO13OR0RR0.05ER ERT EE S-0.01N12IANIFGA0.04FGO-0.02110.03-0.03100.02NORMALIZED AT TC-0.04

A = +25°9

0.01

-40

-15

10

35

60

854.754.854.955.055.155.25-40-1510356085

TEMPERATURE (°C)AVDD (V)TEMPERATURE (°C)

_______________________________________________________________________________________7

MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326元器件交易网www.cecb2b.com

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326Typical Operating Characteristics (continued)(AVDD = +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), see the Typical Operating Circuits sec-tion, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)

SIGNAL-TO-NOISE RATIOvs. CLOCK FREQUENCY

fANALOG_IN = 103kHzfSAMPLE = 490kHzfCLK = 10MHzSINAD = 76.7dBSNR = 77.0dBTHD = -88.3dBSFDR = 91.0dBMAX1316 toc13MAX1316 toc14FFT

0-20-40-60-80-100-120-140

0

0.05

0.10

0.15

0.20

0.25

FREQUENCY (MHz)

80797877

SIGNAL-TO-NOISE PLUS DISTORTION

vs. CLOCK FREQUENCY

797877SINAD (dB)76757473727170

fIN = 100kHzMAX1316 toc1580

fIN = 100kHzAMPLITUDE (dB)SNR (dB)767574737271708

10

12

14fCLK (MHz)

16

18

20

8101214fCLK (MHz)

161820

EFFECTIVE NUMBER OF BITSvs. CLOCK FREQUENCY

MAX1316 toc16TOTAL HARMONIC DISTORTION

vs. CLOCK FREQUENCY

MAX1316 toc17SPURIOUS-FREE DYNAMIC RANGE

vs. CLOCK FREQUENCY

9590

MAX1316 toc17b13.5

fIN = 100kHz13.012.5

-70-75-80-85-90-95-100

100

ENOB (BITS)SFDR (dB)THD (dB)85807570

12.011.511.010.5

8

10

12

14fCLK (MHz)

16

18

20

6560

8

10

12

14fCLK (MHz)

16

18

20

8

10

12

14fCLK (MHz)

16

18

20

8_______________________________________________________________________________________

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input Ranges

Typical Operating Characteristics (continued)(AVDD = +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), see the Typical Operating Circuits sec-tion, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)

CONVERSION TIME

CONVERSION TIMEOUTPUT HISTOGRAM

vs. ANALOG SUPPLY VOLTAGE

vs. TEMPERATURE

(DC INPUT)

2.0890t1t14500

2cCONVINTERNAL CLOCKcCONVINTERNAL CLOCK2.0cooott 1.8 t1.8 6611331138156131XX4000AAX1.6M1.6MA)3500M)ssμμ(( 1.4 1.4EEM3000MIIT1.2T1.2S TNNN2500OOU2306I1.0I1.0SSORRCEE2000V0.8V0.8NNO0.6tONEXTC0.6tNEXT15001562C0.40.410000.20.250034115400

0

013104.750

4.8755.0005.1255.250-40-1510356085820982108211821282138214821582168217

ANALOG SUPPLY VOLTAGE (V)TEMPERATURE (°C)

DIGITAL OUTPUT CODE

Pin Description

PINMAX1316MAX1317MAX1318MAX1320MAX1321MAX1322NAMEFUNCTIONMAX1324MAX1325MAX1326Analog Supply Input. AVDD is the power input for the analog section1, 15, 171, 15, 171, 15, 17AVDDof the converter. Apply 4.75V to 5.25V to AVDD. Bypass AVDD toAGND (pin 14 to pin 15, pin 16 to pin 17, pin 1 to pin 2) with a 0.1μFcapacitor at each AVDD input.2, 3, 14, 16, 232, 3, 14, 16, 232, 3, 14, 16, 23AGNDAnalog Ground. AGND is the power return for AVDD. Connect allAGNDs together.444CH0Channel 0 Analog Input555CH1Channel 1 Analog InputMidscale Voltage Bypass. For the MAX1316/MAX1317/MAX1318,666MSVconnect a 2.2μF and a 0.1μF capacitor from MSV to AGND. For theMAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326,connect MSV directly to AGND.77—CH2Channel 2 Analog Input88—CH3Channel 3 Analog Input9——CH4Channel 4 Analog Input_______________________________________________________________________________________9

MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326元器件交易网www.cecb2b.com

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326Pin Description (continued)PINMAX1316MAX1320MAX1324101112MAX1317MAX1321MAX1325———MAX1318MAX1322MAX1326———NAMEFUNCTIONCH5CH6CH7INTCLK/EXTCLKChannel 5 Analog InputChannel 6 Analog InputChannel 7 Analog InputClock-Mode Select Input. Use INTCLK/EXTCLK to select the internalor external conversion clock. Connect INTCLK/EXTCLK to AVDD toselect the internal clock. Connect INTCLK/EXTCLK to AGND to usean external clock connected to CLK.Midscale Reference Bypass or Input. REFMS is the bypass point foran internally generated reference voltage. For the MAX1316/MAX1317/MAX1318, connect a 0.1μF capacitor from REFMS toAGND. For the MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326, connect REFMS directly to REF and bypasswith a 0.1μF capacitor from REFMS to AGND.ADC Reference Bypass or Input. REF is the bypass point for aninternally generated reference voltage. Bypass REF with a 0.01μFcapacitor to AGND. REF can be driven externally by a precisionexternal voltage reference.Positive Reference Bypass. REF+ is the bypass point for aninternally generated reference voltage. Bypass REF+ with a 0.1μFcapacitor to AGND. Also bypass REF+ to REF- with a 2.2μF and a0.1μF capacitor.Reference Common Bypass. COM is the bypass point for aninternally generated reference voltage. Bypass COM to AGND witha 2.2μF and a 0.1μF capacitor.Negative Reference Bypass. REF- is the bypass point for aninternally generated reference voltage. Bypass REF- with a 0.1μFcapacitor to AGND. Also bypass REF- to REF+ with a 2.2μF and a0.1μF capacitor.Digital I/O Bit 0 of 14-Bit Parallel Data Bus. High impedance whenRD = 1 or CS = 1.Digital I/O Bit 1 of 14-Bit Parallel Data Bus. High impedance whenRD = 1 or CS = 1.Digital I/O Bit 2 of 14-Bit Parallel Data Bus. High impedance whenRD = 1 or CS = 1.131313181818REFMS191919REF202020REF+212121COM222222REF-242526242526242526D0D1D210______________________________________________________________________________________

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input Ranges

Pin Description (continued)PINMAX1316MAX1317MAX1318MAX1320MAX1321MAX1322NAMEFUNCTIONMAX1324MAX1325MAX1326272727D3Digital I/O Bit 3 of 14-Bit Parallel Data Bus. High impedance whenRD = 1 or CS = 1.282828D4Digital I/O Bit 4 of 14-Bit Parallel Data Bus. High impedance whenRD = 1 or CS = 1.292929D5Digital I/O Bit 5 of 14-Bit Parallel Data Bus. High impedance whenRD = 1 or CS = 1.303030D6Digital I/O Bit 6 of 14-Bit Parallel Data Bus. High impedance whenRD = 1 or CS = 1.313131D7Digital I/O Bit 7 of 14-Bit Parallel Data Bus. High impedance whenRD = 1 or CS = 1.323232D8Digital Out Bit 8 of 14-Bit Parallel Data Bus. High impedance whenRD = 1 or CS = 1.333333D9Digital Out Bit 9 of 14-Bit Parallel Data Bus. High impedance whenRD = 1 or CS = 1.343434D10Digital Out Bit 10 of 14-Bit Parallel Data Bus. High impedance whenRD = 1 or CS = 1.353535D11Digital Out Bit 11 of 14-Bit Parallel Data Bus. High impedance whenRD = 1 or CS = 1.363636D12Digital Out Bit 12 of 14-Bit Parallel Data Bus. High impedance whenRD = 1 or CS = 1.373737D13Digital Out Bit 13 of 14-Bit Parallel Data Bus. High impedance whenRD = 1 or CS = 1.383838DVDDDigital-Supply Input. Apply +2.7V to +5.25V to DVDD. Bypass DVDDto DGND with a 0.1μF capacitor.Digital-Supply GND. DGND is the power return for DVDD. Connect393939DGNDDGND to AGND at only one point (see the Layout, Grounding, andBypassing section).404040EOCEnd-of-Conversion Output. EOC goes low to indicate the end of aconversion. EOC returns high after one clock period.______________________________________________________________________________________11

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326Pin Description (continued)PINMAX1316MAX1320MAX132441MAX1317MAX1321MAX132541MAX1318MAX1322MAX132641NAMEFUNCTIONEOLCEnd-of-Last-Conversion Output. EOLC goes low to indicate the endof the last conversion. EOLC returns high when CONVST goes lowfor the next conversion sequence.Read Input. When RD and CS go low, the device initiates a readcommand of the parallel data buses, D0–D13. D0–D13 are highimpedance while either RD or CS is high.Write Input. The write command initiates when WR and CS go low. Awrite command loads the configuration byte on D0–D7.Chip-Select Input. Pulling CS low activates the digital interface.D0–D13 are high impedance while either CS or RD is high.Convert-Start Input. Driving CONVST high places the device in holdmode and initiates the conversion process. The analog inputs aresampled on the rising edge of CONVST. When CONVST is low, theanalog inputs are tracked.External-Clock Input. CLK accepts an external-clock signal up to15MHz. Connect CLK to DGND for internally clocked conversions.To select external-clock mode, set INTCLK/EXTCLK = 0.Shutdown Input. Set SHDN = 0 for normal operation. Set SHDN = 1for shutdown mode.Enable-All-Channels Input. Drive ALLON high to enable all inputchannels. When ALLON is low, only input channels selected asactive are powered. Select channels as active using theconfiguration register.Internally Connected. Connect I.C. to AGND. For factory use only.424242RD434443444344WRCS454545CONVST464646CLK474747SHDN484848ALLON—9–127–12I.C.12______________________________________________________________________________________

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input Ranges

MAX1316–MAX1318AVDDMAX1320–MAX1322DVDDMAX1324–MAX1326D13CH0S/H8 x 114-BIT8 x 14 OUTPUT D8MUX ADCSRAMDRIVERSD7CH7S/HD0MSVCONFIGURATION*REGISTERWRREF+CSCOMINTERFACERDREF-ANDCONTROLCONVSTSHDN5k?CLKREF5k?ALLONREFMSEOC2.500VEOLCINTCLK/EXTCLKDGNDAGND*SWITCH CLOSED ON UNIPOLAR DEVICES, OPEN ON BIPOLAR DEVICESFigure 1. Functional Diagram

Detailed Description

Analog Inputs

The MAX1316–MAX1318/MAX1320–MAX1322/MAX1324-T/H

MAX1326 are 14-bit ADCs. They offer two, four, or eightTo preserve phase information across these multichan-(independently selectable) input channels, each with itsnel devices, each input channel has a dedicated own T/H circuitry. Simultaneous sampling of all activeT/H amplifier.

channels preserves relative phase information, makingthese devices ideal for motor control and power monitor-Use a low-input source impedance to minimize gain-ing. These devices are available with 0 to +5V, ±5V, anderror harmonic distortion. The time required for the T/H±10V input ranges. The 0 to +5V devices feature ±6Vto acquire an input signal depends on the input sourcefault-tolerant inputs. The ±5V and ±10V devices featureimpedance. If the input signal’s source impedance is±16.5V fault-tolerant inputs. Two channels convert in 2μs;high, the acquisition time lengthens and more timeall eight channels convert in 3.8μs, with a maximum 8-must be allowed between conversions. The acquisitionchannel throughput of 263ksps per channel. Internal ortime (texternal reference and internal- or external-clock capabil-acquire the signal. Use the following formula to calcu-1) is the maximum time the device takes toity offer great flexibility and ease of use. A write-only con-late acquisition time:

figuration register can mask out unused channels, and at1= 10 (RS+ RIN) x 6pF

shutdown feature reduces power. A 16.6MHz, 14-bit, par-where RIN= 2.2k?, RS= the input signal’s sourceallel data bus outputs the conversion result. Figure 1impedance, and tshows the functional diagram of these devices.

impedance of less than 1001is never less than 180ns. A source?does not significantlyaffect the ADC’s performance.

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326To improve the input-signal bandwidth under AC condi-tions, drive the input with a wideband buffer (>50MHz)that can drive the ADC’s input capacitance and settlequickly. For example, the MAX4265 can be used for +5Vunipolar devices, or the MAX4350 can be used for ±5Vbipolar inputs.

The T/H aperture delay is typically 13ns. The aperture-delay mismatch between T/Hs of 50ps allows the relativephase information of up to eight different inputs to bepreserved. Figure 2 shows a simplified equivalent inputcircuit, illustrating the ADC’s sampling architecture.Input Bandwidth

The input tracking circuitry has a 12MHz small-signalbandwidth, making it is possible to digitize high-speedtransient events and measure periodic signals withbandwidths exceeding the ADC’s sampling rate by usingundersampling techniques. To avoid high-frequencysignals being aliased into the frequency band of interest,anti-alias filtering is recommended.

Input Range and Protection

These devices provide ±10V, ±5V, or 0 to +5V analoginput voltage ranges. Figure 2 shows the equivalent inputcircuit. Overvoltage protection circuitry at the analoginput provides ±16.5V fault protection for the bipolar inputdevices and ±6.0V fault protection for the unipolar inputdevices. This fault-protection circuit limits the currentgoing into or out of the device to less than 50mA, provid-ing an added layer of protection from momentary over-voltage or undervoltage conditions at the analog input.

Power-Saving Modes

Shutdown Mode

During shutdown, the analog and digital circuits in thedevice power down and the device draws less than100μA from AVDD, and less than 100μA from DVDD.Select shutdown mode using the SHDN input. Set SHDNhigh to enter shutdown mode. After coming out of shut-down, allow a 1ms wake-up time before making the firstconversion. When using an external clock, apply at least20 clock cycles with CONVST high before making the firstconversion. When using internal-clock mode, wait at least2μs before making the first conversion.

ALLON

ALLON is useful when some of the analog input channelsare selected (see theConfiguration Registersection).Drive ALLON high to power up all input channel circuits,regardless of whether they are selected as active by theconfiguration register. Drive ALLON low or connect toground to power only the input channels selected asactive by the configuration register, saving 2mA perchannel (typ). The wake-up time for any channel turnedon with the configuration register is 2μs (typ) whenALLON is low. The wake-up time with ALLON high isonly 0.01μs. New configuration-register informationdoes not become active until the next CONVST fallingedge. Therefore, when using software to control powerstates (ALLON = 0), pulse CONVST low once beforeapplying the actual CONVST signal (Figure 3). With anexternal clock, apply at least 15 clock cycles beforethe second CONVST. If using internal-clock mode, waitat least 1.5μs or until the first EOCbefore generatingthe second CONVST.

MAX1316–MAX1318MAX1320–MAX1322MAX1324–MAX1326R1CH_R2VBIASCPAR1pFTable 1. Conversion Times Using theInternal ClockNUMBER OF CHANNELS5pFINTERNAL-CLOCKCONVERSION TIME1.61.92.22.52.83.13.43.712345INPUT RANGE (V) R1 (k? R2 (k)?)VBIAS (V)0 TO +5±5±103.336.6713.335.002.862.350.902.502.06678Figure 2. Typical Input Circuit14

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input Ranges

tACQtACQSAMPLECONVSTDUMMYACTUALCONVERSIONCONVERSIONSTARTSTARTWRLATCHDATA-IN CHANGES ONE OR MORE CHANNELSFROM POWER-DOWN TO ACTIVE MODED0–D7DATA-IN1234514151CLK>14 CYCLESEOCEOLCFigure 3. Software Channel Wake-Up Timing (ALLON = 0)

Clock Modes

MAX4265), which settles quickly and is stable with theThese devices provide an internal clock of 10MHzADC’s capacitive load (in parallel with any bypass(typ). Alternatively, an external clock can be used.capacitors on the analog inputs).

Internal Clock

Applications SectionInternal-clock mode frees the microprocessor from theburden of running the ADC conversion clock. For internal-Digital Interface

clock operation, connect INTCLK/EXTCLKto AVDDandThe bidirectional, parallel, digital interface sets the 8-bitconnect CLK to DGND. Table 1 illustrates the total con-configuration register (see the Configuration Registerversion time using internal-clock mode.

section) and outputs the 14-bit conversion result. Theinterface includes the following control signals: chipExternal Clock

select (CS), read (RD), write (WR), end of conversionFor external-clock operation, connect INTCLK/EXTCLK(EOC), end of last conversion (EOLC), convert startto AGND and connect an external-clock source to CLK.(CONVST), shutdown (SHDN), all on (ALLON), internal-Note that INTCLK/EXTCLKis referenced to the analogclock select (INTCLK /EXTCLK), and external-clock inputpower supply, AVDD. The external-clock frequency can(CLK). Figures 4, 5, 6, 7, Table 4, and the Timingbe up to 15MHz, with a duty cycle between 30% andCharacteristicssection show the operation of the inter-70%. Clock frequencies of 100kHz and lower can beface. D0–D7 are bidirectional, and D8–D13 are outputused, but the droop in the T/H circuits reduce linearity.

only. All bits are high impedance when RD= 1 or CS= 1.

Selecting an Input Buffer

Configuration Register

Most applications require an input buffer to achieve 14-Enable channels as active by writing to the configurationbit accuracy. Although slew-rate and bandwidth areregister through I/O lines D0–D7 (Table 2). The bits in theimportant, the most critical specification is settling time.configuration register map directly to the channels, withThe sampling requires a relatively brief sampling inter-D0 controlling channel zero, and D7 controlling channelval of 150ns. At the beginning of the acquisition, theseven. Setting any bit high activates the correspondinginternal sampling capacitor array connects to CH_ (theinput channel, while resetting any bit low deactivates theamplifier output), causing some output disturbance.corresponding channel. Devices with fewer than eightEnsure the amplifier is capable of settling to at least 14-channels contain some bits that have no function.

bit accuracy during this interval. Use a low-noise, low-distortion, wideband amplifier (such as the MAX4350 or

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MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326Table 2. Configuration RegisterPART NO.MAX1316MAX1320MAX1324MAX1317MAX1321MAX1325MAX1318MAX1322MAX1326STATEONOFFONOFFONOFFBIT/CHANNELD0/CH0101010D1/CH1101010D2/CH21010NANAD3/CH31010NANAD4/CH410NANANANAD5/CH510NANANANAD6/CH610NANANANAD7/CH710NANANANANA = Not applicable.

To write to the configuration register, pull CSand WRlow, load bits D0–D7 onto the parallel bus, and forceWRhigh. The data are latched on the rising edge ofWR(Figure 4). It is possible to write to the configurationregister at any point during the conversion sequence;however, it is not active until the next convert-start sig-nal. At power-up, write to the configuration register toselect the active channels before beginning a conver-sion. Shutdown does not change the configuration reg-ister. See the Shutdown Mode and theALLONsectionsfor information about using the configuration register forpower saving.

RDt2CSt6WRt14D0–D7t15DATA-INt5t7Starting a Conversion

To start a conversion using internal-clock mode, pullCONVST low for at least the acquisition time (t1). TheT/H acquires the signal while CONVST is low, and con-version begins on the rising edge of CONVST. An end-of-conversion signal (EOC) pulses low when the firstresult becomes available, and for each subsequentresult until the end of the conversion cycle. The end-of-last-conversion signal (EOLC) goes low when the lastconversion result is available (Figures 5, 6, and 7).To start a conversion using external-clock mode, pullCONVST low for at least the acquisition time (t1). The T/Hacquires the signal while CONVST is low, and conversionbegins on the rising edge of CONVST. Apply an externalclock to CLK. To avoid T/H droop degrading the sampledanalog input signals, the first clock pulse should occurwithin 10μs from the rising edge of CONVST, and have aminimum clock frequency of 100kHz. The first conversionresult is available for read on the rising edge of the 17thclock cycle, and subsequent conversions after every thirdclock cycle thereafter (Figures 5, 6, and 7).

16

Figure 4. Write Timing

In both internal- and external-clock modes, CONVSTmust be held high until the last conversion result isread. For best operation, the rising edge of CONVSTmust be a clean, high-speed, low-jitter digital signal.Table 3 shows the total throughput as a function of theclock frequency and the number of channels selectedfor conversion. The calculations use the nominal speedof the internal clock (10MHz) and a 200ns CONVSTpulse width.

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input Ranges

Data Throughput

Reading a Conversion Result

The data throughput (fTH) of the MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326 is a functionReading During a Conversion

of the clock speed (fCLK). In internal-clock mode, fFigures 5 and 6 show the interface signals for initiating a≤fCLK=10MHz. In external-clock mode, 100kHz read operation during a conversion cycle. These figures12.5MHz. When reading during conversion (Figures 5CLK≤show two channels selected for conversion. If more chan-and 6), calculate fTHas follows:

nels are selected, the results are available successivelyevery third clock cycle. CScan be low at all times; it canfTH=

1

be low during the RDcycles, or it can be the same as RD.tQUIET+

16+3x(N?1)+1

After initiating a conversion by bringing CONVST high,fCLKwait for EOCto go low (about 1.6μs in internal-clockwhere N is the number of active channels and tmode or 17 clock cycles in external-clock mode) beforeincludes acquistion time tis the period of busQUIETACQ. tQUIETreading the first conversion result. Read the conversioninactivity before the rising edge of CONVST. Typically useresult by bringing RDlow, thus latching the data to thetQUIET= tACQ+ 50ns, and prevent disturbance on theparallel digital-output bus. Bring RDhigh to release theoutput bus from corrupting signal acquistion. See thedigital bus. Wait for the next falling edge of EOC(aboutStarting a Conversion section for more information.

300ns in internal-clock mode or three clock cycles inexternal-clock mode) before reading the next result.When the last result is available, EOLCgoes low.

Table 3. Throughput vs. Channels Sampled (tQUIET= tACQ= 200ns, fCLK= 10MHz)CHANNELSCLOCK CYCLESCLOCK CYCLE FORTOTALSAMPLES PERTHROUGHPUTSAMPLEDUNTIL LASTREADING LASTCONVERSIONSECONDPER CHANNEL (N)RESULTCONVERSIONTIME (ns)(ksps)(ksps)1161190052652621912200909455322125001200400425128001429357528131001613323631134001765294734137001892270837140002000250SAMPLEt1t13CONVSTTRACKHOLDTRACKtCONVtNEXTt12EOCt20RDt10t3D0–D13CH0CH1t11Figure 5. Read During Conversion—Two Channels Selected, Internal Clock______________________________________________________________________________________17MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326元器件交易网www.cecb2b.com

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326SAMPLEtACQCONVSTTRACKt19CLK12316t1617t13HOLDt17181920t182122231TRACKEOCt12RDt10D0–D13CH0t11CH1t3tQUIETFigure 6. Read During Conversion—Two Channels Selected, External ClockSAMPLEtACQt13HOLDt19t172t16383940t18414243CONVSTTRACKCLK1EOCONLY LAST PULSE SHOWNt12EOLCCSt8RDt3t4t9tQUIETD0–D13CH0t10t11CH1CH2CH3CH4CH5CH6CH7Figure 7. Reading After Conversion—Eight Channels Selected, External Clock18

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input Ranges

Reading After Conversion

Layout, Grounding, and Bypassing

Figure 7 shows the interface signals for a read operationFor best performance use PC boards with groundafter a conversion with all eight channels enabled. At theplanes. Board layout should ensure that digital andfalling edge of EOLC, on the 38th clock pulse after the ini-analog signal lines are separated from each other. Dotiation of a conversion, driving CSand RDlow places thenot run analog and digital lines parallel to one anotherfirst conversion result onto the parallel bus, which can be(especially clock lines), or do not run digital lineslatched on the rising edge of RD. Successive low pulsesunderneath the ADC package. Figure 8 shows the rec-of RDplace the successive conversion results onto theommended system ground connections when not usingbus. Pulse CONVST low to initiate a new conversion.

a ground plane. A single-point analog ground (starPower-Up Reset

ground point) should be established at AGND, sepa-At power-up, all channels are selected for conversionrate from the logic ground. All other analog grounds(see the Configuration Registersection). After applyingand DGND should be connected to this ground.

power, allow a 1.0ms wake-up time to elapse before ini-tiating the first conversion. Then, hold CONVST high forat least 2.0μs after the wake-up time is complete. Ifusing an external clock, apply 20 clock pulses to CLKwith CONVST high before initiating the first conversion.

SUPPLIESReference

+5VRETURN+3V TO +5VRETURNInternal Reference

The internal-reference circuits provide for analog inputOPTIONALvoltages of 0 to +5V unipolar (MAX1316/MAX1317/FERRITEMAX1318), ±5V bipolar (MAX1320/MAX1321/MAX1322),BEADor ±10V bipolar (MAX1324/MAX1325/MAX1326). Installexternal capacitors for reference stability, as indicated inTable 4, and as shown in the Typical Operating Circuits.External Reference

Connect a +2.0V to +3.0V external reference at REFAVDDAGNDDVDDDGNDVDDGNDand/or REF. When connecting an external reference, theMSinput impedance is typically 5k?. The external referenceMAX1316–MAX1318DIGITALmust be able to drive 200μA of current and have a lowMAX1320–MAX1322CIRCUITRYoutput impedance. For more information about usingMAX1324–MAX1326external references see the Transfer Functionssection.

Figure 8. Power-Supply Grounding and BypassingTable 4. Reference Bypass CapacitorsLOCATIONINPUT VOLTAGE RANGEUNIPOLAR (μF)BIPOLAR (μF)MSV bypass capacitor to AGND2.2 || 0.1NAREFMS bypass capacitor to AGND0.010.01 (connect REFMS to REF)REF bypass capacitor to AGND0.010.01 (connect REFMS to REF)REF+ bypass capacitor to AGND0.10.1REF+ to REF- capacitor2.2 || 0.12.2 || 0.1REF- bypass capacitor to AGND0.10.1COM bypass capacitor to AGND2.2 || 0.12.2 || 0.1NA = Not applicable (connect MSV directly to AGND).______________________________________________________________________________________19

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326No other digital system ground should be connected tothis single-point analog ground. The ground return tothe power supply for this ground should be low imped-ance and as short as possible for noise-free operation.High-frequency noise in the VDDpower supply mayaffect the high-speed comparator in the ADC. Bypassthese supplies to the single-point analog ground with0.1μF and 2.2μF bypass capacitors close to the device.If the +5V power supply is very noisy, a ferrite bead canbe connected as a lowpass filter, as shown in Figure 8.

The input range is centered about VMSV. Normally,MSV = AGND, and the input is symmetrical about zero.For a custom midscale voltage, drive MSV with anexternal voltage source. Noise present on MSV directlycouples into the ADC result. Use a precision, low-driftvoltage reference with adequate bypassing to preventMSV from degrading ADC performance. For maximumFSR, be careful not to violate the absolute maximumvoltage ratings of the analog inputs when choosingVMSV.

Determine the input voltage as a function of VREF,VMSV, and the output code in decimal using the follow-ing equation:

VCH_ = LSB × CODE10 + VMSV

Bipolar ±5V Devices

Table 6 and Figure 10 show the two’s complementtransfer function for the MAX1320/MAX1321/MAX1322with a ±5V input range. The FSR is four times the volt-age at REF. The internal +2.500V reference gives a+10V FSR, while an external +2V to +3V referenceallows an FSR of +8V to +12V, respectively. Calculatethe LSB size using the following equation:

LSB = 4 × VREF214Transfer Functions

Bipolar ±10V Devices

Table 5 and Figure 9 show the two’s complement trans-fer function for the MAX1324/MAX1325/MAX1326 with a±10V input range. The full-scale input range (FSR) iseight times the voltage at REF. The internal +2.500V ref-erence gives a +20V FSR, while an external +2V to +3Vreference allows an FSR of +16V to +24V, respectively.Calculate the LSB size using the following equation:

LSB = 8 × VREF214This equals 1.2207mV with a +2.5V internal reference.

This equals 0.6104mV when using the internal reference.

Table 5. ±10V Bipolar Code TableTWO’S COMPLEMENTBINARY OUTPUT CODE01 1111 1111 11110x1FFF01 1111 1111 11100x1FFE00 0000 0000 00010x000100 0000 0000 00000x000011 1111 1111 11110x3FFF10 0000 0000 00010x200110 0000 0000 00000x2000DECIMALEQUIVALENTOUTPUT(CODE10)8191819010-1-8191-8192INPUTVOLTAGE (V)(VREF = 2.5V,VMSV = 0V)9.9994±0.5 LSB9.9982±0.5 LSB0.0018±0.5 LSB0.0006±0.5 LSB-0.0006±0.5 LSB-9.9982±0.5 LSB-9.9994±0.5 LSB8 x VREF0x1FFF0x1FFE0x1FFD0x1FFCTWO'S COMPLEMENT BINARY OUTPUT CODE0x00010x00000x3FFF8 x VREF0x20030x20020x20010x2000-8192-8190-10+1(MSV)1 LSB =8 x VREF214+8189+8191INPUT VOLTAGE (VCH_ - VMSV IN LSBs)Figure 9. ±10V Bipolar Transfer Function

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326Pin ConfigurationsTOP VIEWCLKCONVSTCSALLONSHDNCLKCONVSTCSWRRDEOLCEOCDGNDDVDDD134847464544434241403938ALLONSHDNDGND39EOLCEOC4140484746454443423837DVDDD13WRRDAVDDAGNDAGNDCH0CH1MSVCH2CH3CH4CH5CH6CH7123456789101112131415161718192021222324363534333231302928272625D12D11D10D9D8D7D6D5D4D3D2D1AVDDAGNDAGNDCH0CH1MSVCH2CH3I.C.I.C.I.C.I.C.37123456789101112131415161718192021222324363534333231302928272625D12D11D10D9D8D7D6D5D4D3D2D1MAX1316MAX1320MAX1324MAX1317MAX1321MAX1325INTCLK/EXTCLKAGND8-CHANNEL TQFPCLKCONVSTALLONSHDN4847464544434241403938AVDDAGNDAGNDCH0CH1MSVI.C.I.C.I.C.I.C.I.C.I.C.37DGNDDVDDD13EOLCEOCCSWRRD123456789101112131415161718192021222324MAX1318MAX1322MAX1326INTCLK/EXTCLKAGNDAVDD2-CHANNEL TQFP26______________________________________________________________________________________

REFMSAGNDAVDDREFREF+COMREF-AGNDD0INTCLK/EXTCLKAGNDAVDDAGNDAVDDREFMSREFREF+COMREF-AGNDD0REFREF+COMREF-AGNDAVDDAGNDAVDDREFMSD04-CHANNEL TQFP363534333231302928272625D12D11D10D9D8D7D6D5D4D3D2D1元器件交易网www.cecb2b.com

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input Ranges

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline informationgo to www.maxim-ic.com/packages.)

SPE.PFQT,L84/L23PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm 21-0054E12PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm 21-0054E22Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________27?2004 Maxim Integrated Products

Printed USA

is a registered trademark of Maxim Integrated Products.

MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input Ranges

Table 6. ±5V Bipolar Code Table4 x VREF0x1FFFDECIMALINPUT0x1FFETWO’S COMPLEMENTEQUIVALENTVOLTAGE (V)EDO0x1FFDBINARY OUTPUT CODEOUTPUT(VREF = 2.5V,C TU0x1FFC(CODE10)VMSV = 0V)PTUO 01 1111 1111 11114.9997RYAN0x00010x1FFF8191±0.5 LSBIB T0x00004 x VREFNEM0x3FFF01 1111 1111 1110E0x1FFE81904.9991±0.5 LSBLPMOC00 0000 0000 0001 S'O0x000110.0009±0.5 LSBW0x2003T0x20020x20011 LSB =4 x VREF00 0000 0000 000000.0003±0.5 LSB0x20002140x000011 1111 1111 1111-8192-8190-10+1+8189+81910x3FFF-1-0.0003±0.5 LSB(MSV)INPUT VOLTAGE (VCH_ - VMSV IN LSBs)10 0000 0000 00010x2001-8191-4.9991±0.5 LSBFigure 10. ±5V Bipolar Transfer Function

10 0000 0000 00000x2000-8192-4.9997±0.5 LSBThe input range is centered about VMSV = AGND, and the input is symmetrical about zero.MSV. Normally,For a custom midscale voltage, drive MSV with anTable 7. 0 to +5V Unipolar Code Tableexternal voltage source. Noise present on MSV directlycouples into the ADC result. Use a precision, low-driftDECIMALINPUTvoltage reference with adequate bypassing to preventBINARY OUTPUT CODEEQUIVALENTVOLTAGE (V)MSV from degrading ADC performance. For maximumOUTPUT(VREF = VREFMSFSR, be careful not to violate the absolute maximum(CODE10)= 2.5V)voltage ratings of the analog inputs when choosing11 1111 1111 1111V0x3FFF163834.9998±0.5 LSBVMSV. Determine the input voltage as a function ofREF, VMSV, and the output code in decimal using thefollowing equation:

11 1111 1111 1110163824.99950x3FFE±0.5 LSB VCH_ = LSB × CODE10 + VMSV

10 0000 0000 000181932.50050x2001±0.5 LSBUnipolar 0 to +5V Devices

10 0000 0000 0000Table 7 and Figure 11 show the offset binary transfer81922.50020x2000±0.5 LSBfunction for the MAX1316/MAX1317/MAX1318 with a 0to +5V input range. The FSR is two times the voltage at01 1111 1111 111181912.4998REF. The internal +2.500V reference gives a +5V FSR,0x1FFF±0.5 LSBwhile an external +2V to +3V reference allows an FSR00 0000 0000 0001of +4V to +6V, respectively. Calculate the LSB size10.00050x0001±0.5 LSBusing the following equation:

00 0000 0000 000000.00020x0000±0.5 LSBLSB = 2 × VREF 214This equals 0.3052mV when using the internal reference.

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326Differential Nonlinearity

2 x VREF0x3FFF0x3FFE0x3FFD0x3FFCBINARY OUTPUT CODEDifferential nonlinearity (DNL) is the difference betweenan actual step width and the ideal value of 1 LSB. Forthese devices, the DNL of each digital output code ismeasured and the worst-case value is reported in theElectrical Characteristicstable. A DNL error specifica-tion of less than ±1 LSB guarantees no missing codesand a monotonic transfer function.

2 x VREF0x20010x20000x1FFFUnipolar Offset Error

For the unipolar MAX1316/MAX1317/MAX1318, the idealzero-scale transition from 0x0000 to 0x0001 occurs at 1 LSB (see Figure 11). The unipolar offset error is theamount of deviation between the measured zero-scaletransition point and the ideal zero-scale transition point.

0x00030x00020x00010x000002819281908194(MSV)1 LSB =2 x VREF214Bipolar Offset Error

For the bipolar MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326, the ideal zero-point tran-sition from 0x3FFF to 0x0000 occurs at MSV, which isusually connected to ground (see Figures 9 and 10).The bipolar offset error is the amount of deviationbetween the measured zero-point transition and theideal zero-point transition.

16,38116,383INPUT VOLTAGE (LSBs)Figure 11. 0 to +5V Unipolar Transfer Function

Gain Error

The ideal full-scale transition from 0x1FFE to 0x1FFFoccurs at 1 LSB below full scale (see the TransferFunctionssection). The gain error is the amount of devi-ation between the measured full-scale transition pointand the ideal full-scale transition point, once offset errorhas been nullified.

The input range is centered about VMSV, which is inter-nally set to +2.500V. For a custom midscale voltage,drive REFMSwith an external voltage source and MSVwill follow REFMS. Noise present on MSV or REFMSdirectly couples into the ADC result. Use a precision,low-drift voltage reference with adequate bypassing toprevent MSV from degrading ADC performance. Formaximum FSR, be careful not to violate the absolutemaximum voltage ratings of the analog inputs whenchoosing VMSV. Determine the input voltage as a func-tion of VREF, VMSV, and the output code in decimalusing the following equation:

V = LSB × CODE10+ (VMSV - 2.500V) CH_

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital

samples, signal-to-noise ratio (SNR) is the ratio of thefull-scale analog input (RMS value) to the RMS quanti-zation error (residual error). The ideal, theoretical mini-mum analog-to-digital noise is caused by quantizationnoise error only and results directly from the ADC’s res-olution (N bits):

× N + 1.76)dB

SNR=(6.02

where N = 14 bits.

In reality, there are other noise sources besides quanti-zation noise: thermal noise, reference noise, clock jitter,etc. SNR is computed by taking the ratio of the RMSsignal to the RMS noise, which includes all spectralcomponents minus the fundamental, the first five har-monics, and the DC offset.

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the valueson an actual transfer function from a straight line. Forthese devices, this straight line is a line drawn betweenthe end points of the transfer function, once offset andgain errors have been nullified.

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input Ranges

Signal-to-Noise Plus Distortion

Aperture Delay

Signal-to-noise plus distortion (SINAD) is the ratio of theAperture delay (tfundamental input frequency’s RMS amplitude to theclock edge to the instant when an actual sample is taken.

AD) is the time delay from the sampling

RMS equivalent of all the other ADC output signals:Aperture Jitter

SINAD(dB)=20×log?Aperture Jitter (t?SignalRMS?AJ) is the sample-to-sample variation inaperture delay.

?(Noise+Distortion)RMS??Channel-to-Channel Isolation

Effective Number of Bits

Channel-to-channel isolation indicates how well eachThe effective number of bits (ENOB) indicates the globalanalog input is isolated from the other channels. Channel-accuracy of an ADC at a specific input frequency andto-channel isolation is measured by applying DC to chan-sampling rate. An ideal ADC’s error consists of quanti-nels 1 to 7, while a -0.5dBFS sine wave is applied tozation noise only. With an input range equal to the full-channel 0. A 100kHz FFT is taken for channel 0 andscale range of the ADC, calculate the ENOB as follows:

channel 1. Channel-to-channel isolation is expressed indB as the power ratio of the two 100kHz magnitudes.

SINAD-1.76Small-Signal Bandwidth

ENOB=6.02A small -20dBFS analog input signal is applied to anADC in a manner that ensures that the signal’s slewTotal Harmonic Distortion

rate does not limit the ADC’s performance. The inputTotal harmonic distortion (THD) is the ratio of the RMSfrequency is then swept up to the point where thesum of the first five harmonics of the input signal to theamplitude of the digitized conversion result hasfundamental itself. This is expressed as:

decreased 3dB.

?Full-Power Bandwidth

THD=20×log?V22+V32+V42+V52??A large -0.5dBFS analog input signal is applied to an?ADC, and the input frequency is swept up to the point ??V1???where the amplitude of the digitized conversion resulthas decreased by 3dB. This point is defined as full-where V1is the fundamental amplitude and V2 through

power input bandwidth frequency.

V5are the 2nd- through 5th-order harmonics.

Spurious-Free Dynamic Range

Chip InformationSpurious-free dynamic range (SFDR) is the ratio of theRMS amplitude of the fundamental (maximum signalTRANSISTOR COUNT: 80,000component) to the RMS value of the next-largest fre-PROCESS: BiCMOS 0.6μm

quency component.

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MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326元器件交易网www.cecb2b.com

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326Typical Operating Circuits13+5V0.1μF0.1μF0.1μF11517AVDDAVDDAVDDINTCLK/EXTCLKDVDD38+3V0.1μFMAX1316MAX1317MAX1318DGND39GNDCSRD444243454748464041DIGITALINTERFACEANDCONTROL2.2μF0.1μFUNIPOLARCONFIGURATION6MSVWRCONVSTSHDNREFMSREFALLONCLKEOC0.01μF0.01μF18190.1μF20REF+EOLC2.2μF0.1μF22REF-D13D122.2μFD1121COMD10D9AGNDCH7CH6CH5CH4CH3CH2CH1CH0D8D7D6D5D4D3D2D1D03736353433323130292827262524PARALLELDIGITALI/OPARALLELDIGITALOUTPUT0.1μF0.1μFGNDANALOGINPUTS0 TO +5V2, 3, 14, 16, 23121110MAX1316987MAX1317MAX13185424______________________________________________________________________________________

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8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCswith ±10V, ±5V, and 0 to +5V Analog Input Ranges

Typical Operating Circuits (continued)13INTCLK/EXTCLKDVDD38+3V+5V0.1μF0.1μF1MAX1320AV39DDGND0.1μFMAX1321DGND15MAX1322AVDD440.1μFMAX1324CS17AVMAX1325DDMAX1326RD42WR436MSVCONVST45BIPOLARDIGITAL47CONFIGURATION0.01μF18REFMSSHDNINTERFACEAND1948REFALLONCONTROLCLK460.1μF20EOC40REF+EOLC412.2μF0.1μF2237REF-D130.1μFD12362.2μFD1135PARALLEL21DIGITAL0.1μFCOMD1034OUTPUTD933GND2, 3, 14, 16, 23AGNDD832BIPOLAR12CH7D731ANALOGINPUTS11CH6D63010CH5D529MAX1322MAX13249CH4D428PARALLEL8CH3D327DIGITALI/OMAX13207CH2D226MAX13255CH1D125MAX1321MAX13264CH0D024______________________________________________________________________________________25

MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326

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