M25PE16-VMW6TG中文资料

April 2007 Rev 41/56

M25PE16

16 Mbit, low-voltage, Page-Erasable Serial Flash memory with

byte-alterability, 50 MHz SPI bus, standard pinout

Features

■

SPI bus compatible Serial interface ■

16-Mbit Page-Erasable Flash memory ■Page size: 256 bytes

–Page Write in 11ms (typical)

–Page Program in 0.8ms (typical)

–Page Erase in 10ms (typical)

■SubSector Erase (4 Kbytes)

■Sector Erase (64 Kbytes)

■Bulk Erase (16 Mbits)

■ 2.7 V to 3.6V single supply voltage

■50MHz clock rate (maximum)

■Deep Power-down mode 1μA (typical)

■Electronic Signature

–JEDEC standard two-byte signature

(8015h)

■Software Write Protection on a 64 KByte

Sector basis

■Hardware Write Protection of the memory area

selected using the BP0, BP1 and BP2 bits

■More than 100 000 Write cycles

■More than 20 year data retention

■

Packages

–ECOPACK? (RoHS compliant)

a1ae8b4aa8956bec0975e365 元器件交易网a1ae8b4aa8956bec0975e365

元器件交易网a1ae8b4aa8956bec0975e365

Contents M25PE16

Contents

1Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.5Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.6Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.7V CC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.8V SS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13

4.5Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.6Active Power, Standby Power and Deep Power-Down modes . . . . . . . . . 13

4.7Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.8Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.8.1Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.8.2Specific Hardware and Software protections . . . . . . . . . . . . . . . . . . . . . 15

5Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.2Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.3Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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M25PE16Contents

6.4Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4.1WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4.2WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4.3BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4.4SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.5Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.6Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.7Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 30

6.8Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.9Page Write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.10Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.11Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.12Page Erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.13Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.14SubSector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.15Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.16Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.17Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

11DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

12Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

13Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

14Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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List of tables M25PE16

List of tables

Table 1.Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2.Software protection truth table (Sectors 0 to 31, 64 Kbyte granularity) . . . . . . . . . . . . . . . 15

Table 3.Protected area sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4.Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5.Instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 6.Read Identification (RDID) data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 7.Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 8.Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 9.Lock Register out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 10.Lock Register in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 11.Power-Up timing and VWI threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 12.Device status after a RESET Low pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 13.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 14.Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 15.AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 16.Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 17.DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 18.AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 19.Reset conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 20.Timings after a RESET Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 21.VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,

6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 22.SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, mechanical data. . . . . . . . 53

Table 23.Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 24.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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M25PE16List of figures

List of figures

Figure 1.Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2.VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.Bus Master and memory devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4.SPI modes supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6.Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 7.Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 8.Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 24

Figure 9.Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 26

Figure 10.Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 11.Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 29

Figure 12.Read Data Bytes at Higher Speed (FAST_READ) instruction sequence

and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 13.Read Lock Register (RDLR) instruction sequence

and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 14.Page Write (PW) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 15.Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 16.Write to Lock Register (WRLR) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 17.Page Erase (PE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 18.Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 19.SubSector Erase (SSE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 20.Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 21.Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 22.Release from Deep Power-down (RDP) instruction sequence. . . . . . . . . . . . . . . . . . . . . . 42

Figure 23.Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 24.AC measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 25.Serial input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 26.Write Protect setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 27.Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 28.Reset AC waveforms while a program or erase cycle is in progress . . . . . . . . . . . . . . . . . 51

Figure 29.VFQFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 6 × 5mm,

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 30.SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package outline . . . . . . . . 53

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Description M25PE16

1 Description

The M25PE16 is a 16 Mbit (2Mb × 8) Serial Paged Flash memory accessed by a high

speed SPI-compatible bus.

The memory can be written or programmed 1 to 256 Bytes at a time, using the Page Write

or Page Program instruction. The Page Write instruction consists of an integrated Page

Erase cycle followed by a Page Program cycle.

The memory is organized as 32 sectors that are further pided up into 16 subsectors each

(512 subsectors in total). Each sector contains 256 pages and each subsector contains 16

pages. Each page is 256 Bytes wide. Thus, the whole memory can be viewed as consisting

of 8192 pages, or 2,097,152 Bytes.

The memory can be erased a page at a time, using the Page Erase instruction, a subsector

at a time, using the SubSector Erase instruction, a sector at a time, using the Sector Erase

instruction, or as a whole, using the Bulk Erase instruction.

The memory can be Write Protected by either Hardware or Software using mixed volatile

and non-volatile protection features, depending on the application needs. The protection

granularity is of 64 Kbytes (sector granularity).

In order to meet environmental requirements, ST offers these devices in ECOPACK?

packages.

ECOPACK? packages are Lead-free and RoHS compliant.

ECOPACK is an ST trademark. ECOPACK specifications are available at: a1ae8b4aa8956bec0975e365.

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M25PE16

Description

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1.There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally, to V SS ,

and must not be allowed to be connected to any other voltage or signal line on the PCB.2.See Section 12: Package mechanical for package dimensions, and how to identify pin-1.

Table 1.

Signal names

C Serial Clock

D Serial Data Input Q Serial Data Output S Chip Select W Write Protect RESET Reset

V CC Supply Voltage V SS

Ground

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Signal description M25PE168/56 2 Signal description

2.1 Serial Data Output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (C).

2.2 Serial Data Input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be programmed. Values are latched on the rising edge of Serial

Clock (C).

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4 When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the

device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low selects the device, placing it in the Active Power mode.

After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.

output is high impedance.

operation (write, program or erase cycle) and data may be lost.

See Table 122.6 The Write Protect (W) input is used to freeze the size of the area of memory that is

protected against write, program and erase instructions (as specified by the values in the

BP2, BP1 and BP0 bits of the Status Register). See Section 6.4: Read Status Register

(RDSR).

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M25PE16Signal description

2.7 V CC supply voltage

V CC is the supply voltage.

2.8 V SS ground

V SS is the reference for the V CC supply voltage.

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SPI modes M25PE16

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3 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of

the two following modes:

●CPOL=0, CPHA=0●

CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Stand-by mode and not transferring data:

● C remains at 0 for (CPOL=0, CPHA=0)●

C remains at 1 for (CPOL=1, CPHA=1)

1.The Write Protect (W) and Reset (RESET) signals should be driven, High or Low as appropriate.

Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, the other devices are high impedance.

The pull-up resistor R (represented in Figure 4) ensures that no device is selected if the Bus In applications where the Bus Master might enter a state where all inputs/outputs SPI lines are in high impedance at the same time (for example, if the Bus Master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pull-down resistor so that, if all inputs/outputs become high impedance, the C line is pulled Low time, and so, that the t SHCH requirement is met.

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M25PE16SPI modes The typical value of R is 100 k?, assuming that the time constant R*C p (C p = parasitic

capacitance of the bus line) is short enough, as the S and C lines must reach the correct

state (S = High and C = Low) while the SPI bus is in high impedance.

Example: C p = 50 pF, that is R*C p = 5 μs <=> the application must ensure that the Bus

Master never leaves the SPI bus in the high impedance state for a time period shorter than

5μs.

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Operating features M25PE1612/56 4 Operating features

4.1 Sharing the overhead of modifying data

To write or program one (or more) data Bytes, two instructions are required: Write Enable

(WREN), which is one Byte, and a Page Write (PW) or Page Program (PP) sequence, which

consists of four Bytes plus data. This is followed by the internal cycle (of duration t PW or t PP ).

To share this overhead, the Page Write (PW) or Page Program (PP) instruction allows up to

256 Bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1)

at a time, provided that they lie in consecutive addresses on the same page of memory.

4.2 An easy way to modify data

The Page Write (PW) instruction provides a convenient way of modifying data (up to 256 contiguous Bytes at a time), and simply requires the start address, and the new data in the

instruction sequence.The Page Write (PW) instruction is entered by driving Chip Select (S) Low, and then transmitting the instruction Byte, three address Bytes (A23-A0) and at least one data Byte, and then driving Chip Select (S) High. While Chip Select (S) is being held Low, the data

Bytes are written to the data buffer, starting at the address given in the third address Byte

(A7-A0). When Chip Select (S) is driven High, the Write cycle starts. The remaining,

unchanged, Bytes of the data buffer are automatically loaded with the values of the

corresponding Bytes of the addressed memory page. The addressed memory page then

automatically put into an Erase cycle. Finally, the addressed memory page is programmed

with the contents of the data buffer.

All of this buffer management is handled internally, and is transparent to the user. The user

is given the facility of being able to alter the contents of the memory on a Byte-by-Byte basis.

For optimized timings, it is recommended to use the Page Write (PW) instruction to write all

consecutive targeted Bytes in a single sequence versus using several Page Write (PW)

sequences with each containing only a few Bytes (see Section 6.9: Page Write (PW) and

Table 18: AC characteristics ).

元器件交易网a1ae8b4aa8956bec0975e365

元器件交易网a1ae8b4aa8956bec0975e365

M25PE16Operating features

4.3 A fast way to modify data

The Page Program (PP) instruction provides a fast way of modifying data (up to 256

contiguous Bytes at a time), provided that it only involves resetting bits to 0 that had

previously been set to 1.

This might be:

●when the designer is programming the device for the first time

●when the designer knows that the page has already been erased by an earlier Page

Erase (PE), SubSector Erase (SSE), Sector Erase (SE) or Bulk Erase (BE) instruction.

This is useful, for example, when storing a fast stream of data, having first performed

the erase cycle when time was available

●when the designer knows that the only changes involve resetting bits to 0 that are still

set to 1. When this method is possible, it has the additional advantage of minimizing the

number of unnecessary erase operations, and the extra stress incurred by each page.

For optimized timings, it is recommended to use the Page Program (PP) instruction to

program all consecutive targeted Bytes in a single sequence versus using several Page

Program (PP) sequences with each containing only a few Bytes (see Section6.10: Page

Program (PP) and Table18: AC characteristics).

4.4 Polling during a Write, Program or Erase cycle

A further improvement in the time to write (PW, WRSR), program (PP) or erase (SE, SSE or

BE) can be achieved by not waiting for the worst case delay (t W, t PW, t PP, t PE, t SE, t SSE or

t BE). The Write In Progress (WIP) bit is provided in the Status Register so that the

application program can monitor its value, polling it to establish when the previous cycle is

complete.

4.5 Reset

An internal Power-On Reset circuit helps protect against inadvertent data writes. Addition

protection is provided by driving Reset (RESET) Low during the Power-on process, and only

driving it High when V CC has reached the correct voltage level, V CC(min).

4.6 Active Power, Standby Power and Deep Power-Down modes

mode until all internal cycles have completed (Program, Erase, Write). The device then goes

in to the Standby Power mode. The device consumption drops to I CC1.

The Deep Power-down mode is entered when the specific instruction (the Deep Power-

down (DP) instruction) is executed. The device consumption drops further to I CC2. When in

this mode, only the Release from Deep Power-down instruction is accepted. All other

instructions are ignored. The device remains in the Deep Power-down mode until the

Release from Deep Power-down instruction is executed. This can be used as an extra

software protection mechanism, when the device is not in active use, to protect the device

from inadvertent Write, Program or Erase instructions.

13/56

Operating features M25PE1614/56 4.7 Status Register

The Status Register contains a number of status and control bits that can be read or set (as

appropriate) by using specific instructions. See Section 6.4: Read Status Register (RDSR)

for a detailed description of the Status Register bits.

4.8 Protection modes

The environments where non-volatile memory devices are used can be very noisy. No SPI

device can operate correctly in the presence of excessive noise. T o help combat this and to

meet the needs of modularized applications, the M25PE16 features the following flexible

data protection mechanisms:

4.8.1 Protocol-related protections

●

Power On Reset and an internal timer (t PUW ) can provide protection against inadvertent changes while the power supply is outside the operating specification.●

Program, Erase and Write instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.●All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state

by the following events:

–Power-up –

–

Write Disable (WRDI) instruction completion –

Page Write (PW) instruction completion –

Write Status Register (WRSR) instruction completion –

Page Program (PP) instruction completion –

Write to Lock Register (WRLR) instruction completion –

Page Erase (PE) instruction completion –

SubSector Erase (SSE) instruction completion –

Sector Erase (SE) instruction completion –Bulk Erase (BE) instruction completion

●the specific cases of Program and Write cycles, the designer should refer to

Section 6.5: Write Status Register (WRSR), Section 6.9: Page Write (PW),

Section 6.10: Page Program (PP), Section 6.12: Page Erase (PE), Section 6.13: Sector

Erase (SE) and Section 6.14: SubSector Erase (SSE), and to Table 12: Device status

after a RESET Low pulse .

●

In addition to the low power consumption feature, the Deep Power-down mode offers

extra software protection from inadvertent Write, Program and Erase instructions while

the device is not in active use.元器件交易网a1ae8b4aa8956bec0975e365

M25PE16Operating features

15/564.8.2 Specific Hardware and Software protections

There are two Software Protected modes, SPM1 and SPM2, that can be combined to

protect the memory array as required. The SPM2 can be Hardware protected with the help SPM1 and SPM2

●The first Software Protected mode (SPM1) is managed by specific Lock Registers

assigned to each 64 Kbyte sector.

The Lock Registers can be read and written using the Read Lock Register (RDLR) and

Write to Lock Register (WRLR) instructions.

In each Lock Register two bits control the protection of each sector: the Write Lock Bit

and the Lock Down Bit.

–Write Lock Bit:

The Write Lock Bit determines whether the contents of the sector can be modified

(using the Write, Program or Erase instructions). When the Write Lock Bit is set,

‘1’, the sector is write protected – any operations that attempt to change the data

in the sector will fail. When the Write Lock Bit is reset to ‘0’, the sector is not write

protected by the Lock Register, and may be modified.

–Lock Down Bit:

The Lock Down Bit provides a mechanism for protecting software data from simple

hacking and malicious attack. When the Lock Down Bit is set, ‘1’, further

modification to the Write Lock and Lock Down Bits cannot be performed. A reset,

or power-up, is required before changes to these bits can be made. When the

Lock Down Bit is reset, ‘0’, the Write Lock and Lock Down Bits can be changed.

The Write Lock Bit and the Lock Down Bit are volatile and their value is reset to ‘0’ after

a Power-Down or a Reset (see Table 12: Device status after a RESET Low pulse ).

The definition of the Lock Register bits is given in Table 9: Lock Register out .

Table 2.Software protection truth table (Sectors 0 to 31, 64 Kbyte granularity)

Sector Lock

Register

Protection Status

Lock

Down Bit

Write Lock Bit 0

0Sector Unprotected from Program/Erase/Write operations, Protection Status Reversible 0

1Sector Protected from Program/Erase/Write operations, Protection Status Reversible 1

0Sector Unprotected from Program/Erase/Write operations, Sector Protection Status cannot be changed except by a Reset or Power-up.11Sector Protected from Program/Erase/Write operations,

Sector Protection Status cannot be changed except by a Reset or Power-up.

元器件交易网a1ae8b4aa8956bec0975e365

Operating features M25PE16

16/56●The second Software Protected mode (SPM2) uses the Block Protect (BP2, BP1,

BP0, see Section6.4.3)) bits to allow part of the memory to be configured as read-only. Table 3.Protected area sizes

Status Register

Content

Memory content

BP2

Bit

BP1

Bit

BP0

Bit

Protected Area Unprotected Area

0 0 0 none All

sectors(1) (32 sectors: 0 to 31)

1.The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are

0.

0 0 1 Upper 32nd (Sector 31)Lower 31st/32nd (31 sectors: 0 to 30)

0 1 0

Upper sixteenth (two sectors: 30 and

31)

Lower 15/16ths (30 sectors: 0 to 29)

0 1 1 Upper eighth (four sectors: 28 to 31)Lower seven-eighths (28 sectors: 0 to 27)

1 0 0

Upper quarter (eight sectors: 24 to

31)

Lower three-quarters (24 sectors: 0 to 23)

1 0 1 Upper half (sixteen sectors: 16 to 31)Lower half (16 sectors: 0 to 15)

1 1 0 All sectors (3

2 sectors: 0 to 31)none

1 1 1 All sectors (3

2 sectors: 0 to 31)none

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M25PE16Memory organization

17/56

5 Memory organization

The memory is organized as:

●8192 pages (256 Bytes each).●2,097,152 Bytes (8 bits each)

●32 sectors (512 Kbits, 65536 Bytes each)●

512 subsectors (32 Kbits, 4096 Bytes each)Each page can be inpidually:

●programmed (bits are programmed from 1 to 0)●erased (bits are erased from 0 to 1)●

written (bits are changed to either 0 or 1)

The device is Page, Sector or Bulk Erasable (bits are erased from 0 to 1).

Table 4.

Memory organization

Sector Subsector

Address Range Sector Subsector

Address Range 31

511

1FF000h 1FFFFFh

23

38317F000h 17FFFFh ...

...............

4961F0000h 1F0FFFh 368170000h 170FFFh 30

495

1EF000h 1EFFFFh

22

36716F000h 16FFFFh ...

...............4801E0000h 1E0FFFh 352160000h 160FFFh 29

479

1DF000h 1DFFFFh

21

35115F000h 15FFFFh ..................4641D0000h 1D0FFFh 336150000h 150FFFh 28

463

1CF000h 1CFFFFh

20

33514F000h 14FFFFh ..................4481C0000h 1C0FFFh 320140000h 140FFFh 27

447

1BF000h 1BFFFFh

19

31913F000h 13FFFFh ..................4321B0000h 1B0FFFh 304130000h 130FFFh 26

431

1AF000h 1AFFFFh

18

30312F000h 12FFFFh ..................4161A0000h 1A0FFFh 288120000h 120FFFh 25

415

19F000h 19FFFFh

17

28711F000h 11FFFFh ..................400190000h 190FFFh 272110000h 110FFFh 24

399

18F000h 18FFFFh

16

27110F000h 10FFFFh ..................384180000h

180FFFh

256

100000h

100FFFh 元器件交易网a1ae8b4aa8956bec0975e365

Memory organization M25PE16

18/56

15

255FF000h FFFFFh

6

1116F000h6FFFFh .

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

240F0000h F0FFFh9660000h60FFFh

14

239EF000h EFFFFh

5

955F000h5FFFFh .

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

224E0000h E0FFFh8050000h50FFFh

13

223DF000h DFFFFh

4

794F000h4FFFFh .

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

208D0000h D0FFFh6440000h40FFFh

12

207CF000h CFFFFh

3

633F000h3FFFFh .

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

192C0000h C0FFFh4830000h30FFFh

11

191BF000h BFFFFh

2

472F000h2FFFFh .

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

176B0000h B0FFFh3220000h20FFFh

10

175AF000h AFFFFh

1

311F000h1FFFFh

.

.

.

.

.

.

.

.

.

160A0000h A0FFFh1610000h10FFFh

9

1599F000h9FFFFh

150F000h0FFFFh .

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

14490000h90FFFh404000h04FFFh

8

1438F000h8FFFFh303000h03FFFh

.

.

.

.

.

.

.

.

.202000h02FFFh 12880000h80FFFh101000h01FFFh

7

1277F000h7FFFFh000000h00FFFh

.

.

.

.

.

.

.

.

.

11270000h70FFFh

Table 4.Memory organization (continued)

Sector Subsector Address Range Sector Subsector Address Range

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元器件交易网a1ae8b4aa8956bec0975e365

M25PE16Memory organization

19/56

元器件交易网a1ae8b4aa8956bec0975e365

Instructions M25PE16

6 Instructions

All instructions, addresses and data are shifted in and out of the device, most significant bit

first.

Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select

(S) is driven Low. Then, the one-Byte instruction code must be shifted in to the device, most

significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of

Serial Clock (C).

The instruction set is listed in Table5.

Every instruction sequence starts with a one-Byte instruction code. Depending on the

instruction, this might be followed by address Bytes, or by data Bytes, or by both or none.

In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),

Read Identification (RDID), Read Status Register (RDSR), or Read Lock Register (RDLR)

instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip

Select (S) can be driven High after any bit of the data-out sequence is being shifted out.

In the case of a Page Write (PW), Page Program (PP), Write to Lock Register (WRLR),

Page Erase (PE), Sector Erase (SE), SubSector Erase (SSE), Bulk Erase (BE), Write

Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI), Deep Power-down

(DP) or Release from Deep Power-down (RDP) instruction, Chip Select (S) must be driven

High exactly at a Byte boundary, otherwise the instruction is rejected, and is not executed.

That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select

(S) being driven Low is an exact multiple of eight.

All attempts to access the memory array during a Write cycle, Program cycle or Erase cycle

are ignored, and the internal Write cycle, Program cycle or Erase cycle continues

unaffected.

20/56

M25PE16

Instructions

21/56

Table 5.

Instruction set

Instruction Description

One-Byte Instruction Code Address

Bytes Dummy

Bytes

Data Bytes WREN Write Enable 0000 011006h 0 0 0 WRDI Write Disable 0000 010004h 0 0 0 RDID Read Identification 1001 11119Fh 0 0 1 to 3RDSR Read Status Register 0000 010105h 0 0 1 to ∞WRSR Write Status Register 0000 000101h 0 0 1 WRLR Write to Lock Register 1110 0101E5h 301RDLR Read Lock Register 1110 1000E8h 301READ Read Data Bytes 0000 001103h 30 1 to ∞FAST_READ

Read Data Bytes at Higher Speed 0000 10110Bh 31 1 to ∞PW Page Write 0000 10100Ah 30 1 to 256PP Page Program 0000 001002h 30 1 to 256

PE Page Erase 1101 1011DBh 3 0 0 SE Sector Erase 1101 1000D8h 3 0 0 SSE SubSector Erase 0010 000020h 3 0 0 BE Bulk Erase 1100 0111C7h 000DP Deep Power-down 1011 1001B9h 0 0 0 RDP

Release from Deep Power-down

1010 1011

ABh

元器件交易网a1ae8b4aa8956bec0975e365

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