用VHDL语言设计555压控振荡器测频率 - 图文

实验五利用压控振荡器测量电压

一、实验目的

（1）以555定时器为基础设计压控振荡器 （2）设计一个具有如下功能的简易频率计。

1. 可以测量压控振荡器产生的频率，用4位数码管显示 2.测量结果直接用十进制数值显示

3. 被测信号是压控振荡器产生的方波脉冲信号，根据设计的压控振荡器确定电压值 4. 具有超量程警告（可以用 LED 灯显示） 二、实验设备与器材

（1）计算机：Quartus Ⅱ 16.0软件；

（2）硬件：Cyclone DE0-CV FPGA开发平台、555定时器、电阻、电容、可变电阻 三、利用Multisim搭建仿真电路

四、实验程序 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -- 计数器

entity cnt10 is

port (rst,fx,ena:in std_logic; cout: out std_logic;

outy :out std_logic_vector(3 downto 0)); end cnt10;

architecture behv of cnt10 is begin

process (rst,ena,fx) -- 定义变量

-- <=是对信号赋值；而:=是对变量进行赋值 variable cqi :std_logic_vector(3 downto 0); begin

-- others =>'0'是对数组cqi所有元素赋值0 if rst='1' then cqi :=(others =>'0'); elsif fx'event and fx='1' then if ena ='1' then if cqi < 9 then

cqi:=cqi+1;cout<='0'; elsif cqi=9 then

cqi :=(others =>'0'); cout<='1'; end if;

elsif ena='0' then cqi:=(others =>'0'); end if; end if; outy <=cqi; end process; end behv;

-- 4位10进计数器 library ieee;

use ieee.std_logic_1164.all; entity cnt10_4 is

port(fx,rst,ena,clk:in std_logic;

d:out std_logic_vector(15 downto 0); led_a:out std_logic); end entity;

architecture one of cnt10_4 is component cnt10

port (rst,fx,ena:in std_logic; cout: out std_logic;

outy :out std_logic_vector(3 downto 0)); end component;

component led_hehe port(

ena,clk:in std_logic; q:out std_logic); end component;

signal e:std_logic_vector(3 downto 0); begin

-- 整体使用相同的rst和ena，fx作为进位使用。

u1:cnt10 port map(fx=>fx,rst=>rst,ena=>ena,cout=>e(0),outy=>d(3 downto 0)); u2:cnt10 port map(fx=>e(0),rst=>rst,ena=>ena,cout=>e(1),outy=>d(7 downto 4)); u3:cnt10 port map(fx=>e(1),rst=>rst,ena=>ena,cout=>e(2),outy=>d(11 downto 8)); u4:cnt10 port map(fx=>e(2),rst=>rst,ena=>ena,cout=>e(3),outy=>d(15 downto 12)); u5:led_hehe port map(ena=>e(3),clk=>clk,q=>led_a); end architecture one;

-- 16位锁存器 latch=闩 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity latch4 is

port(d:in std_logic_vector(15 downto 0); ena,clk:in std_logic;

q:out std_logic_vector(15 downto 0)); end latch4;

architecture one of latch4 is

begin

process(clk,ena,d)

variable cqi:std_logic_vector(15 downto 0); begin

if ena='0' then cqi:=cqi;--- ena=0 锁存上次的数据

elsif clk'event and clk='1' then cqi:=d;---clk=1&&ena=1 计入新数据 end if; q<=cqi; end process;

end one;

-- 报警led hehe library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all; entity led_hehe is port(

ena,clk:in std_logic; q:out std_logic); end led_hehe;

architecture one of led_hehe is begin

process(clk,ena)

variable cqi:std_logic; begin

if ena='0' then cqi:=cqi;--- ena=0 锁存上次的数据

elsif clk'event and clk='1' then cqi:= not cqi;---clk=1&&ena=1 计入新数据 end if; q<=cqi; end process; end one;

-- LED控制模块(数码管controller) library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity led_controller is

port(d:in std_logic_vector(3 downto 0); a:out std_logic_vector(6 downto 0)); end led_controller;

architecture one of led_controller is begin

process(d) begin case d is

when \ when \ when \ when \ when \ when \ when \ when \ when others=> null; end case;

end process; end;

-- 控制模块(每隔一次clk，就翻转ena和rst) library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity control is

port (clk:in std_logic;

rst,ena: out std_logic); end control;

architecture behv of control is begin

process (clk)

variable cqi :std_logic_vector(2 downto 0); begin

if clk'event and clk='1' then

if cqi <1 then cqi:=cqi+1;ena<='1';rst<='0'; elsif cqi=1 then

cqi :=(others =>'0'); ena<='0';rst<='1'; end if; end if; end process; end behv;

-- 时钟（1hz）发生器 library ieee;

use ieee.std_logic_1164.all;

entity freq_div is

port (clk:in std_logic;

clk_out:out std_logic); end freq_div;

architecture fwm of freq_div is constant m: integer:= 25000; signal tmp:std_logic; begin

process(clk,tmp)

variable cout:integer:=0; begin

if clk'event and clk='1' then

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