FPGA芯片中支持不同io电平标准

在fpga芯片中支持不同io电平标准

2008-06-06 15:15:39| 分类： FPGA AND DSP | 标签： |字号大中小 订阅

I/O Banking

Some of the I/O standards described above require VCCO and/or VREF voltages. These voltages are externally supplied and connected to device pins that serve groups of IOBs, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank. Eight I/O banks result from separating each edge of the FPGA into two banks (see Figure 3). The pinout tables show the bank affiliation of each I/O (see Pinout Tables, Module 4). Each bank has multiple VCCO pins which must be connected to the same voltage. Voltage requirements are determined by the output standards in use.

In the TQ144 and PQ208 packages, the eight banks have VCCO connected together. Thus, only one VCCO level is allowed in these packages, although different VREF values are allowed in each of the eight banks.Within a bank, standards may be mixed only if they use the same VCCO. [在spartan IIE的这两种封装中，每一个bank的io电引脚是连在一起的，而参考电平引脚是在不同的bank中是独立的，也就是说在所有bank中只能有一个io电平，每一个bank可以有自己的电平。在同一个bank中，可以支持不同的电平标准，但要求电平标准要相互兼容]Compatible standards are shown in Table 2.GTL and GTL+ appear under all voltages because their open-drain outputs do not depend on VCCO. Note that VCCO is required for most output standards and for LVTTL,LVCMOS, and PCI inputs. VCCO 3.3V 2.5V 1.8V 1.5V Compatible Standards PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, LVPECL, GTL, GTL+ SSTL2 I, SSTL2 II, LVCMOS2, LVDS, Bus LVDS, GTL, GTL+ LVCMOS18, GTL, GTL+ HSTL I, HSTL III, HSTL IV, GTL, GTL+ Some input standards require a user-supplied threshold voltage, VREF. In this case, certain user-I/O pins are automatically configured as inputs for the VREF voltage. About one in six of the I/O pins in the bank assume this role. VREF pins within a bank are interconnected internally and consequently only one VREF voltage can be used within each bank. All VREF pins in the bank, however, must be connected to the external voltage source for correct operation.In a bank, inputs requiring VREF can be mixed with those

that do not but only one VREF voltage may be used within a bank. The VCCO and VREF pins for each bank appear in the device pinout tables. Within a given package, the number of VREF and VCCO pins can vary depending on the size of device. In larger devices, more I/O pins convert to VREF pins. Since these are always a superset of the VREF pins used for smaller devices, it is

possible to design a PCB that permits migration to a larger device. All VREF pins for the largest device anticipated must be connected to the VREF voltage, and not used for I/O.

不同BANK可以用不同的IO电压，可以用不同的IO标准。同一BANK中只能用相同电压IO标准。（不太贴切）

I/O 电平标准： GTL+: Vref= 1.0v HSTL Class I: Vref= 0.75v HSTL Class II: Vref= 0.75v HSTL Class III: Vref= 0.9v HSTL Class IV: Vref= 0.9v SSTL2 Class I: Vref= 1.25v SSTL2 Class II: Vref= 1.25v SSTL3 Class I: Vref= 1.5v SSTL3 Class II: Vref= 1.5v I/O Standard LVTTL (2-24 mA) LVCMOS2 LVCMOS18 PCI (3V, 33 MHz/66 MHz) GTL GTL+ HSTL Class I HSTL Class III HSTL Class IV SSTL3 Class I and II SSTL2 Class I and II CTT AGP LVDS, Bus LVDS Input Ref. Volt. (VREF) N/A N/A N/A N/A 0.8 1.0 0.75 0.9 0.9 1.5 1.25 1.5 1.32 N/A Input Volt. (VCCO) 3.3 2.5 1.8 3.3 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Output Source Volt. (VCCO) 3.3 2.5 1.8 3.3 N/A N/A 1.5 1.5 1.5 3.3 2.5 3.3 3.3 2.5 Board Term. Volt. (VTT) N/A N/A N/A N/A 1.2 1.5 0.75 1.5 1.5 1.5 1.25 1.5 N/A N/A LVPECL I/O Standard LVTTL (2-24 mA) LVCMOS2 LVCMOS18 PCI (3V, 33MHz/66 MHz) GTL GTL+ HSTL Class I HSTL Class III HSTL Class IV SSTL3 Class I and II SSTL2 Class I and II CTT AGP LVDS, Bus LVDS LVPECL N/A (VREF) N/A N/A N/A N/A 0.8 1.0 0.75 0.9 0.9 1.5 1.25 1.5 1.32 N/A N/A N/A (VCCO) 3.3 2.5 1.8 3.3 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 3.3 (VCCO) 3.3 2.5 1.8 3.3 N/A N/A 1.5 1.5 1.5 3.3 2.5 3.3 3.3 2.5 3.3 N/A (VTT) N/A N/A N/A N/A 1.2 1.5 0.75 1.5 1.5 1.5 1.25 1.5 N/A N/A N/A <> xilinx FGPA SPARTAN IIE I/O 管脚可以配置多种I/O 标准，当和这些电平信号相连时，需要外接相应的Vref 电压.（有些电平标准，具体可看数据手册，如上面spartan iie） 所谓的VREF，指的是器件IO PIN的参考电压，对于LVTTL,LVCOMS2，LVCOMS18等信号电平标准来说，是不需要接VREF的，但是如果是GTL，STL等电平标准来说，VREF是必须的。

简而言之，需要或者不需要接VREF是由其I/O信号需要还是不需要VREF来决定的。 如，GTL的偏置电压为0.8V，那么VREF就必须接0.8V电压。这个电压是给接口信号提供的参考电压，跟FPGA的内核，接口电压等等没有什么关系。

The Spartan-3E Starter Kit boards includes a 512 Mbit (32M x 16) Micron Technology DDR

SDRAM (MT46V32M16) with a 16-bit data interface, as shown in Figure 13-1. All DDR

SDRAM interface pins connect to the FPGA’s I/O Bank 3 on the FPGA. I/O Bank 3 and the

DDR SDRAM are both powered by 2.5V, generated by an LTC3412 regulator from the

board’s 5V supply input. The 1.25V reference voltage, common to the FPGA and DDR

SDRAM, is generated using a resistor voltage divider from the 2.5V rail. Address

Figure 13-2 provides the User Constraint File (UCF) constraints for the DDR SDRAM address pins, including the I/O pin assignment and the I/O standard used. Data

Figure 13-3 provides the User Constraint File (UCF) constraints for the DDR SDRAM data

pins, including the I/O pin assignment and I/O standard used.

Figure 13-2: UCF Location Constraints for DDR SDRAM Address Inputs NET \NET \NET \NET \NET \NET \NET \NET \NET \NET \NET \NET \NET \Figure 13-3: UCF Location Constraints for DDR SDRAM Data I/Os NET \NET \NET \NET \NET \NET \NET \NET \NET \NET \

NET \NET \NET \NET \NET \NET \

Figure 13-4 provides the User Constraint File (UCF) constraints for the DDR SDRAM control pins, including the I/O pin assignment and the I/O standard used. Reserve FPGA VREF Pins

Five pins in I/O Bank 3 are dedicated as voltage reference inputs, VREF. These pins cannot

be used for general-purpose I/O in a design. Prohibit the software from using these with the constraints provided in Figure 13-5. 5i

Figure 13-4: UCF Location Constraints for DDR SDRAM Control Pins NET \NET \NET \NET \NET \NET \NET \NET \NET \NET \NET \NET \NET \# Path to allow connection to top DCM connection

NET \Figure 13-5: UCF Location Constraints for StrataFlash Control Pins # Prohibit VREF pins CONFIG PROHIBIT = D2; CONFIG PROHIBIT = G4; CONFIG PROHIBIT = J6;

CONFIG PROHIBIT = L5; CONFIG PROHIBIT = R4;

From spartan 3e start kit user guide

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