数字集成电路：电路系统与设计(第二版) (1)

数字集成电路(设计透视)

CHAPTER

1

INTRODUCTIONThe evolution of digital circuit design

n

Compelling issues in digital circuit design

n

How to measure the quality of a design

n

Valuable references

1.1

1.2

1.3

1.4

1.5A Historical PerspectiveIssues in Digital Integrated Circuit DesignQuality Metrics of a Digital DesignSummaryTo Probe Further

9

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10INTRODUCTIONChapter 1

1.1A Historical Perspective

The concept of digital data manipulation has made a dramatic impact on our society. Onehas long grown accustomed to the idea of digital computers. Evolving steadily from main-frame and minicomputers, personal and laptop computers have proliferated into daily life.More significant, however, is a continuous trend towards digital solutions in all otherareas of electronics. Instrumentation was one of the first noncomputing domains where thepotential benefits of digital data manipulation over analog processing were recognized.Other areas such as control were soon to follow. Only recently have we witnessed the con-version of telecommunications and consumer electronics towards the digital format.Increasingly, telephone data is transmitted and processed digitally over both wired andwireless networks. The compact disk has revolutionized the audio world, and digital videois following in its footsteps.

The idea of implementing computational engines using an encoded data format is by

no means an idea of our times. In the early nineteenth century, Babbage envisioned large-scale mechanical computing devices, called Difference Engines [Swade93]. Althoughthese engines use the decimal number system rather than the binary representation nowcommon in modern electronics, the underlying concepts are very similar. The AnalyticalEngine, developed in 1834, was perceived as a general-purpose computing machine, withfeatures strikingly close to modern computers. Besides executing the basic repertoire ofoperations (addition, subtraction, multiplication, and division) in arbitrary sequences, themachine operated in a two-cycle sequence, called “store” and “mill” (execute), similar tocurrent computers. It even used pipelining to speed up the execution of the addition opera-tion! Unfortunately, the complexity and the cost of the designs made the concept impracti-cal. For instance, the design of Difference Engine I (part of which is shown in Figure 1.1)

required 25,000 mechanical parts at a total cost of £17,470 (in 1834!).

Figure 1.1Working part of Babbage’s

Difference Engine I (1832), the first known

automatic calculator (from [Swade93],

courtesy of the Science Museum of London).

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Section 1.1A Historical Perspective11

The electrical solution turned out to be more cost effective. Early digital electronics

systems were based on magnetically controlled switches (or relays). They were mainlyused in the implementation of very simple logic networks. Examples of such are trainsafety systems, where they are still being used at present. The age of digital electroniccomputing only started in full with the introduction of the vacuum tube. While originallyused almost exclusively for analog processing, it was realized early on that the vacuumtube was useful for digital computations as well. Soon complete computers were realized.The era of the vacuum tube based computer culminated in the design of machines such asthe ENIAC (intended for computing artillery firing tables) and the UNIVAC I (the firstsuccessful commercial computer). To get an idea about integration density, the ENIACwas 80 feet long, 8.5 feet high and several feet wide and incorporated 18,000 vacuumtubes. It became rapidly clear, however, that this design technology had reached its limits.Reliability problems and excessive power consumption made the implementation of largerengines economically and practically infeasible.

All changed with the invention of the transistor at Bell Telephone Laboratories in

1947 [Bardeen48], followed by the introduction of the bipolar transistor by Schockley in1949 [Schockley49]1. It took till 1956 before this led to the first bipolar digital logic gate,introduced by Harris [Harris56], and even more time before this translated into a set ofintegrated-circuit commercial logic gates, called the Fairchild Micrologic family

[Norman60]. The first truly successful IC logic family, TTL (Transistor-Transistor Logic)was pioneered in 1962 [Beeson62]. Other logic families were devised with higher perfor-mance in mind. Examples of these are the current switching circuits that produced the firstsubnanosecond digital gates and culminated in the ECL (Emitter-Coupled Logic) family

[Masaki74]. TTL had the advantage, however, of offering a higher integration density andwas the basis of the first integrated circuit revolution. In fact, the manufacturing of TTLcomponents is what spear-headed the first large semiconductor companies such as Fair-child, National, and Texas Instruments. The family was so successful that it composed thelargest fraction of the digital semiconductor market until the 1980s.

Ultimately, bipolar digital logic lost the battle for hegemony in the digital design

world for exactly the reasons that haunted the vacuum tube approach: the large power con-sumption per gate puts an upper limit on the number of gates that can be reliably integratedon a single die, package, housing, or box. Although attempts were made to develop highintegration density, low-power bipolar families (such as I2L—Integrated Injection Logic

[Hart72]), the torch was gradually passed to the MOS digital integrated circuit approach.

The basic principle behind the MOSFET transistor (originally called IGFET) was

proposed in a patent by J. Lilienfeld (Canada) as early as 1925, and, independently, by O.Heil in England in 1935. Insufficient knowledge of the materials and gate stability prob-lems, however, delayed the practical usability of the device for a long time. Once thesewere solved, MOS digital integrated circuits started to take off in full in the early 1970s.Remarkably, the first MOS logic gates introduced were of the CMOS variety

[Wanlass63], and this trend continued till the late 1960s. The complexity of the manufac-turing process delayed the full exploitation of these devices for two more decades. Instead,

An intriguing overview of the evolution of digital integrated circuits can be found in [Murphy93].

(Most of the data in this overview has been extracted from this reference). It is accompanied by some of the his-torically ground-breaking publications in the domain of digital IC’s.1

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12INTRODUCTIONChapter 1

the first practical MOS integrated circuits were implemented in PMOS-only logic andwere used in applications such as calculators. The second age of the digital integrated cir-cuit revolution was inaugurated with the introduction of the first microprocessors by Intelin 1972 (the 4004) [Faggin72] and 1974 (the 8080) [Shima74]. These processors wereimplemented in NMOS-only logic, which has the advantage of higher speed over thePMOS logic. Simultaneously, MOS technology enabled the realization of the first high-density semiconductor memories. For instance, the first 4Kbit MOS memory was intro-duced in 1970 [Hoff70].

These events were at the start of a truly astounding evolution towards ever higher

integration densities and speed performances, a revolution that is still in full swing rightnow. The road to the current levels of integration has not been without hindrances, how-ever. In the late 1970s, NMOS-only logic started to suffer from the same plague that madehigh-density bipolar logic unattractive or infeasible: power consumption. This realization,combined with progress in manufacturing technology, finally tilted the balance towardsthe CMOS technology, and this is where we still are today. Interestingly enough, powerconsumption concerns are rapidly becoming dominant in CMOS design as well, and thistime there does not seem to be a new technology around the corner to alleviate theproblem.

Although the large majority of the current integrated circuits are implemented in the

MOS technology, other technologies come into play when very high performance is atstake. An example of this is the BiCMOS technology that combines bipolar and MOSdevices on the same die. BiCMOS is used in high-speed memories and gate arrays. Wheneven higher performance is necessary, other technologies emerge besides the already men-tioned bipolar silicon ECL family—Gallium-Arsenide, Silicon-Germanium and evensuperconducting technologies. These technologies only play a very small role in the over-all digital integrated circuit design scene. With the ever increasing performance of CMOS,this role is bound to be further reduced with time. Hence the focus of this textbook onCMOS only.

1.2Issues in Digital Integrated Circuit Design

Integration density and performance of integrated circuits have gone through an astound-ing revolution in the last couple of decades. In the 1960s, Gordon Moore, then with Fair-child Corporation and later cofounder of Intel, predicted that the number of transistors thatcan be integrated on a single die would grow exponentially with time. This prediction,later called Moore’s law, has proven to be amazingly visionary [Moore65]. Its validity isbest illustrated with the aid of a set of graphs. Figure 1.2 plots the integration density ofboth logic IC’s and memory as a function of time. As can be observed, integration com-plexity doubles approximately every 1 to 2 years. As a result, memory density hasincreased by more than a thousandfold since 1970.

An intriguing case study is offered by the microprocessor. From its inception in the

early seventies, the microprocessor has grown in performance and complexity at a steadyand predictable pace. The transistor counts for a number of landmark designs are collectedin Figure 1.3. The million-transistor/chip barrier was crossed in the late eighties. Clockfrequencies double every three years and have reached into the GHz range. This is illus-

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Section 1.2Issues in Digital Integrated Circuit Design13

(a) Trends in logic IC complexityFigure 1.2(b) Trends in memory complexityEvolution of integration complexity of logic ICs and memories as a function of time.

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INTRODUCTIONChapter 1

Figure 1.4Microprocessor performance trends at the beginning of the 21st century.

design and also explains why, for instance, very large scale analog design has nevercaught on.

The obvious next question is why such an approach is feasible in the digital world

and not (or to a lesser degree) in analog designs. The crucial concept here, and the mostimportant one in dealing with the complexity issue, is abstraction. At each design level,the internal details of a complex module can be abstracted away and replaced by a blackbox view or model. This model contains virtually all the information needed to deal withthe block at the next level of hierarchy. For instance, once a designer has implemented amultiplier module, its performance can be defined very accurately and can be captured in amodel. The performance of this multiplier is in general only marginally influenced by theway it is utilized in a larger system. For all purposes, it can hence be considered a blackbox with known characteristics. As there exists no compelling need for the systemdesigner to look inside this box, design complexity is substantially reduced. The impact ofthis divide and conquer approach is dramatic. Instead of having to deal with a myriad ofelements, the designer has to consider only a handful of components, each of which arecharacterized in performance and cost by a small number of parameters.

This is analogous to a software designer using a library of software routines such as

input/output drivers. Someone writing a large program does not bother to look inside thoselibrary routines. The only thing he cares about is the intended result of calling one of thosemodules. Imagine what writing software programs would be like if one had to fetch everybit individually from the disk and ensure its correctness instead of relying on handy “fileopen” and “get string” operators.

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Section 1.2Issues in Digital Integrated Circuit Design

15

(a)The 4004 microprocessor Standard Cell Module

Memory Module

(b)The Pentium ® 4 microprocessor

Figure 1.5Comparing the design methodologies of the Intel 4004 (1971) and Pentium ® 4 (2000

microprocessors (reprinted with permission from Intel).

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16INTRODUCTIONChapter 1

Typically used abstraction levels in digital circuit design are, in order of increasing

abstraction, the device, circuit, gate, functional module (e.g., adder) and system levels(e.g., processor), as illustrated in Figure 1.6. A semiconductor device is an entity with a

SYSTEM

MODULE

+

GATECIRCUIT

DEVICE

GS

n+n+D

Figure 1.6Design abstraction levels in digital circuits.

very complex behavior. No circuit designer will ever seriously consider the solid-statephysics equations governing the behavior of the device when designing a digital gate.Instead he will use a simplified model that adequately describes the input-output behaviorof the transistor. For instance, an AND gate is adequately described by its Boolean expres-sion (Z = A.B), its bounding box, the position of the input and output terminals, and thedelay between the inputs and the output.

This design philosophy has been the enabler for the emergence of elaborate com-

puter-aided design (CAD) frameworks for digital integrated circuits; without it the currentdesign complexity would not have been achievable. Design tools include simulation at thevarious complexity levels, design verification, layout generation, and design synthesis. Anoverview of these tools and design methodologies is given in Chapter 8 of this textbook.

Furthermore, to avoid the redesign and reverification of frequently used cells such

as basic gates and arithmetic and memory modules, designers most often resort to celllibraries. These libraries contain not only the layouts, but also provide complete docu-mentation and characterization of the behavior of the cells. The use of cell libraries is, for

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Section 1.2Issues in Digital Integrated Circuit Design17

instance, apparent in the layout of the Pentium ® 4 processor (Figure 1.5b). The integerand floating-point unit, just to name a few, contain large sections designed using the so-called standard cell approach. In this approach, logic gates are placed in rows of cells ofequal height and interconnected using routing channels. The layout of such a block can begenerated automatically given that a library of cells is available.

The preceding analysis demonstrates that design automation and modular design

practices have effectively addressed some of the complexity issues incurred in contempo-rary digital design. This leads to the following pertinent question. If design automationsolves all our design problems, why should we be concerned with digital circuit design atall? Will the next-generation digital designer ever have to worry about transistors or para-sitics, or is the smallest design entity he will ever consider the gate and the module?

The truth is that the reality is more complex, and various reasons exist as to why an

insight into digital circuits and their intricacies will still be an important asset for a longtime to come.

First of all, someone still has to design and implement the module libraries. Semi-

conductor technologies continue to advance from year to year. Until one has devel-

oped a fool-proof approach towards “porting” a cell from one technology to another,

each change in technology—which happens approximately every two

years—requires a redesign of the library.

Creating an adequate model of a cell or module requires an in-depth understanding

of its internal operation. For instance, to identify the dominant performance parame-

ters of a given design, one has to recognize the critical timing path first.

The library-based approach works fine when the design constraints (speed, cost or

power) are not stringent. This is the case for a large number of application-specific

designs, where the main goal is to provide a more integrated system solution, and

performance requirements are easily within the capabilities of the technology.

Unfortunately for a large number of other products such as microprocessors, success

hinges on high performance, and designers therefore tend to push technology to its

limits. At that point, the hierarchical approach tends to become somewhat less

attractive. To resort to our previous analogy to software methodologies, a program-

mer tends to “customize” software routines when execution speed is crucial; com-

pilers—or design tools—are not yet to the level of what human sweat or ingenuity

can deliver.

Even more important is the observation that the abstraction-based approach is only

correct to a certain degree. The performance of, for instance, an adder can be sub-

stantially influenced by the way it is connected to its environment. The interconnec-

tion wires themselves contribute to delay as they introduce parasitic capacitances,

resistances and even inductances. The impact of the interconnect parasitics is bound

to increase in the years to come with the scaling of the technology.

Scaling tends to emphasize some other deficiencies of the abstraction-based model.

Some design entities tend to be global or external (to resort anew to the software

analogy). Examples of global factors are the clock signals, used for synchronizationin a digital design, and the supply lines. Increasing the size of a digital design has a

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18INTRODUCTIONChapter 1

profound effect on these global signals. For instance, connecting more cells to a sup-

ply line can cause a voltage drop over the wire, which, in its turn, can slow down all

the connected cells. Issues such as clock distribution, circuit synchronization, and

supply-voltage distribution are becoming more and more critical. Coping with them

requires a profound understanding of the intricacies of digital circuit design.

Another impact of technology evolution is that new design issues and constraints

tend to emerge over time. A typical example of this is the periodical reemergence of

power dissipation as a constraining factor, as was already illustrated in the historical

overview. Another example is the changing ratio between device and interconnect

parasitics. To cope with these unforeseen factors, one must at least be able to model

and analyze their impact, requiring once again a profound insight into circuit topol-

ogy and behavior.

Finally, when things can go wrong, they do. A fabricated circuit does not always

exhibit the exact waveforms one might expect from advance simulations. Deviations

can be caused by variations in the fabrication process parameters, or by the induc-

tance of the package, or by a badly modeled clock signal. Troubleshooting a design

requires circuit expertise.

For all the above reasons, it is my belief that an in-depth knowledge of digital circuitdesign techniques and approaches is an essential asset for a digital-system designer. Eventhough she might not have to deal with the details of the circuit on a daily basis, the under-standing will help her to cope with unexpected circumstances and to determine the domi-nant effects when analyzing a design.

Example 1.1Clocks Defy Hierarchy

To illustrate some of the issues raised above, let us examine the impact of deficiencies in oneof the most important global signals in a design, the clock. The function of the clock signal in

a digital design is to order the multitude of events happening in the circuit. This task can be

compared to the function of a traffic light that determines which cars are allowed to move. It

also makes sure that all operations are completed before the next one starts—a traffic light

should be green long enough to allow a car or a pedestrian to cross the road. Under ideal cir-

cumstances, the clock signal is a periodic step waveform with transitions synchronized

throughout the designed circuit (Figure 1.7a). In light of our analogy, changes in the traffic

lights should be synchronized to maximize throughput while avoiding accidents. The impor-

tance of the clock alignment concept is illustrated with the example of two cascaded registers,

both operating on the rising edge of the clock φ (Figure 1.7b). Under normal operating condi-

tions, the input In gets sampled into the first register on the rising edge of φ and appears at the

output exactly one clock period later. This is confirmed by the simulations shown in Figure

1.8c (signal Out).

Due to delays associated with routing the clock wires, it may happen that the clocks

become misaligned with respect to each other. As a result, the registers are interpreting time

indicated by the clock signal differently. Consider the case that the clock signal for the second

register is delayed—or skewed—by a value δ. The rising edge of the delayed clock φ′ will

postpone the sampling of the input of the second register. If the time it takes to propagate the

output of the first register to the input of the second is smaller than the clock delay, the latterwill sample the wrong value. This causes the output to change prematurely, as clearly illus-

trated in the simulation, where the signal Out′ goes high at the first rising edge of φ′ instead of

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Section 1.2Issues in Digital Integrated Circuit Design19

φ (Volt)3

2Voltt (nsec)

(a) Ideal clock waveformInInφ10φ′skew

REGISTER3

2VoltOut’

1

0Outskewφ′

(b) Two cascaded registers

Figure 1.7Impact of clock misalignment.

the second one. In terms of our traffic analogy, cars of a first traffic light hit the cars of the

next light that have not left yet.

Clock misalignment, or clock skew, as it is normally called, is an important example of

how global signals may influence the functioning of a hierarchically designed system. Clock

skew is actually one of the most critical design problems facing the designers of large, high-performance systems.

Example 1.2Power Distribution Networks Defy Hierarchy

While the clock signal is one example of a global signal that crosses the chip hierarchyboundaries, the power distribution network represents another. A digital system requires astable DC voltage to be supplied to the individual gates. To ensure proper operation, thisvoltage should be stable within a few hundred millivolts. The power distribution systemhas to provide this stable voltage in the presence of very large current variations. Theresistive nature of the on-chip wires and the inductance of the IC package pins make this adifficult proposition. For example, the average DC current to be supplied to a 100 W-1Vmicroprocessor equals 100 A! The peak current can easily be twice as large, and currentdemand can readily change from almost zero to this peak value over a short time—in therange of 1 nsec or less. This leads to a current variation of 100 GA/sec, which is a trulyastounding number.

Consider the problem of the resistance of power-distribution wires. A current of 1 A

running through a wire with a resistance of 1 causes a voltage drop of 1V. With supplyvoltages of modern digital circuits ranging between 1.2 and 2.5 V, such a drop is unaccept-φREGISTEROuttime(c) Simulated waveforms

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20INTRODUCTIONChapter 1

(a) Routing through the block

Figure 1.8Power distribution network design.(b) Routing around the block

able. Making the wires wider reduces the resistance, and hence the voltage drop. Whilethis sizing of the power network is relatively simple in a flat design approach, it is a lotmore complex in a hierarchical design. For example, consider the two blocks below inFigure 1.8a [Saleh01]. If power distribution for Block A is examined in isolation, the addi-tional loading due to the presence of Block B is not taken into account. If power is routedthrough Block A to Block B, a larger IR drop will occur in Block B since power is alsobeing consumed by Block A before it reaches Block B.

Since the total IR drop is based on the resistance seen from the pin to the block, one

could route around the block and feed power to each block separately, as shown in Figure

1.8b. Ideally, the main trunks should be large enough to handle all the current flowingthrough separate branches. Although routing power this way is easier to control and main-tain, it also requires more area to implement. The large metal trunks of power have to besized to handle all the current for each block. This requirement forces designers to setaside area for power busing that takes away from the available routing area.

As more and more blocks are added, the complex interactions between the blocks

determine the actual voltage drops. For instance, it is not always easy to determine whichway the current will flow when multiple parallel paths are available between the powersource and the consuming gate. Also, currents into the different modules do rarely peak atthe same time. All these considerations make the design of the power-distribution a chal-lenging job. It requires a design methodology approach that supersedes the artificialboundaries imposed by hierarchical design.

The purpose of this textbook is to provide a bridge between the abstract vision of

digital design and the underlying digital circuit and its peculiarities. While starting from asolid understanding of the operation of electronic devices and an in-depth analysis of thenucleus of digital design—the inverter—we will gradually channel this knowledge intothe design of more complex entities, such as complex gates, datapaths, registers, control-lers, and memories. The persistent quest for a designer when designing each of the men-tioned modules is to identify the dominant design parameters, to locate the section of thedesign he should focus his optimizations on, and to determine the specific properties thatmake the module under investigation (e.g., a memory) different from any others.

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Section 1.3Quality Metrics of a Digital Design21

The text also addresses other compelling (global) issues in modern digital circuit

design such as power dissipation, interconnect, timing, and synchronization.

1.3Quality Metrics of a Digital Design

This section defines a set of basic properties of a digital design. These properties help toquantify the quality of a design from different perspectives: cost, functionality, robustness,performance, and energy consumption. Which one of these metrics is most importantdepends upon the application. For instance, pure speed is a crucial property in a computeserver. On the other hand, energy consumption is a dominant metric for hand-held mobileapplications such as cell phones. The introduced properties are relevant at all levels of thedesign hierarchy, be it system, chip, module, and gate. To ensure consistency in the defini-tions throughout the design hierarchy stack, we propose a bottom-up approach: we startwith defining the basic quality metrics of a simple inverter, and gradually expand these tothe more complex functions such as gate, module, and chip.

1.3.1Cost of an Integrated Circuit

The total cost of any product can be separated into two components: the recurringexpenses or the variable cost, and the non-recurring expenses or the fixed cost.

Fixed Cost

The fixed cost is independent of the sales volume, the number of products sold. An impor-tant component of the fixed cost of an integrated circuit is the effort in time and man-power it takes to produce the design. This design cost is strongly influenced by the com-plexity of the design, the aggressiveness of the specifications, and the productivity of thedesigner. Advanced design methodologies that automate major parts of the design processcan help to boost the latter. Bringing down the design cost in the presence of an ever-increasing IC complexity is one of the major challenges that is always facing the semicon-ductor industry.

Additionally, one has to account for the indirect costs, the company overhead that

cannot be billed directly to one product. It includes amongst others the company’sresearch and development (R&D), manufacturing equipment, marketing, sales, and build-ing infrastructure.

Variable Cost

This accounts for the cost that is directly attributable to a manufactured product, and ishence proportional to the product volume. Variable costs include the costs of the partsused in the product, assembly costs, and testing costs. The total cost of an integrated cir-cuit is now

fixed costcost per IC=variable cost per IC+ ---------------------- volume (1.1)

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22INTRODUCTIONChapter 1

Individual die

Figure 1.9Finished wafer. Each

square represents a die - in this case

the AMD Duron microprocessor

(Reprinted with permission from AMD).

The impact of the fixed cost is more pronounced for small-volume products. This alsoexplains why it makes sense to have large design team working for a number of years on ahugely successful product such as a microprocessor.

While the cost of producing a single transistor has dropped exponentially over the

past decades, the basic variable-cost equation has not changed:

+cost of die test+cost of packagingvariable cost=cost of die------------------------------------------------------------------------------------------------------------------final test yield(1.2)

As will be elaborated on in Chapter 2, the IC manufacturing process groups a number ofidentical circuits onto a single wafer (Figure 1.9). Upon completion of the fabrication, thewafer is chopped into dies, which are then individually packaged after being tested. Wewill focus on the cost of the dies in this discussion. The cost of packaging and test is thetopic of later chapters.

The die cost depends upon the number of good die on a wafer, and the percentage of

those that are functional. The latter factor is called the die yield.

cost of wafercost of die=------------------------------------------------------------dies per wafer×die yield(1.3)

The number of dies per wafer is, in essence, the area of the wafer divided by the diearea.The actual situation is somewhat more complicated as wafers are round, and chips aresquare. Dies around the perimeter of the wafer are therefore lost. The size of the wafer hasbeen steadily increasing over the years, yielding more dies per fabrication run. Eq. (1.3)also presents the first indication that the cost of a circuit is dependent upon the chiparea—increasing the chip area simply means that less dies fit on a wafer.

The actual relation between cost and area is more complex, and depends upon the

die yield. Both the substrate material and the manufacturing process introduce faults thatcan cause a chip to fail. Assuming that the defects are randomly distributed over the wafer,and that the yield is inversely proportional to the complexity of the fabrication process, weobtain the following expression of the die yield:

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Section 1.3Quality Metrics of a Digital Design23

defects per unit area×die area –α die yield =1+------------------------------------------------------------------------- α(1.4)

α is a parameter that depends upon the complexity of the manufacturing process, and isroughly proportional to the number of masks. α = 3 is a good estimate for today’s complexCMOS processes. The defects per unit area is a measure of the material and processinduced faults. A value between 0.5 and 1 defects/cm2 is typical these days, but dependsstrongly upon the maturity of the process.

Example 1.3Die Yield

Assume a wafer size of 12 inch, a die size of 2.5 cm2, 1 defects/cm2, and α = 3. Determine the

die yield of this CMOS process run.

The number of dies per wafer can be estimated with the following expression, which

takes into account the lost dies around the perimeter of the wafer.

(wafer diameter ---2)wafer diameterdies per wafer=π-----×---------------------------------------------------–π-----×---------die areaThis means 252 (= 296 - 44) potentially operational dies for this particular example. The dieyield can be computed with the aid of Eq. (1.4), and equals 16%! This means that on the aver-

age only 40 of the dies will be fully functional.2

The bottom line is that the number of functional of dies per wafer, and hence the

cost per die is a strong function of the die area. While the yield tends to be excellent for thesmaller designs, it drops rapidly once a certain threshold is exceeded. Bearing in mind theequations derived above and the typical parameter values, we can conclude that die costsare proportional to the fourth power of the area:

cost of die=f(die area)4(1.5)

The area is a function that is directly controllable by the designer(s), and is the prime met-ric for cost. Small area is hence a desirable property for a digital gate. The smaller thegate, the higher the integration density and the smaller the die size. Smaller gates further-more tend to be faster and consume less energy, as the total gate capacitance—which isone of the dominant performance parameters—often scales with the area.

The number of transistors in a gate is indicative for the expected implementation

area. Other parameters may have an impact, though. For instance, a complex interconnectpattern between the transistors can cause the wiring area to dominate. The gate complex-ity, as expressed by the number of transistors and the regularity of the interconnect struc-ture, also has an impact on the design cost. Complex structures are harder to implementand tend to take more of the designers valuable time. Simplicity and regularity is a pre-cious property in cost-sensitive designs.

1.3.2Functionality and Robustness

A prime requirement for a digital circuit is, obviously, that it performs the function it isdesigned for. The measured behavior of a manufactured circuit normally deviates from the

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24INTRODUCTIONChapter 1

expected response. One reason for this aberration are the variations in the manufacturingprocess. The dimensions, threshold voltages, and currents of an MOS transistor varybetween runs or even on a single wafer or die. The electrical behavior of a circuit can beprofoundly affected by those variations. The presence of disturbing noise sources on or offthe chip is another source of deviations in circuit response. The word noise in the contextof digital circuits means “unwanted variations of voltages and currents at the logicnodes.” Noise signals can enter a circuit in many ways. Some examples of digital noisesources are depicted in Figure 1.10. For instance, two wires placed side by side in an inte-grated circuit form a coupling capacitor and a mutual inductance. Hence, a voltage or cur-rent change on one of the wires can influence the signals on the neighboring wire. Noiseon the power and ground rails of a gate also influences the signal levels in the gate.

Most noise in a digital system is internally generated, and the noise value is propor-

tional to the signal swing. Capacitive and inductive cross talk, and the internally-generatedpower supply noise are examples of such. Other noise sources such as input power supplynoise are external to the system, and their value is not related to the signal levels. For thesesources, the noise level is directly expressed in Volt or Ampere. Noise sources that are afunction of the signal level are better expressed as a fraction or percentage of the signallevel. Noise is a major concern in the engineering of digital circuits. How to cope with allthese disturbances is one of the main challenges in the design of high-performance digitalcircuits and is a recurring topic in this book.

v(t)

i(t)VDD

(a) Inductive coupling(b) Capacitive coupling

Figure 1.10Noise sources in digital circuits.(c) Power and ground noise

The steady-state parameters (also called the static behavior) of a gate measure how

robust the circuit is with respect to both variations in the manufacturing process and noisedisturbances. The definition and derivation of these parameters requires a prior under-standing of how digital signals are represented in the world of electronic circuits.

Digital circuits (DC) perform operations on logical (or Boolean) variables. A logical

variable x can only assume two discrete values:

x ∈ {0,1}

As an example, the inversion (i.e., the function that an inverter performs) implements thefollowing compositional relationship between two Boolean variables x and y:

y = x = 0 y = 1; x = 1 y = 0}(1.6)

数字集成电路(设计透视)

Section 1.3Quality Metrics of a Digital Design25

A logical variable is, however, a mathematical abstraction. In a physical implemen-

tation, such a variable is represented by an electrical quantity. This is most often a nodevoltage that is not discrete but can adopt a continuous range of values. This electrical volt-age is turned into a discrete variable by associating a nominal voltage level with each logicstate: 1 VOH, 0 VOL, where VOH and VOL represent the high and the low logic levels,respectively. Applying VOH to the input of an inverter yields VOL at the output and viceversa. The difference between the two is called the logic or signal swing Vsw.

VOH=(VOL)

VOL=

(VOH)The Voltage-Transfer Characteristic

Assume now that a logical variable in serves as the input to an inverting gate that producesthe variable out. The electrical function of a gate is best expressed by its voltage-transfercharacteristic (VTC) (sometimes called the DC transfer characteristic), which plots theoutput voltage as a function of the input voltage Vout = f(Vin). An example of an inverterVTC is shown in Figure 1.11. The high and low nominal voltages, VOH and VOL, canreadily be identified—VOH = f(VOL) and VOL = f(VOH). Another point of interest of theVTC is the gate or switching threshold voltage VM (not to be confused with the thresholdvoltage of a transistor), that is defined as VM = f(VM). VM can also be found graphically atthe intersection of the VTC curve and the line given by Vout = Vin. The gate threshold volt-age presents the midpoint of the switching characteristics, which is obtained when the out-put of a gate is short-circuited to the input. This point will prove to be of particular interestwhen studying circuits with feedback (also called sequential circuits).

V(1.7)

VVFigure 1.11Inverter voltage-transfer

characteristic.OLOHin

Even if an ideal nominal value is applied at the input of a gate, the output signal

often deviates from the expected nominal value. These deviations can be caused by noiseor by the loading on the output of the gate (i.e., by the number of gates connected to theoutput signal). Figure 1.12a illustrates how a logic level is represented in reality by a rangeof acceptable voltages, separated by a region of uncertainty, rather than by nominal levels

数字集成电路(设计透视)

26INTRODUCTIONChapter 1

alone. The regions of acceptable high and low voltages are delimited by the VIH and VILvoltage levels, respectively. These represent by definition the points where the gain(=dVout/dVin) of the VTC equals 1 as shown in Figure 1.12b. The region between VIHand VIL is called the undefined region (sometimes also referred to as transition width, orTW). Steady-state signals should avoid this region if proper circuit operation is to beensured.

Noise Margins

For a gate to be robust and insensitive to noise disturbances, it is essential that the “0” and“1” intervals be as large as possible. A measure of the sensitivity of a gate to noise is givenby the noise margins NML (noise margin low) and NMH (noise margin high), which quan-tize the size of the legal “0” and “1”, respectively, and set a fixed maximum threshold onthe noise value:

NML=VIL–VOL

NMH=VOH–VIH(1.8)

The noise margins represent the levels of noise that can be sustained when gates are cas-caded as illustrated in Figure 1.13. It is obvious that the margins should be larger than 0for a digital circuit to be functional and by preference should be as large as possible.

Regenerative Property

A large noise margin is a desirable, but not sufficient requirement. Assume that a signal isdisturbed by noise and differs from the nominal voltage levels. As long as the signal iswithin the noise margins, the following gate continues to function correctly, although itsoutput voltage varies from the nominal one. This deviation is added to the noise injected atthe output node and passed to the next gate. The effect of different noise sources mayaccumulate and eventually force a signal level into the undefined region. This, fortunately,does not happen if the gate possesses the regenerative property, which ensures that a dis-

“1”

“0”

(a) Relationship between voltage and logic levels

Figure 1.12Mapping logic levels to the voltage domain. VOHVIHUndefinedRegionVILVOLVoutVOHSlope = -1Slope = -1VOLVILVIHin (b) Definition of VIH and VIL

数字集成电路(设计透视)

Section 1.3Quality Metrics of a Digital Design27

“1”

VOH

NMHVIH

Undefinedregion

VOL

“0”

Gate output

Stage MGate inputStage M + 1Figure 1.13Cascaded inverter gates: definition of noise margins.NMLVIL

turbed signal gradually converges back to one of the nominal voltage levels after passingthrough a number of logical stages. This property can be understood as follows:

An input voltage vin (vin ∈ “0”) is applied to a chain of N inverters (Figure 1.14a).

Assuming that the number of inverters in the chain is even, the output voltage vout (N →∞) will equal VOL if and only if the inverter possesses the regenerative property. Similarly,when an input voltage vin (vin ∈ “1”) is applied to the inverter chain, the output voltagewill approach the nominal value VOH.

…

v0v1v2v3v4v5v6

(a) A chain of inverters

5

v0

V (Volt)3(b)Simulated response of chain of MOS inverters

v1v21

–104

t (nsec)6810

Figure 1.14The regenerative property.

Example 1.4Regenerative property

The concept of regeneration is illustrated in Figure 1.14b, which plots the simulated transientresponse of a chain of CMOS inverters. The input signal to the chain is a step-waveform with

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