TMDS442PNPR中文资料

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TMDS442

SLLS757A–AUGUST2006–REVISEDMARCH2007

4-TO-2DVI/HDMISWITCH

FEATURES

A4-to-2Single-Linkor2-to-1Dual-LinkDVI/HDMIPhysicalLayerSwitchCompatiblewithHDMI1.3a

Supports2.25GbpsSignalingRatefor480i/p,720i/p,and1080i/pResolutionsupto12-BitColorDepth

IntegratedReceiverTerminations

8-dBReceiverEqualizerCompensatesforLossesFromStandardHDMICables

SelectableOutputDe-EmphasisCompensatesforLossesFromFlatCables

High-ImpedanceOutputsWhenDisabled

I2CRepeaterIsolatesBusCapacitanceatBothEnds

TMDSInputsHBMESDProtectionExceeds6kV

3.3-VSupplyOperation128-PinTQFPPackage

ROHSCompatibleand260°CReflowRated

APPLICATIONS

DigitalTV

DigitalProjector

AudioVideoReceiverDVIorHDMISwitch

DESCRIPTION

TheTMDS442,4-to-2portDVI/HDMIswitch,allowsupto4digitalvideointerface(DVI)orhigh-definitionmultimediainterface(HDMI)portstobeswitchedtotwoindependentdisplayblocks.Theessentialrequirementofpicture-in-picturedisplayfromtwodigitalaudiovisualsourcesishavingtwoindividualDVIorHDMIreceiversinadigitaldisplaysystem.TMDS442supportstwoDVIorHDMIreceiverstoenablemultiple-sourceselection(picture-in-picture),aswellassupportsactingasa4-input1-outputvideoswitch.

Eachinputoroutputportcontainsone5-Vpowerindicator(5V_PWR),onehotplugdetector(HPD),apairofI2Cinterfacesignals(SCL/SDA),andfourTMDSchannelssupportingdataratesupto2.25Gbps.The5-Vpowerindicatorandthehotplugdetectorarepulleddownwithinternalresistors,forcingalowstateonthesepinsuntilreceivingavalidhighsignal.TheI2CinterfaceisconstructedbyanI2Crepeatercircuittoisolatethecapacitanceformbothendsofthebuses.TMDSreceiversintegrate50- terminationresistorspulleduptoVCC,whicheliminatestheneedforexternalterminations.An8-dBinputequalizationcooperatestoeachTMDSreceiverinputstooptimizesystemperformancethrough5-meterorlongerDVIorHDMIcompliantcables.

TYPICALAPPLICATION

Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.

PowerPADisatrademarkofTexasInstruments.

PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.

Copyright©2006–2007,TexasInstrumentsIncorporated

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TMDS442

SLLS757A–AUGUST2006–REVISEDMARCH2007

AprecisionresistorisconnectedexternallyfromtheVSADJpintoground,forsettingthedifferentialoutputvoltagetobecompliantwiththeTMDSstandardforallTMDSdriveroutputs.ThePREpincontrolstheTMDSoutputtobeoperatedundereitherastandardTMDSmodeoranACde-emphasismode.WhenPRE=high,a3-dBACde-emphasisTMDSoutputswingisselectedtopre-conditiontheoutputsignalstoovercomesignalimpairmentsthatmayexistbetweentheoutputoftheTMDS442andtheHDMIreceiverplacedataremotelocation.

EachsinkoutputportcanbeconfiguredwiththeSA,SB,I2CEN,andPREpins.SA1,SB1,I2CEN1,andPRE1regulatethebehaviourofsinkport1;SA2,SB2,I2CEN2,andPRE2regulatethebehaviourofsinkport2.Thesecontrolsignalsarehard-wirecontrolledbyGPIOinterface,orthroughalocalI2Cinterface.WhenGE=low,theconfigurationsaredonethroughalocalI2Cinterface,LC_SCL,LC_SDA,LC_A0,andLC_A1pins,andthe5V_ENcanbeprogrammedthroughthelocalI2Cinterface.Itisdefaulthighafterdevicepoweredon.WhenGE=high,theconfigurationsaredonethroughGPIOpinsregardlessthevalueofthe5V_ENintheinternalI2Cregisters.

Thetwobitsourceselectorpins,SAandSB,determinethesourcetransferredtothesinkport.TheinternalmultiplexerinterconnectstheTMDSchannelsandI2Cinterfacefromtheselectedsourceporttothesinkport.TheHPDoutputoftheselectedsourceportfollowsthestatusoftheHPD_SINK.Sincetwoofthesourceportswillalwaysbeunconnectedtoanyoutput,theI2CinterfacesofunselectedportsareisolatedandtheHPDoutputsofanunselectedportarepulledlow.

TheTMDSoutputsofeachofthesinkportsareenabledbasedonthesignaland5V_PWRsignal(fromtheselectedsourceport).Whenislow,foranoutputport,andthe5V_PWRsignalfromtheselectedsourceportishigh,theTMDSoutputsignalsareenabled;otherwisetheyaredisabled,andhighimpedance.

TheI2Cdriveratsinkside,SCL_SINKandSDA_SINK,areenabledbysettingI2CENhigh.WhenI2CENislow,theI2CdrivercannotforwardalowstatetotheI2Cbusconnectedatthesinkport.Ahardwireoutputvoltageselectpin,OVS,allowsadjustableoutputvoltageleveltoSCL_SINKandSDA_SINKtooptimisenoisemarginswhileinterfacingtodifferentHDMIreceivers.TheI2Cdriverofeachsourceport,SCLandSDA,iscontrolledbyits5V_PWRsignal.Avalid5-Vsignalappearingattheinputof5V_PWRenablestheI2Cdriverofthesourceport.

Thedeviceispackagedina128-pinPowerPADTQFPpackageandcharacterizedforoperationfrom0°Cto70°C.

Thesedeviceshavelimitedbuilt-inESDprotection.TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.

2

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TMDS442

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FUNCTIONALBLOCKDIAGRAM

A14B14A13B13A12B12A11B11

A24B24A23B23A22B22A21B21

Y14Z14Y13Z13Y12Z12Y11Z11

A34B34A33B33A32B32A31B31

Y24Z24Y23Z23Y22Z22Y21Z21

A44B44A43B43A42B42A41B41

LC_SCLLC_SDALC_A0LC_A1GE

HPD1HPD2HPD3HPD4SCL1SDA1SCL2SDA2SCL3SDA3SCL4SDA4

HPD_SINK1HPD_SINK2

5V_SINK15V_SINK2

SCL_SINK1SDA_SINK1SCL_SINK2SDA_SINK2

GPIO0 (SA1GPIO1 (SB1GPIO2 (/OE1GPIO3 (I2CEN1GPIO4 (PRE1GPIO5 (SA2GPIO6 (SB2GPIO7 (/OE2GPIO8 (I2CEN2GPIO9 (PRE2GPIO10 (SPOVS

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TMDS442

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PNPPACKAGE(TOPVIEW)

TERMINALFUNCTIONS

TERMINAL

NAME

A11,A12,A13,A14A21,A22,A23,A24A31,A32,A33,A34A41,A42,A43,A44B11,B12,B13,B14B21,B22,B23,B24B31,B32,B33,B34B41,B42,B43,B44Y11,Y12,Y13,Y14Y21,Y22,Y23,Y244

NO.8,11,14,17118,121,124,

127

100,103,106,

109

82,85,88,917,10,13,16117,120,123,

126

99,102,105,10881,84,87,9062,59,56,5343,40,37,34

I/O

DESCRIPTION

I

SourceSourceSourceSourceSourceSourceSourceSource

port1port2port3port4port1port2port3port4

TMDSTMDSTMDSTMDSTMDSTMDSTMDSTMDS

positivepositivepositivepositive

I

negativenegativenegativenegative

O

Sinkport1TMDSpositiveoutputsSinkport2TMDSpositiveoutputsSubmitDocumentationFeedback

inputsinputsinputsinputsinputsinputsinputsinputs

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TMDS442

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TERMINALFUNCTIONS(continued)

TERMINAL

NAME

Z11,Z12,Z13,Z14Z21,Z22,Z23,Z24SCL1SDA1SCL2SDA2SCL3SDA3SCL4SDA4SCL_SINK1SDA_SINK1SCL_SINK2SDA_SINK2HPD1HPD2HPD3HPD4HPD_SINK1HPD_SINK25V_PWR15V_PWR25V_PWR35V_PWR45V_SINK15V_SINK2LC_SCLLC_SDALC_A0LC_A1GEGPIO0GPIO1GPIO2GPIO3GPIO4GPIO5GPIO6GPIO7GPIO8GPIO9GPIO10GPIO11VSADJ

NO.63,60,57,5444,41,38,35

541151149796797865664647211294766849311395776748747372713120212223242526272829303251

1,9,15,1936,42,50,55,6169,75,83,89,93101,107,111,119,1256,12,18,33,39,45,52,58,6470,80,86,9298,104,110,116,122,128

I/OOIOIOIOIOIOIO

DESCRIPTION

Sinkport1TMDSnegativeoutputsSinkport2TMDSnegativeoutputsSourcePort1DDCI2CclocklineSourcePort1DDCI2CdatalineSourcePort2DDCI2CclocklineSourcePort2DDCI2CdatalineSourcePort3DDCI2CclocklineSourcePort3DDCI2CdatalineSourcePort4DDCI2CclocklineSourcePort4DDCI2CdatalineSinkport1DDCI2CclocklineSinkport1DDCI2CdatalineSinkport2DDCI2CclocklineSinkport2DDCI2CdatalineSourceSourceSourceSource

Port1Port2Port3Port4

hothothothot

plugplugplugplug

detectoroutputdetectoroutputdetectoroutputdetectoroutput

O

I

Sinkport1hotplugdetectorinputSinkport2hotplugdetectorinputSourceSourceSourceSource

Port1Port2Port3Port4

5-V5-V5-V5-V

powerpowerpowerpower

signalinputsignalinputsignalinputsignalinput

I

OIOII

SinkPort15-VpowerindicatoroutputSinkPort25-VpowerindicatoroutputLocalI2CclocklineLocalI2CdatalineLocalI2Caddressbit0LocalI2Caddressbit1

GPIOEnable

L:LocalI2Cpinsareactive,GPIOpinsarehighimpedanceH:GPIOpinsareactive,localI2CpinsarehighimpedanceSA1–Sinkport1sourceselectorSB1–Sinkport1sourceselector

–Sinkport1TMDSoutputenable

I2CEN1–Sinkport1DDCI2Coutputenable

PRE1–Sinkport1TMDSACde-emphasismodeselectorSA2–Sinkport2sourceselectorSB2–Sinkport2sourceselector

–Sinkport2TMDSoutputenable

I2CEN2–Sinkport2DDCI2Coutputenable

PRE2–Sinkport2TMDSACde-emphasismodeselectorSP–Sinkpriorityselector

OVS–SCL_SINK/SDA_SINKoutputvoltageselectTMDScompliantvoltageswingcontrol

I

I

I

VccPowersupply

GNDGround

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TMDS442

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EQUIVALENTINPUTANDOUTPUTSCHEMATICDIAGRAMS

TMDS Input Stage

TMDS Output Stage

A

WB

Z

Source-Side I2C Input/Output StageSink-Side I2C Input/Output Stage

Status Input StageVcc

SCLSDA5V_PWR

Control Input StageControl Input StageStatus Output Stage

GEGPIOLC_SCL

OVS

HPD

5V_SINK

ORDERINGINFORMATION(1)

PARTNUMBERTMDS442PNPTMDS442PNPR

(1)

PARTMARKING

TMDS442TMDS442

PACKAGE128-PINTQPF128-PINTQPFTape/Reel

Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,.

6

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ABSOLUTEMAXIMUMRATINGS

overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)

UNIT

VCCSupplyvoltagerange

Voltagerange

(2)

–0.5Vto4V

Aim*,Bim

Yjm,Zjm,,Vsadjj,HPDi,5V_SINKj,LC_SCL,LC_SDA,LC_A0,LC_A1,GE,GPIOSCLi,SCL_SINKj,SDAi,SDA_SINKj,HPD_SINKj,5V_PWRiHumanbodymodel(3)

Aim,BimAllpins

2.5Vto4V–0.5Vto4V–0.5Vto6V

±6kV±5kV±1500V±200VSeeDissipationRatingTable

Electrostaticdischarge

Charged-devicemodel(4)(allpins)Machinemodel

(5)

(allpins)

Continuouspowerdissipation(1)(2)(3)(4)(5)

Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratingsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.Allvoltagevalues,exceptdifferentialI/Obusvoltages,arewithrespecttonetworkgroundterminal.TestedinaccordancewithJEDECStandard22,TestMethodA114-BTestedinaccordancewithJEDECStandard22,TestMethodC101-ATestedinaccordancewithJEDECStandard22,TestMethodA115-A

DISSIPATIONRATINGS

PACKAGE128-TQFPPNP128-TQFPPNP(1)(2)(3)

PCBJEDECSTANDARD

Low-K(2)High-K(3)

TA≤25°C2129.47mW4308.48mW

DERATINGFACTORABOVETA=25°C

21.2947mW/°C43.0848mW/°C

(1)

TA=70°CPOWERRATING1171.20mW2369.66mW

Thisistheinverseofthejunction-to-ambientthermalresistancewhenboard-mountedandwithnoairflow.InaccordancewiththeLow-KthermalmetricdefinitionsofEIA/JESD51-3InaccordancewiththeHigh-KthermalmetricdefinitionsofEIA/JESD51-7

THERMALCHARACTERISTICS

overoperatingfree-airtemperaturerange(unlessotherwisenoted)

PARAMETER

RθJBRθJCPD

Junction-to-boardthermalresistanceJunction-to-casethermalresistanceDevicepowerdissipation

VIH=VCC,VIL=VCC-0.6V,RT=50 ,AVCC=3.3V,VCC=3.6V,RVSADJ=4.6k ,PRE=LoworhighAi/Bi(2:4)=1.65GbpsHDMIdatapattern,Ai/Bi(1)=165MHzclock

TESTCONDITIONS

MIN

TYPMAX7.8619.5

1431

UNIT°C/W°C/WmW

RECOMMENDEDOPERATINGCONDITIONS

MIN

VCCTAVICVIDRVSADJAVCCRT

Supplyvoltage

Operatingfree-airtemperatureInputcommonmodevoltage

Receiverpeak-to-peakdifferentialinputvoltageResistorforTMDScompliantvoltageswingrangeTMDSOutputterminationvoltage,seeFigure3Terminationresistance,seeFigure3Signalingrate

CONTROLPINS(LC_A0,LC_A1,GE,GPIO)VIH

LVTTLHigh-levelinputvoltage

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2

VCC

V

7

30

VCC–400

1504.63450

4.643.350NOM3.3

MAX3.670VCC+1015604.683.6552.25

UNITV°CmVmVp-pk V Gbps

TMDSDIFFERENTIALPINS(A/B)

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TMDS442

SLLS757A–AUGUST2006–REVISEDMARCH2007

RECOMMENDEDOPERATINGCONDITIONS(continued)

MIN

VILVIHVILVIHVILVIHVILVILCVIHVILVIHVIL(1)

LVTTLLow-levelinputvoltageLVTTLHigh-levelinputvoltageLVTTLLow-levelinputvoltageHigh-levelinputvoltageLow-levelinputvoltageHigh-levelinputvoltageLow-levelinputvoltage

Low-levelinputvoltagecontention(1)High-levelinputvoltageLow-levelinputvoltageHigh-levelinputvoltageLow-levelinputvoltage

GND

3-0.52GND0.7VCC

-0.5-0.52.1-0.50.7VCC

-0.5

CONTROLPINS(OVS)

3.60.55.30.85.50.3VCC

0.45.51.5VCC0.3VCC

VVVVVVVVVVV

NOM

MAX0.8

UNITV

STATUSPINS(HPD_SINK,5V_PWR)

DDCI/OPINS(SCL_SINK,SDA_SINK)

DDCI/OPINS(SCL,SDA)

LOCALI2CPINS(LC_SCL,LC_SDA)

VILspecificationisforthefirstlowlevelseenbytheSCL_SINK/SDA_SINKlines.VILCisforthesecondandsubsequentlowlevelsseenbytheSCL_SINK/SDA_SINKlines.

ELECTRICALCHARACTERISTICS

overrecommendedoperatingconditions(unlessotherwisenoted)

PARAMETER

ICC

Supplycurrent

TESTCONDITIONS

VIH=VCC,VIL=VCC–0.4V,RT=50 ,AVCC=3.3V,

Ai/Bi(2:4)=1.65-GbpsHDMIdatapattern,Ai/Bi(1)=165-MHzPixelclock

VIH=VCC,VIL=VCC–0.4V,RT=50 ,AVCC=3.3V,

Ai/Bi(2:4)=1.65-GbpsHDMIdatapattern,Ai/Bi(1)=165-MHzPixelclock

AVCC–10AVCC–600

SeeFigure4,AVCC=3.3V,RT=50

400MIN

TYP(1)

250

MAX412(2)

UNITmA

PDPowerdissipation6401344(2)mW

TMDSDIFFERENTIALPINS(A/B,Y/Z)VOHVOLVswingVOD(O)VOD(U) VOC(SS)I(O)OFFVOD(pp)VODE(SS)I(OS)VI(open)RINT

Single-endedhigh-leveloutputvoltageSingle-endedlow-leveloutputvoltageSingle-endedoutputswingvoltageOvershootofoutputdifferentialvoltageUndershootofoutputdifferentialvoltageChangeinsteady-statecommon-modeoutputvoltagebetweenlogicstatesSingle-endedstandbyoutputcurrentPeak-to-peakoutputdifferentialvoltageSteadystateoutputdifferentialvoltagewithde-emphasisShortcircuitoutputcurrent

Single-endedinputvoltageunderhighimpedanceinputoropeninputInputterminationresistance

0V≤VCC≤1.5V,

AVCC=3.3V,RT=50 SeeFigure5,PRE=High,AVCC=3.3V,RT=50 SeeFigure6II=10µAVIN=2.9V

PRE=LowPRE=High

–10800560-12-15VCC–10

45

50

AVCC+10AVCC–400

60015%25%51012008401215VCC+10

55

mVp-pmVmVmV2×Vswing2×Vswing

mVµA

mAmV

(1)(2)8

Alltypicalvaluesareat25°Candwitha3.3-Vsupply.Themaximumratingischaracterizedunder3.6VVCC.

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ELECTRICALCHARACTERISTICS(continued)

overrecommendedoperatingconditions(unlessotherwisenoted)

PARAMETER

STATUSPINS(HPD_SINK,5V_PWR)IIHIILVOHVOLIIHIILCI

High-leveldigitalinputcurrentLow-leveldigitalinputcurrentHigh-leveloutputvoltageLow-leveloutputvoltageHigh-leveldigitalinputcurrentLow-leveldigitalinputcurrentInputcapacitance

VIH=5.3VVIH=2VorVCCVIL=GNDor0.8VIOH=-4mAIOL=4mAVIH=2VorVCCVIL=GNDor0.8VVI=GNDorVCCVI=5.5VVI=VCCVO=3.6VVIL=GND

OVS=NC

VOL

Low-leveloutputvoltage

IOL=400µAor4mA

OVS=GNDOVS=VCCOVS=NC

VOL-VILC

Low-levelinputvoltagebelowoutputlow-levelvoltagelevel

Ensuredbydesign

OVS=GNDOVS=VCC

CIO

Input/outputcapacitance

VI=5.0Vor0V,Freq=100kHzVI=3.0Vor0V,Freq=100kHzVI=5.5VVI=VCCVO=3.6VVIL=GNDIOL=4mA

VI=5.0Vor0V,Freq=100kHzVI=3.0Vor0V,Freq=100kHz

-50-10-10-10-50-10-10-40470620775

70240420

2510

pFmV

-150-85-202.4GND-10-10

1508520VCC0.410101050101040620775950

VµAµAVVµAµApF

TESTCONDITIONS

MIN

TYP(1)

MAX

UNIT

STATUSPINS(HPD,5V_SINK)

CONTROLPINS(LC_A0,LC_A1,GE,GPIO)

DDCI/OPINS(SCL_SINK,SDA_SINK)IlkgIOHIIL

InputleakagecurrentHigh-leveloutputcurrentLow-levelinputcurrent

µAµAµA

DDCI/OPINS(SCL,SDA)ANDLOCALI2CPINS(LC_SCL,LC_SDA)IlkgIOHIILVOLCI

InputleakagecurrentHigh-leveloutputcurrentLow-levelinputcurrentLow-leveloutputvoltageInputcapacitance

501010100.22510

µAµAµAVpF

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SWITCHINGCHARACTERISTICS

overrecommendedoperatingconditions(unlessotherwisenoted)

PARAMETER

TMDSDIFFERENTIALPINS(Y/Z)tPLHtPHLtrtftsk(p)tsk(D)tsk(o)tsk(bb)tsk(pp)tentdistsxtjit(pp)tjit(pp)tjit(pp)tjit(pp)

Propagationdelaytime,low-to-high-leveloutputPropagationdelaytime,high-to-low-leveloutputDifferentialoutputsignalrisetime(20%-80%)Differentialoutputsignalfalltime(20%-80%)Pulseskew(|tPHL–tPLH|)(2)

Intra-pairdifferentialskew,seeFigure7Inter-pairchannel-to-channeloutputskew(3)Bank-to-bankskewPart-to-partskewEnabletimeDisabletimeTMDSSwitchtime

Peak-to-peakoutputjitterfromY/Z(1),residualjitterPeak-to-peakoutputjitterfromY/Z(2:4),residualjitterPeak-to-peakoutputjitterfromY/Z(1),residualjitterPeak-to-peakoutputjitterfromY/Z(2:4),residualjitter

SeeFigure9,Ai/Bi(1)=165-MHzclock,Ai/Bi(2:4)=1.65-GbpsHDMIpattern,PRE=low

Input:5m28AWGHDMIcable,Output:3-Inch8-miltracewidthSeeFigure9,Ai/Bi(1)=225-MHzclock,Ai/Bi(2:4)=2.25-GbpsHDMIpattern,PRE=low

Input:5m28AWGHDMIcable,Output:3-Inch8-miltracewidth

10481856

(4)

TESTCONDITIONSMIN2502508080

TYP(1)MAX8008002402405075150300120202030743371

UNITpspspspspspspspsnsnsnsnspspspsps

SeeFigure4,AVCC=3.3V,RT=50

SeeFigure8

CONTROLANDSTATUSPINS(HPD_SINK,HPD,5V_PWR,5V_SINK)tpd(HPD)tpd(5V)tsx(HPD)tsx(5V)tsx

PropagationdelaytimePropagationdelaytimeHPDSwitchtime5-VPowerswitchtimeDDCSwitchtime

Propagationdelaytime,low-to-high-leveloutputSCL_SINK/SDA_SINKtoSCL/SDAPropagationdelaytime,high-to-low-leveloutputSCL_SINK/SDA_SINKtoSCL/SDA

Propagationdelaytime,low-to-high-leveloutputSCL/SDAtoSCL_SINK/SDA_SINK

Propagationdelaytime,high-to-low-leveloutputSCL/SDAtoSCL_SINK/SDA_SINK

Outputsignalrisetime,SCL_SINK/SDA_SINKOutputsignalfalltime,SCL_SINK/SDA_SINKOutputsignalrisetime,SCL/SDAOutputsignalfalltime,SCL/SDAEnabletostartconditionEnableafterstopcondition

SeeFigure12

SeeFigure11,OVS=NCSeeFigure8

CL=10pF,CL(DDC)=100pF

151515151

nsnsnsnsµs

DDCI/OPINS(SCL,SCL_SINK,SDA,SDA_SINK)tPLHtPHLtPLHtPHLtrtftrtftsetthold

20435194355002079620100100

4591403511408007299972

nsnsnsnsnsnsnsnsnsns

(1)(2)(3)(4)

Alltypicalvaluesareat25°Candwitha3.3-Vsupply.

tsk(p)isthemagnitudeofthetimedifferencebetweentPLHandtPHLofaspecifiedterminal.

tsk(o)isthemagnitudeofthedifferenceinpropagationdelaytimesbetweenanyspecifiedterminalsofchannel2to4ofadevicewheninputsaretiedtogether.

tsk(pp)isthemagnitudeofthedifferenceinpropagationdelaytimesbetweenanyspecifiedterminalsofchannel2to4oftwodevices,orbetweenchannel1oftwodevices,whenbothdevicesoperatewiththesamesource,thesamesupplyvoltages,atthesametemperature,andhaveidenticalpackagesandtestcircuits.

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TIMINGCHARACTERISTICSFORLOCALI2CINTERFACE(LC_SCL,LC_SDA,LC_AO,LC_A1)

PARAMETER

fSCLtw(L)tw(H)trtftsu(1)th(1)t(buf)tsu(2)th(2)tsu(3)Cb(1)(1)

Clockfrequency,SCLClocklowperiod,SCLlowClockhighperiod,SCLhighRisetime,SCLandSDAFalltime,SCLandSDASetuptime,SDAtoSCLHoldtime,SCLtoSDA

BUSFreetimebetweenaSTOPandSTARTconditionSetuptime,SCLtostartconditionHoldtime,startconditiontoSCLSetuptime,SCLtostopconditionCapacitiveloadforeachbusline

25004.74.744

400

4.74

1000300

10001.30.60.60.6

400

STANDARDMODE

MIN

MAX100

1.30.6

300300

FASTMODEMIN

MAX400

UNITkHzµsµsµsµsµsµsµsµsµsµspF

CbisthetotalcapacitanceofonebuslineinpF.

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PARAMETERMEASUREMENTINFORMATION

SCL

SDA

A.

trandtfaremeasuredat20%-80%referedtoVIHminandVILmaxlevels.

Figure1.SCLandSDATiming

SCL

SDA

Figure2.StartandStopConditions

Figure3.TypicalTerminationforTMDSOutputDriver

12

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PARAMETERMEASUREMENTINFORMATION(continued)

VccAVcc

DC CoupledVccAC CoupledVcc+0.2 V

Vcc 0.4 V0.4 V0 V100%

Vcc 0.2 V

VOC(SS)

NOTE:PRE=low.Allinputpulsesaresuppliedbyageneratorhavingthefollowingcharacteristics:trortf<100ps,100

MHzfromAgilent81250.CLincludesinstrumentationandfixturecapacitancewithin0.06moftheD.U.T.Measurementequipmentprovidesabandwidthof20GHzminimum.

Figure4.TMDSTimingTestCircuitandDefinitions

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PARAMETERMEASUREMENTINFORMATION(continued)

Figure5.De-EmphasisOutputVoltageWaveformsandDurationMeasurementDefinitions

0 V or 3.6 V

Figure6.ShortCircuitOutputCurrentTestCircuit

VY

VOH

VZ

VOL

Figure7.DefinitionofIntra-PairDifferentialSkew

14

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TMDS442

SLLS757A–AUGUST2006–REVISEDMARCH2007

PARAMETERMEASUREMENTINFORMATION(continued)

Input-1

kept HIGHInput-2kept LOW

SA

SBOutput

/OE

Figure8.TMDSOutputsControlTimingDefinitions

TTP1TTP2TTP3TTP4

A.B.C.

AlljittersaremeasuredinBERof10-12

TheresidualjitterreflectsthetotaljittermeasuredattheTMDS442output,TP3,subtractthetotaljitterfromthesignalgenerator,TP1

Theinputcablelengthandtheoutputtransmissionmediaarespecifiedinthetestconditions.

Figure9.JitterTestCircuit

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PARAMETERMEASUREMENTINFORMATION(continued)

SASB

5V_SINK

HPD1

HPD2

HPD3HPD4SDA1

SDA2

Figure10.PostSwitchTimingDefinitions

16

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PARAMETERMEASUREMENTINFORMATION(continued)

Vcc

0.1V

3.3V10%

1.5VVOLVcc

1.5V0.1V5V10%

Vcc/2VOL

SCL_SINK/SDA_SINKInput

5V10%

SCL/SDA

Output

Vcc/2

Figure11.I2CTimingTestCircuitandDefinition

START

STOP

5V

SCL

0V5VVCC/20V

SDA

VCC

1.5V0V

VCC

I2CEN

0V

Figure12.I2CSetupandHoldDefinition

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TYPICALCHARACTERISTICS

SUPPLYCURRENT

vs

FREQUENCY

325

SUPPLYCURRENT

vs

FREE-AIRTEMPERATURE

ICC- Supply Current - mA

ICC- Supply Current - mA

320315

310

305

300

2002504506507508501050125014501650

Signaling Rates - Mbps

010203040506070

TA- Free-Air Temperature - ºC

Figure13.

RESIDUALPEAK-TO-PEAKJITTER

vs

DATARATE

(DCCoupledInput:5mCable,Output:1mCable)

20

20

Figure14.

RESIDUALPEAK-TO-PEAKJITTER

vs

DATARATE

(DCCoupledInput:5mCable,Output:0mCable)

Residual Peak-Peak Jitter

- % of Tbit

Residual Peak-Peak Jitter - % of Tbi

t

181614121086420

750

1450

1650

1850

2250

Data Rate - Mbps181614121086420

Data Rate - Mbps

Figure15.Figure16.

18

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TYPICALCHARACTERISTICS(continued)

RESIDUALPEAK-TO-PEAKJITTER

vs

DATARATE

(ACCoupledInput:3mCable,Output:1mCable)

2018

2018

RESIDUALPEAK-TO-PEAKJITTER

vs

DATARATE

(ACCoupledInput:3mCable,Output:0mCable)

Residual Peak-Peak Jitter - % of Tbit

1614121086420

750

1450

1650

1850

2250

Data Rate - Mbps

Residual Peak-Peak Jitter - % of Tbit

1614121086420

750

145016501850

Data Rate - Mbps

2250

Figure17.

RESIDUALPEAK-TO-PEAKJITTER

vs

8-MILFR4TRACEOUTPUT(DCCoupledInput:5mCable)

Figure18.

RESIDUALPEAK-TO-PEAKJITTER

vs

PEAK-TO-PEAKDIFFERENTIALINPUTVOLTAGE

(atTTP1,DCCoupled:5mCable)

28

Residual Peak-Peak Jitter - % of Tbit

Residual Peak-Peak Jitter - % of Tbit

22101003005007009001100130015001700Peak-to-Peak Differential Input Voltage - mVp-p

4

81216

8-mil FR4 Trace Length - inch

Figure19.Figure20.

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TYPICALCHARACTERISTICS(continued)

OUTPUTINTRA-PAIRSKEW

vs

INPUTINTRA-PAIRSKEW

(DCCoupledInput:0m,Output:0m)

30

25

Output Intra-Pair Skew - ps

20

15

10

5

0.080.16

0.240.320.40.480.56Input Intra-Pair Skew - Tbit

0.64

Figure21.

20

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TYPICALCHARACTERISTICS(continued)

Eye Pattern

@TP1

CableA1mData

@TP2

@TP3 PRE=LOW @TP4 PRE=HIGH

Cable B

1m

Clock

5mData1m

Clock

Figure22.EyePatternsat148.5-MHzPixelClock

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