quartus Ⅱ 10.0软件使用手册

quartus Ⅱ 10.0 软件

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Quartus II Design Software

quartus Ⅱ 10.0 软件

Fast Path to Your Design

Quartus® II soft ware is #1 in performance and productivity for CPLD, FPGA, and ASIC designs, providing the fastest path to convert your concept into reality.

Quartus II Key Features

Faster Compile

Time

Incremental-Compile

PowerPlayPower AnalyzerTimeQuestTiming Analyzer

SOPC Builder

System Development

Industry-Leading Compile Time

Superior synthesis and placement and routing results in compile time advantage Other subscription-only, compile time reduction features include:– Multiprocessor support– Rapid Recompile– Incremental compile

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quartus Ⅱ 10.0 软件

Compile Time Comparison

e

m90%

iT e80%lipm70%oC60% vei50%taleR40%30%20%

4.0

4.1

4.2

5.0

5.1

6.0

6.1

7.1

7.2

8.0

8.1

9.0

9.1

10.0

10.1

2004Quartus II Version2010

*Benchmark data points are net of computing speed improvements

Compare Full and Incremental Compile

Full Compile

Incremental CompileTop-Down Approach

Create Design Partitions (A, B, C)

Quartus II Project

Step 1

Quartus II Project(No Partitions)

Step 1

A

B

C

Modify Design (In Red)Modify Design in Partition ARe-Compile Whole Project Re-Compile—Only Partition A

Quartus II Project

Step 2

Quartus II Project(No Partitions)

Step 2

ABC

Incremental Compile

Compiles only the changes in a partition to reduce compile time by up to 70 percent Preserves timing in unchanged partitions for performance preservation Enables team-based designs

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quartus Ⅱ 10.0 软件

TimeQuest Timing Analyzer

TimeQuest Timing Analyzer GUI

Th e only FPGA vendor with comprehensive Synopsis Design Constraints (SDC) support Second-generation, easy-to-use timing analyzer

Complete GUI environment and scripting support to create timing constraints and reports

Easy-to-use wizard to create SDC constraints

PowerPlay Power Analyzer Flow

PowerPlay Power Analyzer

Push-button power optimization technology Automated power optimization for an average 10 percent reduction in power consumption

4 Quartus II Design Software 2010

quartus Ⅱ 10.0 软件

SOPC Builder System Development Tool

Automates intellectual property (IP) connectivity and HDL generation Raises the level of abstraction and increases productivity

SOPC Builder

Clock 1

Clock 2

SOPC Builder Auto-Generated Interconnect

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quartus Ⅱ 10.0 软件

Quartus II Design Flow

12

Lowest density devices for Arria II and Stratix series FPGAs may be included in Web EditionAvailable with talkback feature enabled in Web Edition

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quartus Ⅱ 10.0 软件

Quartus II Ordering

Purchase Quartus II software and increase your productivity today.

Want to Dig Deeper?

Are you ready to accelerate your design process? Take these steps to gain profi ciency in designing with Quartus II soft ware: 1) Download free Web Edition or 30-day Subscription Edition trial; 2) Get oriented with the Quartus II Soft ware Interactive Tutorial; and 3) Sign up for training.

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Altera Corporation

Altera European Headquarters

Altera Japan Ltd.

Altera International Ltd.

101 Innovation DriveHolmers Farm WayShinjuku i-Land Tower 32FUnit 11-18, 9/F

San Jose, CA 95134High Wycombe6-5-1, Nishi-Shinjuku

Millennium City 1, Tower 1USA

BuckinghamshireShinjuku-ku, Tokyo 163-1332388 Kwun Tong

HP12 4XF

Japan

Kwun Tong

United Kingdom

Telephone: (81) 3 3340 9480Kowloon, Hong Kong

Telephone: (44) 1494 602000

www.altera.co.jp

Telephone: (852) 2945 7000

Copyright © 2010 Altera Corporation. All rights reserved. Altera, the stylized Altera logo, specifi c device designations, and all other words and logos that are identifi ed as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. July 2010; PDF GB-01010-1.0

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