USB3.1 Type C 认证规范 USB-Port Controller Specification R1.0 21051020(1) - 图文

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Release 1.0

October 20, 2015 - 1 - USB Type-C Port Controller

Interface Specification

Universal Serial Bus

Type-C Port Controller Interface Specification

Revision 1.0 October 20, 2015

Release 1.0

October 20, 2015 - 2 - USB Type-C Port Controller

Interface Specification

Hewlett-Packard Company, Intel Corporation, Microsoft Corporation,

Renesas, STMicroelectronics, and Texas Instruments

LIMITED COPYRIGHT LICENSE: The USB 3.0 Promoters grant a conditional copyright license under the copyrights embodied in the USB Type-C Cable and Connector Specification to use and reproduce the Specification for the sole purpose of, and solely to the extent necessary for, evaluating whether to implement the Specification in products that would comply with the specification. Without limiting the foregoing, use of the Specification for the purpose of filing or modifying any patent application to target the Specification or USB compliant products is not authorized. Except for this express copyright license, no other rights or licenses are granted, including without limitation any patent licenses. In order to obtain any additional intellectual property licenses or licensing commitments associated with the Specification a party must execute the USB 3.0 Adopters Agreement. NOTE: By using the Specification, you accept these license terms on your own behalf and, in the case where you are doing this as an employee, on behalf of your employer.

INTELLECTUAL PROPERTY DISCLAIMER

THIS SPECIFICATION IS PROVIDED TO YOU “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO USE OR IMPLEMENTATION OF INFORMATION IN THIS SPECIFICATION. THE PROVISION OF THIS SPECIFICATION TO YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS.

All implementation examples and reference designs contained within this Specification are included as part of the limited patent license for those companies that execute the USB 3.0 Adopters Agreement.

All product names are trademarks, registered trademarks, or service marks of their respective owners.

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October 20, 2015 - 3 - CONTENTS

USB Type-C Port Controller

Interface Specification

Specification Work Group Chairs / Specification Editors ...................................................... 7 Specification Work Group Contributors ...................................................................................... 7 Revision History .................................................................................................................................. 9 1

Introduction ............................................................................................................................... 10 1.1 1.2 1.3 1.4

Purpose ............................................................................................................................ 10 Scope ................................................................................................................................. 10 Related Documents....................................................................................................... 11 Conventions .................................................................................................................... 11 1.4.1 Precedence ...................................................................................................... 11 1.4.2 Keywords ......................................................................................................... 11 1.4.3 Numbering ....................................................................................................... 12 1.5 Terms and Abbreviations ........................................................................................... 12 Overview ..................................................................................................................................... 13 2.1 Introduction ................................................................................................................... 13 2.2 USB Type-C Port Controller (TCPC) Interface ...................................................... 13 Type-C Port Controller Requirements ............................................................................... 14 3.1 3.2 3.3 3.4 3.5 3.6

Port Power Control for VBUS and VCONN ............................................................. 14 USB CC Logic ................................................................................................................... 14 USB-PD Message Delivery .......................................................................................... 14 Debug Accessory Detection ....................................................................................... 15 TCPC State-Machines ................................................................................................... 16 USB Type-C Port Controller Requirements for Source, Sink, and DRP ......... 18 3.6.1 Source Requirements ................................................................................... 18 3.6.2 Sink Requirements: ....................................................................................... 19 3.6.3 Sink with Accessory Support ..................................................................... 20 3.6.4 DRP Requirements ........................................................................................ 21 USB Type-C Port Controller Interface ................................................................................ 22 4.1 4.2 4.3

Register Map .................................................................................................................. 23 TCPC SMBus Optional Normative Requirements ................................................ 25 Writing and Reading TCPC Registers ...................................................................... 25 4.3.1 Writing Single Byte Registers .................................................................... 25 4.3.2 Reading Single Byte Registers ................................................................... 26 4.3.3 Writing Multiple-Byte Registers ............................................................... 26 4.3.4 Reading Multiple-Byte Registers .............................................................. 27 4.3.5 Writing the TRANSMIT_BUFFER ............................................................... 27 4.3.6 Reading the RECEIVE_BUFFER .................................................................. 28 Register Definition ....................................................................................................... 29 4.4.1 Identification Registers ............................................................................... 29 4.4.2 ALERT Register (Required) ........................................................................ 31 4.4.3 Mask Registers ............................................................................................... 33 4.4.4 CONFIGURE STANDARD OUTPUT (Optional Normative) .................. 36

4.4

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4.4.5 Control and Configuration Registers ....................................................... 37 4.4.6 Status Registers ............................................................................................. 43 4.4.7 COMMAND (Required) ................................................................................. 49 4.4.8 Capability Registers ...................................................................................... 52 4.4.9 MESSAGE_HEADER_INFO (Required) ...................................................... 56 4.4.10 RECEIVE_DETECT (Required).................................................................... 56 4.4.11 RECEIVE_BUFFER (Required) .................................................................... 57 4.4.12 TRANSMIT (Required) ................................................................................. 59 4.4.13 TRANSMIT_BUFFER (Required) ................................................................ 60 4.4.14 VBUS_VOLTAGE (Optional Normative) ................................................... 61 4.4.15 Voltage Thresholds ....................................................................................... 62 4.4.16 VENDOR_DEFINED Registers ..................................................................... 64 4.5 STANDARD IO SIGNALS .............................................................................................. 65

4.5.1 STANDARD INPUT SIGNALS (Optional Normative) ............................ 65 4.5.2 STANDARD OUTPUT SIGNALS (Optional Normative except

Alert#) .............................................................................................................. 65

4.6 TCPC Connection State Machine and Flows .......................................................... 67 4.7 PD Communication Operational Model .................................................................. 73

4.7.1 Transmitting an SOP* Message ................................................................. 73 4.7.2 Transmitting a Hard Reset Message ........................................................ 73 4.7.3 Receiving an SOP* message ........................................................................ 73 4.7.4 Receiving a Hard Reset message ............................................................... 74 4.8 Power Management ...................................................................................................... 75

4.8.1 I2C Interface ................................................................................................... 75 4.8.2 PD Messaging .................................................................................................. 75 4.8.3 CC Status Reporting ...................................................................................... 75 4.8.4 VBUS Reporting ............................................................................................... 76 4.8.5 Fault Status Reporting ................................................................................. 76 4.9 TCPC Timing Constraints ............................................................................................ 78 4.10 I2C Physical Interface Specifications ...................................................................... 78 Informative TCPM State-Machine Diagrams .................................................................... 81

FIGURES

Figure 1-1. USB Type-C Port Manager to USB Type-C Port Controller Interface ............................................ 10 Figure 2-1. TCPC Interface....................................................................................................................................................... 13 Figure 3-1. Rx State-Machine Implemented in TCPC ................................................................................................... 16 Figure 3-2. Tx State-Machine Implemented in TCPC ................................................................................................... 17 Figure 3-3. Hard Reset Transmission State-Machine implemented in the TCPC ............................................ 17 Figure 4-1. Writing Consecutive Registers with or without the SMBUS Protocol .......................................... 25 Figure 4-2. Reading Consecutive Registers with or without the SMBus Protocol .......................................... 26 Figure 4-3. Writing a 2-Byte Register with or without the SMBus Protocol ..................................................... 26 Figure 4-4. Reading a 2-Byte Register with or without the SMBus Protocol .................................................... 27 Figure 4-5. Writing the TRANSMIT_BUFFER with or without the SMBus Protocol ...................................... 27 Figure 4-6. Reading the RECEIVE_BUFFER with or without the SMBus Protocol .......................................... 28 Figure 4-7. Automatic VBUS Sink Discharge by the TCPC after a Disconnect .................................................... 43 Figure 4-8. Transition from vSafe5V to High Voltage ................................................................................................. 51

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Figure 4-9. Transition from High Voltage to vSafe5V ................................................................................................. 51 Figure 4-10. TCPC Power-On State Machine ................................................................................................................... 67 Figure 4-11. TCPC State Machine before a Connection .............................................................................................. 68 Figure 4-12. TCPC State Machine After a Connection ................................................................................................. 69 Figure 4-13. TCPC State Machine Debug Accessory ..................................................................................................... 69 Figure 4-14. DRP Initialization and Connection Detection ....................................................................................... 70 Figure 4-15. Source Disconnect ............................................................................................................................................ 71 Figure 4-16. Sink Disconnect .................................................................................................................................................. 72 Figure A-1. Rx State Machine Implemented in TCPM .................................................................................................. 81 Figure A-2. Tx State Machine Implemented in TCPM .................................................................................................. 81 Figure A-3. Hard Reset State Machine Implemented in TCPM ................................................................................ 82

TABLES

Table 4-1. Register Map ............................................................................................................................................................ 23 Table 4-2. VENDOR_ID Register Definition ...................................................................................................................... 29 Table 4-3. PRODUCT_ID Register Definition ................................................................................................................... 29 Table 4-4. DEVICE_ID Register Definition ........................................................................................................................ 29 Table 4-5. USBTYPEC_REV Register Definition (Required)...................................................................................... 29 Table 4-6. USBPD_REV_VER Register Description ........................................................................................................ 30 Table 4-7. PD_INTERFACE_REV Register Description ................................................................................................ 30 Table 4-8. ALERT Register Definition................................................................................................................................. 31 Table 4-9. ALERT_MASK Register Definition .................................................................................................................. 33 Table 4-10. POWER_STATUS_MASK Register Definition ........................................................................................... 34 Table 4-11. FAULT_STATUS_MASK Register Definition ............................................................................................. 35 Table 4-12. CONFIG_STANDARD_OUTPUT Register Definition .............................................................................. 36 Table 4-13. TCPC_Control Register Definition................................................................................................................ 37 Table 4-14. ROLE_CONTROL Register Definition .......................................................................................................... 38 Table 4-15. Power on Default Conditions ......................................................................................................................... 39 Table 4-16. FAULT_CONTROL Register Definition ....................................................................................................... 39 Table 4-17. POWER_CONTROL Register Definition ..................................................................................................... 40 Table 4-18. Discharge Timing Parameters ....................................................................................................................... 41 Table 4-19. Debounce requirements .................................................................................................................................. 44 Table 4-20. CC_STATUS Register Definition .................................................................................................................... 44 Table 4-21. POWER_STATUS Register Definition ......................................................................................................... 46 Table 4-22. FAULT_STATUS Register Definition ........................................................................................................... 47 Table 4-23. COMMAND Register Definition ..................................................................................................................... 50 Table 4-24. DEVICE_CAPABILITIES_1 Register Definition........................................................................................ 52 Table 4-25. DEVICE_CAPABILITIES_2 Register Definition........................................................................................ 53 Table 4-26. STANDARD_INPUT_CAPABILITIES Register Definition .................................................................... 54 Table 4-27. STANDARD_OUTPUT_CAPABILITIES Register Definition ................................................................ 54 Table 4-28. MESSAGE_HEADER_INFO Register Definition ....................................................................................... 56 Table 4-29. RECEIVE_DETECT Register Definition ...................................................................................................... 56 Table 4-30. RECEIVE_BYTE_COUNT Definition ............................................................................................................. 57 Table 4-31. RX_BUF_FRAME_TYPE Definition ................................................................................................................ 57 Table 4-32. RX_BUF_HEADER Definition .......................................................................................................................... 58 Table 4-33. RX_BUFFER_DATA_OBJECTS Definition ................................................................................................... 58 Table 4-34. TRANSMIT Register Definition ..................................................................................................................... 59 Table 4-35. TRANSMIT_BYTE_COUNT Definition ......................................................................................................... 60 Table 4-36. TX_BUF_HEADER Definition .......................................................................................................................... 60 Table 4-37. TX_BUFFER_DATA_OBJECTS Definition ................................................................................................... 60 Table 4-38. VBUS_VOLTAGE Register Definition .......................................................................................................... 61 Table 4-39. VBUS_SINK_DISCONNECT_THRESHOLD Register Description ...................................................... 62 Table 4-40. VBUS_STOP_DISCHARGE_THRESHOLD Register Description ........................................................ 62

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Table 4-41. VBUS_VOLTAGE_ALARM_HI_CFG Register Description .................................................................... 63 Table 4-42. VBUS_VOLTAGE_ALARM_LO_CFG Register Description ................................................................... 63 Table 4-43. Standard Input Signals ..................................................................................................................................... 65 Table 4-44. Standard Output Signals .................................................................................................................................. 65 Table 4-45. TCPC Timing Constraints ................................................................................................................................ 78 Table 4-46. I2C Static Characteristics ................................................................................................................................. 79 Table 4-47. I2C Dynamic Characteristics .......................................................................................................................... 79

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Specification Work Group Chairs / Specification Editors

Intel Corporation (USB 3.0 Promoter company)

Christine Krause – Subgroup WG co-chair, Specification Co-author Chee Lim Nge – Subgroup WG co-chair, Specification Co-author

Specification Work Group Contributors

Advanced Micro Devices Analogix Semiconductor, Inc. Apple

Will Harris Jason Hawken Greg Stewart Sree Anantharaman William Ferry

Arulchandran Paramasivam

Cadence Design Systems, Inc. Canova Tech

Cypress Semiconductor Dell Inc.

DisplayLink (UK) Ltd. Ellisys

Etron Technology, Inc. Fairchild Semiconductor Fresco Logic Inc. Google Inc.

Jacek Duda Pawel Eichler Matteo Casalin Anup Nayak Jagadeesan Raj Mohammed hijazi Marcin Nowak Pete Burgers Dan Ellis Mario Pasquali Shihmin Hsu Oscar Freitas Tim Barilovits Alec Berg Jim Guerin Mark Hayter

Granite River Labs Hewlett Packard Intel Corporation

Mike Engbretson Roger Benson Bob Dunstan Abdul Ismail Sanjeev Jahagirdar

Keysight Technologies Inc. Lattice Semiconductor Corp

MCCI Corporation Microchip Technology Inc.

Jit Lim Young Il Kim Terry Moore Josh Averyt Mark Bohm Shannon Cash

Microsoft Corporation

Randy Aull Anthony Chen Vivek Gupta David Hargrove

Davide Ghedin Subu Sankaran Ganesh Subramaniam Siddhartha Reddy Merle Wood Kevin Jacobs Richard Petrie Chuck Trefts Chien-Cheng Kuo Christian Klein Bob McVay Sameer Nanda Vincent Palatin David Schneider

Robin Castell Vijaykumar Kadgi Henrik Leegaard Tim McKee

Thomas Watzka Sherri Russo Brian Marley Santosh shettty John Sisto Robbie Harris Teemu Helenius Kai Inha Jayson Kastens

Ismo Manninen Rahul Ramadas Nathan Sherman Tatu Tomppo

Chris Yokum Richard Wahler Neil Winchester

Brad Saunders Karthi Vadivelu

Erik Maier Jeffrey Yang Scott Collyer

Jason Young

Nicola Scantamburlo

Joseph Scanlon Peter Teng

Reese Schreiber David Sekowski Sascha Tietz Wojciech Kloska

Michal Staworko

Hsiao-Ping Jennifer Tsai Ken Xue

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October 20, 2015

MQP Electronics Ltd. NXP Semiconductors ON Semiconductor Parade Technologies, Inc. Qualcomm, Inc Realtek Semiconductor Corp.

Renesas Electronics Corp. Richtek Technology Corporation

Sten Carlsen Ken Jaramillo Abhijeet Kulkarni Bryan McCoy Jian Chen Craig Wiley Craig Aiken Charlie Hsu Ray Lee Kiichi Muto Kenny Chan HM Chang Patrick Change Bryan Huang

Ricoh Company Ltd. ROHM Co., Ltd. STMicroelectronics

Yasuyuki Hayashi Tatsuya Irisawa Kris Bahar Ruben Balbuena Jér?me Bach Nathalie Ballot Christophe lorin

Synopsys, Inc. Texas Instruments VIA Technologies, Inc.

Zongyao Wen Felipe Balbi Jay Tseng

- 8 -

Pat Crowe

USB Type-C Port Controller

Interface Specification

Bart Vertenten

Changhung Wu

Scott Wu Alex Yang Ming-Shih Yu

Takashi Sato Legrand Pascal

Vijendra Kuroodi Krishnan TN Paul Xu Alan Yuen Shadi Hawawini Ryan Lin Terry Lin Hajime Nozaki Spice Huang Chunan Kuo Tony Lai Heinz Wei Satoshi Oie Yuuji Tsutsui Nobutaka Itakura Yoshinori Ohwaki Meriem Mersel Federico Musarra Richard O'Connor

Scott Jackson Fong-Jim Wang

Deric Waters

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Interface Specification

Revision History

Release 1.0

October 20, 2015

- 10 - OS Policy ManagerPD System Policy Manager (optional)USB Type-C Port Controller

Interface Specification

1 Introduction

With the continued success of USB Power Delivery, there exists a need to define a common

PPM Interfaceinterface from a USB Type-CTM Port Manager to a Simple USB Type-C Port Controller. This specification defines this interface.

Platform Policy Manager

Figure 1-1 shows the interconnection between the USB Type-C Port Manager, TCPM, and three PD Device Policy Manager (for PD-capable ports)USB Type-C Port Controllers, TCPCs. One TCPM may be used to drive multiple TCPCs subject

to the timing constraints defined in the USB PD Specification. The connection between the TCPM and the TCPC is defined as the USB Type-C Port Controller Interface, TCPCI. TCPM Interface Type-C Port ManagerPolicy EngineProtocol LayerI2C MasterTCPC Interface (TCPCI)I2C SlaveTx/Rx BufferGoodCRC / RetryPhysical LayerType-C CC LogicType-C Port ControllerI2C SlaveTx/Rx BufferGoodCRC / RetryPhysical LayerType-C CC LogicType-C Port ControllerI2C SlaveTx/Rx BufferGoodCRC / RetryPhysical LayerType-C CC LogicType-C Port Controller

Figure 1-1. USB Type-C Port Manager to USB Type-C Port Controller Interface

1.1 Purpose

The USB Type-C Port Controller Interface, TCPCI, is the interface between a USB Type-C Port Manager and a USB Type-C Port Controller. This specification standardizes the communication between the USB Type-C Port Manager (TCPM) and the USB Type-C Port Controller (TCPC) while meeting the USB Type-C Power Delivery requirements.

The goal of the USB Type-C Port Controller Interface (TCPCI) is to provide a defined interface between a TCPC and a TCPM in order to standardize and simplify USB Type-C Port Manager implementations.

The TCPC is a functional block which encapsulates VBUS and VCONN power controls, USB Type-C CC logic, and the USB PD BMC physical layer and protocol layer other than the message creation.

1.2 Scope

This specification is intended as a supplement to USB 3.1, USB Type-C, and USB PD

specifications. It addresses only the elements required to implement and support the USB Type-C Port Controller.

Normative information is provided to allow interoperability of components designed to this specification. Informative information, when provided, may illustrate possible design implementations.

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USB 3.1 Universal Serial Bus Revision 3.1 Specification

This includes the entire document release package. http://www.usb.org/developers/docs USB PD USB Type-C

1.4 Conventions 1.4.1 Precedence

If there is a conflict between text, figures, and tables, the precedence shall be tables, figures, and then text. 1.4.2 Keywords

The following keywords differentiate between the levels of requirements and options. 1.4.2.1 Informative

Informative is a keyword that describes information within this specification that intends to discuss and clarify requirements and features as opposed to mandating them. 1.4.2.2 May

May is a keyword that indicates a choice with no implied preference. 1.4.2.3 N/A

N/A is a keyword that indicates a field or value is not applicable and has no defined value and shall not be checked or used by the recipient. 1.4.2.4 Normative

Normative is a keyword that describes features mandated by this specification. 1.4.2.5 Optional

Optional is a keyword that describes features not mandated by this specification. However, if an optional feature is implemented, the feature shall be implemented as defined by this specification (optional normative). 1.4.2.6 Reserved

Reserved is a keyword indicating reserved bits, bytes, words, fields, and code values that are set-aside for future standardization. Their use and interpretation may be specified by future extensions to this specification and, unless otherwise stated, shall not be utilized or adapted by vendor implementation. A reserved bit, byte, word, or field shall be set to zero by the sender and shall be ignored by the receiver. Reserved field values shall not be sent by the sender, and if received, shall be ignored by the receiver.

USB Power Delivery Specification, Revision 2.0, August 11, 2014 http://www.usb.org/developers/docs

USB Type-C Connector Specification, Revision 1.0, August 11, 2014 http://www.usb.org/developers/docs

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Shall is a keyword indicating a mandatory (normative) requirement. Designers are mandated to implement all such requirements to ensure interoperability with other compliant Devices. 1.4.2.8 Should

Should is a keyword indicating flexibility of choice with a preferred alternative equivalent to the phrase “it is recommended that”. 1.4.3 Numbering

Numbers immediately followed by a lowercase “b” (e.g., 01b) are binary values. Numbers immediately followed by an uppercase “B” are byte values. Numbers immediately followed by a lowercase “h” (e.g., 3Ah) are hexadecimal values. Numbers not immediately followed by either a “b”, “B”, or “h” are decimal values. 1.5 Terms and Abbreviations

Term BMC LPM LPMI OPM PPM PPMI TCPC TCPCI TCPM Snk.Rp Snk.Open Src.Ra Src.Rd Src.Open OCP OVP vSafe0V vSafe5v Biphase Mark Coding Local Policy Manager Local Policy Manager Interface Operating System Policy Manager Platform Policy Manger Platform Policy Manager Interface USB Type-C Port Controller USB Type-C Port Controller Interface USB Type-C Port Manager Sink CC pin above minimum vRd-Connect, USB Type-C Sin CC pin below maximum vRa, USB Type-C Source CC pin above vOPEN, USB Type-C Source CC pin within the vRd range, USB Type-C Source CC pin below maximum vRa Over-current Protection Over-voltage Protection Safe operating voltage at “zero volts” per USB PD Safe operating voltage at 5V per USB PD Description Copyright ? 2015 USB 3.0 Promoter Group. All rights reserved.

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2 Overview

2.1 Introduction

2.2 USB Type-C Port Controller (TCPC) Interface

Local Policy ManagerType-C Port ManagerPolicy EngineProtocol LayerI2C MasterTCPC Interface (TCPCI)I2C SlaveTx/Rx BufferGoodCRC / RetryPhysical LayerType-C CC LogicType-C Port Controller

Figure 2-1. TCPC Interface

The USB Type-C Port Controller Interface, TCPCI, is the interface between a USB Type-C Port Manager and a USB Type-C Port Controller. The goal of the USB Type-C Port Controller Interface (TCPCI) is to provide a defined interface between a TCPC and a TCPM in order to standardize and simplify USB Type-C Port Manager implementations.

The TCPC is a functional block which encapsulates VBUS and VCONN power controls, USB Type-C CC logic, and the USB PD BMC physical layer and protocol layer other than the message creation. The TCPC shall NOT include support for USB PD BFSK.

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3 Type-C Port Controller Requirements

This chapter describes the requirements of a USB Type-C Port Controller. The TCPC has three functions:

? ? ? ?

USB Type-C Port Power Control for VBUS and VCONN (required) USB Type-C CC Control and sensing (required) USB PD Message delivery (required)

Standard Inputs and Outputs are defined for simplified external interfacing (optional)

The TCPC uses I2C to communicate with the TCPM. The TCPC is an I2C slave with Alert# signal for requesting attention.

3.1 Port Power Control for VBUS and VCONN

A Source capable TCPC shall provide a register which allows the TCPM to control VBUS Sourcing. A Sink capable TCPC shall provide a register which allows the TCPM to Control VBUS Sinking.

To ensure safety in case the I2C interface fails, the TCPC that is sourcing VBUS higher than 5V shall autonomously stop sourcing VBUS if the Sink is detached.

The TCPC shall implement a force discharge circuit. A low current bleed discharge may also be implemented. The force discharge is a larger current discharge used to discharge to

below vSafe0V upon detecting a Disconnect per USB Type-C (exiting the Attached.SRC state). The discharge shall be available for both Source and Sink.

A TCPC shall include monitoring for the presence of VBUS (VSafe5V, VSafe0V). The TCPC shall implement high and low voltage alarms if it Sinks or Sources voltage greater than VSafe5V. A Source or DRP TCPC shall include control for VCONN sourcing. A Sink TCPC shall include control for VCONN sourcing if VCONN Swap or Sink w/Accessory is supported. VCONN sourcing shall meet the tVCONNON and tVCONNOFF timing requirement per USB Type-C. A TCPC shall implement low power states as defined in this specification. 3.2 USB CC Logic

The TCPC shall implement logic for controlling the CC pins on the USB Type-C Connector. The TCPC shall implement a method to control the Port Power Role and to report the state of the CC lines, Rp/Rd control, and CC sense/debounce/interrupt. 3.3 USB-PD Message Delivery

The TCPC shall implement BMC encoding. The TCPC shall NOT include support for USB PD BFSK. The TCPC shall implement the portion of the Protocol layer in the USB PD specification as shown in Figure 3-2, and 3-3. The TCPC is opaque from a USB PD point of view. The TCPC sends and receives messages constructed in the TCPM and places them on the CC connections. The TCPC does not interpret the USB PD messages.

The TCPC shall implement the entire USB PD PHY layer with BMC encoding. The TCPC shall implement a portion of the Transmit state machine.

CRCReceiveTimer (PRL_Tx_wait_for_Phy_Response_state)

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RetryCounter (PRL_Tx_Check_RetryCounter State)

MessageID is not checked in the TCPC when a non-GoodCRC message is received. Retried messages that are received are passed to the TCPM via I2C

Received GoodCRC must match the transmitted MessageID and SOP type before it is considered valid

Two things allow the TCPM to track the MessageID even when asynchronous messages are received

o If ALERT.ReceiveSOP*MessageStatus is not cleared when the TCPM requests

a TRANSMIT then the I2C command is NAK’d or

TransmitSOP*MessageDiscarded bit in the ALERT register is asserted. o If a message is received before the TCPC has processed a transmit request, it

asserts the TransmitSOP*MessageDiscarded bit in the ALERT register.

BIST handling shall be as follows: Each incoming BIST message may be passed up to the policy engine as is any other incoming USB PD Message, or responded to with a GoodCRC without passing to the policy engine. The TCPC shall provide a mechanism to allow the policy engine to send a BIST Continuous Carrier Mode 2 message for tBistContMode.

3.4 Debug Accessory Detection

The TCPC may implement autonomous detection of the Debug Accessory State (vRd/vRd) per USB Type-C. This allows the TCPC to indicate a vRd/vRd connection without TCPM involvement, and indicates this via the DebugAccessoryConnected# output and

POWER_STATUS.DebugAccessoryConnected. The TCPC performs autonomous detection of the Debug Accessory state if TCPC_CONTROL.DebugAccessoryControl=0b. The TCPM may control entry to the Debug Accessory Detected state by setting TCPC_CONTROL.DebugAccessoryControl=1b.

The behavior in the Debug Accessory state is defined in USB Type-C in Appendix B.

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This section describes the normative State-Machines for the TCPC. The informative TCPM State-Machines can be found in Appendix A.

TCPC receives Hard reset | Cable reset StartPRL_Rx_Message_DiscardActions on entry:If Tx State-Machine active, discard transmission3 and assert ALERT.TxMessageDiscardedMessage received from PHY 2 PRL_Rx_Wait_for_PHY_messageActions on entry:UnexpectedGoodCRC receivedGoodCRC Message discarded bus Idle1Anything but unexpected GoodCRCPRL_Rx_Send_GoodCRCActions on entry:Send GoodCRC message to PHY(GoodCRC Transmission complete Or GoodCRC Message discarded bus Idle1)PRL_Rx_Report_SOP*Actions on entry:Update RECEIVE_BUFFER (ALERT.ReceiveSOP*Status asserted)1Figure 3-1. Rx State-Machine Implemented in TCPC

This transition is taken by the PHY when the GoodCRC message has been discarded due to CC being busy, and after CC becomes idle again (see USB-PD specification). Two alternate allowable transitions are shown.2 Messages do not include Hard Reset or Cable Reset signals or expected GoodCRC messages (GoodCRC messages are only expected after the TCPC PHY has received the tx message and the TCPC Tx state-machine is in the PRL_Tx_Wait_for_PHY_response state).3 The TCPC may not discard the transmission if the received message is a Ping message.

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PRL_Tx_Wait_for_Transmit_RequestActions on entry:Protocol Layer message reception in PRL_Rx_Message_Discard state | hard reset received| cable reset received.PRL_Tx_Reset_RetryCounterTRANSMIT[2:0]<101bActions on entry:writtenReset RetryCounterPRL_Tx_Construct_MessageActions on entry:Pass TRANSMIT_BYTE_COUNT bytes from TRANSMIT_HEADER_LOW, TRANSMIT_HEADER_HIGH, and TRANSMIT_DATA_OBJECTS to PHYPRL_Tx_Report_FailureActions on entry:Assert ALERT.TransmitSOP*MessageFailed(RetryCounter > nRetryCount)(RetryCounter ≤ nRetryCount)Message sent to PHYPRL_Tx_Check_RetryCounterActions on entry:If DFP or UFP increment and check RetryCounterPRL_Tx_Wait_for_PHY_responseCRCReceiveTimerTimeout |Message discarded bus Idle2Actions on entry:Initialize and run CRCReceiveTimer1 (TX_BUF_HEADER_BYTE_1 != RX_BUF_HEADER_BYTE_1 (MessageID mismatch) |GoodCRC Response from PHY layerTRANSMIT[2:0] != RX_BUF_FRAME_TYPE (SOP mismatch) )PRL_Tx_Match_MessageIDActions on entry:Match MessageIDCounter and response MessageIDPRL_Tx_Report_SuccessActions on entry:Assert ALERT.TransmitSOP*MessageSuccessfulElse (GoodCRC with MessageID & SOP match)1 The CRCReceiveTimer is only started after the PHY has sent the message. If the message is not sent due to a busy channel then the CRCReceiveTimer will not be started (see USB-PD Rev2.0 v1.1 Section 6.5.1).2 This indication is sent by the PHY Layer when a message has been discarded due to VBUS or CC being busy, and after VBUS or CC becomes idle again (see USB-PD REv2.0 v1.1 Section 5.8). The CRCReceiveTimer is not running in this case since no message has been sent.

Figure 3-2. Tx State-Machine Implemented in TCPC

PRL_HR_Construct_MessageTRANSMIT[2:0]=101b or 110bwrittenPRL_HR_FailureActions on entry:Instruct PHY to stop attempting to send Hard Reset or Cable Reset.Actions on entry:Start tHardResetComplete timerRequest PHY to send Hard Reset or Cable ResetPRL_HR_Wait_for_Hard_Reset_RequestActions on entry:tHardResetCompleteexpiresHard Reset or Cable Reset sentPRL_HR_ReportActions on entry:Assert ALERT.TransmitSuccessful and ALERT.TransmitSOP*MessageFailedPRL_HR_SuccessActions on entry:Stop tHardResetComplete timer

Figure 3-3. Hard Reset Transmission State-Machine implemented in the TCPC

Release 1.0

October 20, 2015

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Interface Specification

3.6 USB Type-C Port Controller Requirements for Source, Sink, and DRP 3.6.1 Source Requirements

A TCPC, which supports Source port operation, is defined as follow:

1. A Source TCPC shall provide control of VBUS source path (see Table 4-23. COMMAND

2. A Source TCPC may provide over voltage protection and over current protection

circuitry for the VBUS source path (see FAULT_STATUS.OCP/OVP and FAULT_CONTROL.OCP/OVP).

3. A Source TCPC shall provide control of a VCONN switch (see

POWER_CONTROL.VCONNPowerSupported and POWER_CONTROL.EnableVconn). 4. A Source TCPC may include monitoring for the presence of VCONN (see

POWER_STATUS.VCONNPresent). Name USB-PD VCONN Swap Power Role Swap Support USB-PD Support Optional Optional Optional CC CONTROL CC Detect Status Port Disable Roles Supported Required Required (Rp to zOpen) SRC (Rp default, 1.5A, 3A) indicated in DEVICE_CAPABILITIES_1.SourceResistorSupported SNK (Rd) Optional PORT POWER CONTROL Power Status Supply VCONN Sink VBUS Supply VBUS Dead Battery Required Required Optional Required Required in DRP (present Rd when no power) Not required for Source only Functionality

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October 20, 2015 3.6.2 Sink Requirements:

- 19 - USB Type-C Port Controller

Interface Specification

A TCPC, which supports Sink port operation, is defined as follow:

1. A Sink TCPC shall contain CC logic that implements a mechanism to present Rd in a

dead battery condition (see Table 4-15. Power on Default Conditions). 2. A Sink TCPC may include the monitoring of the presence of VCONN (see

POWER_CONTROL.VCONNPowerSupported and POWER_STATUS.VCONNPresent). 3. A Sink TCPC shall provide control of VBUS sink path (see COMMAND).

4. A Sink TCPC shall provide a mechanism for detecting a Disconnect if it is capable of

sinking a voltage greater than vSafe5V (see Section 4.4.15.1). 5. A Sink TCPC shall provide a mechanism for detecting vSafe0V.

Name USB-PD VCONN Swap Power Role Swap Support USB-PD Support Optional Optional Optional CC CONTROL CC Detect Status Port Disable Roles Supported Required Required (Rd to zOpen) SNK (Rd) Required SRC (Rp default, 1.5A, 3A) Optional PORT POWER CONTROL Power Status Supply VCONN Sink VBUS Supply VBUS Dead Battery Required Optional, but required if VCONN Swap supported Required Optional Required (present Rd when no power) Functionality

Release 1.0

October 20, 2015

3.6.3 Sink with Accessory Support

- 20 - USB Type-C Port Controller

Interface Specification

A TCPC, which supports Sink with Accessory Support operation, is defined as follow:

1. A Sink TCPC shall contain CC logic that implements a mechanism to present Rd in a

dead battery condition (see Table 4-15. Power on Default Conditions). 2. A Sink TCPC shall provide control of VCONN source path (see

POWER_CONTROL.VCONNPowerSupported and POWER_CONTROL.EnableVCONN). 3. A Sink TCPC may include the monitoring of the presence of VCONN (see

POWER_STATUS.VCONNPresent).

4. A Sink TCPC shall provide control of VBUS sink path (see COMMAND).

5. A Sink TCPC shall provide a mechanism for detecting a Disconnect if it is capable of

sinking a voltage greater than vSafe5V (see Section 4.4.15.1). 6. A Sink TCPC shall provide a mechanism for detecting vSafe0V.

Sink with Accessory support is optional, but if implemented shall follow the table below.

Name USB-PD VCONN Swap Power Role Swap Support USB-PD Support Required Optional Required CC CONTROL CC Detect Status Port Disable Roles Supported Required Required (Rp to zOpen) SNK (Rd) Required SRC (Rp default) Required PORT POWER CONTROL Power Status Supply VCONN Sink VBUS Supply VBUS Dead Battery Required Required Required Optional Required (present Rd when no power) Functionality

Release 1.0

October 20, 2015

4.4.6.2 POWER_STATUS (Required)

- 46 - USB Type-C Port Controller

Interface Specification

The TCPM reads this register upon detecting an Alert# and reading the

ALERT.PortPowerStatus Register set to 1. The TCPC indicates the current Power Status in this register.

The TCPM operating as a Sink at vSafe5V (with or without a USB PD Contract) shall detect VBUS presence and removal by reading the VBUSPresent bit.

The TCPM shall check the state of the TCPC Initialization Status bit when it starts or resets. The TCPM shall not start normal operation until the TCPC Initialization Status bit is cleared. The TCPC shall set the TCPC Initialization Status bit to zero when initialization or reset is complete and all registers are valid.

Table 4-21. POWER_STATUS Register Definition

Bit(s) B7 Name Debug Accessory Connected Description 0b: No Debug Accessory connected (default) 1b: Debug Accessory connected Reflects the state of the DebugAccessoryConnected# output if supported Required (Register is required but output is not required) B6 TCPC Initialization Status 0b: The TCPC has completed initialization and all registers are valid 1b: The TCPC is still performing internal initialization and the only registers that are guaranteed to return the correct values are 00h..0Fh Required B5 Sourcing High Voltage 0b: vSafe5V 1b: High Voltage This does not control the path, just provides a monitor of the status. Assert as long as supplying voltage greater than vSafe5V. Required if voltage higher than vSafe5V can be sourced B4 Sourcing VBUS 0b: Sourcing VBUS is disabled 1b: Sourcing VBUS is enabled This does not control the path, just provides a monitor of the status. Required B3 VBUS Present Detection Enabled 0b: VBUS Present Detection Disabled 1b: VBUS Present Detection Enabled (default) Indicates if the TCPC is monitoring for VBUS Present or if the circuit has been powered off Required B2 VBUS Present 0b: VBUS Disconnected 1b: VBUS Connected The TCPC shall report VBUS present when TCPC detects VBUS rises above 4V. The TCPC shall report VBUS is not present when TCPC detects VBUS falls below 3.5V. The TCPC may report VBUS is not present if VBUS is between 3.5V and 4V. Required Copyright ? 2015 USB 3.0 Promoter Group. All rights reserved.

Release 1.0

October 20, 2015 Bit(s) B1 - 47 -

Name USB Type-C Port Controller

Interface Specification

Description VCONN Present 0b: VCONN is not present 1b: This bit is asserted when VCONN present CC1 or CC2. Threshold is fixed at 2.4V If POWER_CONTROL.EnableVCONN is disabled VCONN Present should be set to 0b. Required B0 Sinking VBUS 0b: Sink is Disconnected (Default and if not supported) 1b: TCPC is sinking VBUS to the system load Required 4.4.6.3 FAULT_STATUS (Required)

The TCPM reads this register upon detecting an Alert# and reading the ALERT.Fault bit set to 1. The TCPC indicates the current fault status in this register.

The TCPC indicates a Fault status change has occurred by presenting a logical 1 in the

corresponding bit position in this register, presenting a logical 1 to the ALERT.Fault bit, and asserting the Alert# pin if the corresponding fault bit in FAULT_STATUS_MASK is 1 and ALERT_MASK.Fault is 1. The TCPM clears the FAULT bit by writing a logical 1 to the

respective FAULT bit position and then writing a logical 1 to the ALERT.Fault bit after all bits in FAULT_STATUS have been cleared. The TCPM can clear any number of FAULT bits in a single write by setting multiple bits to logical 1 and the rest of the bits in the register to

logical 0. The TCPM writing a logical 0 to any FAULT bit has no effect and therefore does not cause those FAULT bits to be set or cleared.

Table 4-22. FAULT_STATUS Register Definition

Bit(s) B7 B6 Reserved Name Force Off VBUS (Source or Sink) Description Shall be set to zero by sender and ignored by receiver 0b: No Fault Detected, no action (default and not supported) 1b: VBUS Source/Sink has been forced off due to external fault The TCPC has disconnected VBUS due to STANDARD_INPUT.ForceOffVbus. Required if STANDARD_INPUT_CAPABILITIES_1.ForceOffVbus = 1b B5 Auto Discharge Failed 0b: No discharge failure 1b: Discharge commanded by the TCPM failed If POWER_CONTROL.AutoDischargeDisconnect is set, the TCPC shall report discharge fails if VBUS is not below vSafe0V within tSafe0V. Required B4 Force Discharge Failed 0b: No discharge failure 1b: Discharge commanded by the TCPM failed If POWER_CONTROL.ForceDischarge is set, the TCPC shall report a discharge fails if VBUS is not below vSafe0V within tSafe0V. Required if DEVICE_CAPABILITIES_1.ForceDischarge =1b B3 Internal or External OCP VBUS Over Current Protection Fault 0b: Not in an over-current protection state 1b: Over-current fault latched Required if DEVICE_CAPABILIITES_1.VBUSOCPReporting = 1b Copyright ? 2015 USB 3.0 Promoter Group. All rights reserved.

Release 1.0

October 20, 2015 Bit(s) B2 - 48 -

Name USB Type-C Port Controller

Interface Specification

Description Internal or External OVP VBUS Over Voltage Protection Fault 0b: Not in an over-voltage protection state 1b: Over-voltage fault latched. Required if DEVICE_CAPABILIITES_1.VBUSOVPReporting = 1b 0b: No Fault detected 1b: Over current VCONN fault latched Required if DEVICE_CAPABILITIES_2.VCONNOvercurrentFaultCapable = 1b B1 VCONN Over Current Fault B0 I2C Interface Error 0b: No Error 1b: I2C error has occurred. A TRANSMIT has been sent with an empty TRANSMIT_BUFFER. May be asserted if a non-zero value has been written to a reserved bit in a register. Required

Release 1.0

October 20, 2015

4.4.7 COMMAND (Required)

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Interface Specification

The Command is issued by the TCPM. The Command is cleared by the TCPC after being acted upon.

The TCPM shall issue COMMAND.Look4Connection to enable the TCPC to autonomously toggle the Rp/Rd starting with the Rp. The initial Rp or Rd for toggling is determined by ROLE_CONTROL.CC1 and ROLE_CONTROL.CC2. If ROLE_CONTROL.CC1 and

ROLE_CONTROL.CC2 are not the same value, the COMMAND.Look4Connection shall have no effect.

The TCPM shall issue COMMAND.Look4Connection to enable the TCPC to restart Connection Detection in cases where the role is fixed as Source or Sink, ROLE_CONTROL.DRP = 0b. An example of this is when a potential connection as a Source occurred but was further debounced by the TCPM to find the Sink disconnected. In this case a Source Only or DRP should go back to its Unattached.Src state. This would result in ROLE_CONTROL staying the same.

COMMAND.I2CIdle is used to put the I2C interface into the idle state. When the TCPC

receives COMMAND.I2CIdle, the TCPC may generate a bit-level Not Acknowledge signal (a NAK where SDA remains HIGH during the ninth clock pulse) to its own slave address or any I2C commands.

The TCPM may send the COMMAND.WakeI2C as a throw away command to wake the I2C interface. The COMMAND.WakeI2C requires no action by the TCPC other than to wake the I2C device interface in the TCPC.

COMMAND.I2CIdle is decoupled from other Alert status detection mechanisms (such as CC_STATUS, POWER_STATUS, RECEIVE_DETECT, etc). For example, writing COMMAND. I2CIdle has no effect on ALERT.CcStatus, or the CC_STATUS register behavior. CC_STATUS detection may be turned off by writing to the ROLE_CONTROL register, but its behavior is not affected by the COMMAND.I2CIdle.

The TCPM shall issue COMMAND.SourceVbusHighVoltage to enable the TCPC to transition the Vbus source to a higher voltage level. The target voltage level for COMMAND.SourceVbusHighVoltage is set in a vendor defined manner. The TCPM may need to send vendor defined commands before sending COMMAND.SourceVbusHighVoltage. The steps of transitioning to source a higher voltage than vSafev5V over Vbus may be as follow:

Step 0: TCPC supplies vSafe5V over Vbus

Step 1: TCPM issues vendor defined commands to set the target voltage level of COMMAND.SourceVbusHighVoltage

Step 2: TCPM issues COMMAND.SourceVbusHighVoltage

Step 3: TCPC starts the operation of transitioning to the target voltage level. TCPC shall control the voltage transitioning and meet the power supply requirements in the USB PD specification. For TCPC that directly integrates the power switches, the TCPC shall meet the power supply requirements in the USB PD specification when the TCPC transitions VBUS voltage.

If the TCPM has a new target voltage level for COMMAND.SourceVbusHighVoltage, go to Step 1. The TCPM does not have to go back to vSafe5V and then to a different voltage. It may go directly to the new voltage by setting a new voltage level and then issuing the COMMAND.SourceVbusHighVoltage.

Figure 4-8 and Figure 4-9 indicate the flow from vSafe5V to and from high voltage

respectively.

Release 1.0

October 20, 2015

Table 4-23. COMMAND Register Definition

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Interface Specification

Bit(s) B7..0 Name Command Register Setting 0001 0001b 0010 0010b Description WakeI2C (no action is taken other than to wake the I2C interface). DisableVbusDetect. Disable Vbus present detection. The TCPC shall ignore this command and assert the FAULT_STATUS.I2CInterfaceError if it has sourcing or sinking power over Vbus enabled. EnableVbusDetect. Enable Vbus present detection. DisableSinkVbus. Disable sinking power over Vbus. This COMMAND does not disable POWER_STATUS.VBUSPresent detection. The TCPC shall clear FAULT_STATUS.InternalorExternalOCP and FAULT_STATUS.InternalorExternalOVP. 0011 0011b 0100 0100b 0101 0101b SinkVbus. Enable sinking power over Vbus and enable Vbus present detection. The TCPC shall ignore this command and assert the FAULT_STATUS.I2CInterfaceError if it has sourcing power over Vbus enabled. DisableSourceVbus. Disable sourcing power over Vbus. The TCPC shall stop reporting FAULT_STATUS. Internal or External OCP or OVP Faults. This COMMAND does not disable POWER_STATUS.VBUSPresent detection. SourceVbusDefaultVoltage. Enable sourcing vSafe5V over Vbus and enable Vbus present detection. Source shall transition to vSafe5V if at a high voltage. The TCPC shall ignore this command and assert the FAULT_STATUS.I2CInterfaceError if it has sinking power over Vbus enabled. SourceVbusHighVoltage. Execute sourcing high voltage over Vbus. The TCPC shall ignore this command and assert the FAULT_STATUS.I2CInterfaceError if it is currently sinking voltage from Vbus or does not have ability to source voltages higher than vSafe5V. The TCPC shall ignore this command and assert the FAULT_STATUS.I2CInterfaceError if not already sourcing vSafe5V. The actual voltage to be sourced may be set in a vendor defined manner. The TCPM may need to send vendor defined commands before sending this COMMAND. 0110 0110b 0111 0111b 1000 1000b 1001 1001b Look4Connection. Start DRP Toggling if ROLE_CONTROL.DRP=1b. If ROLE_CONTROL.CC1/CC2 = 01b start with Rp, if ROLE_CONTROL.CC1/CC2 =10b start with Rd. If ROLE_CONTROL.CC1/CC2 are not both 01b or 10b, then do not start toggling. The TCPM shall issue COMMAND.Look4Connection to enable the TCPC to restart Connection Detection in cases where the ROLE_CONTROL contents will not change. An example of this is when a potential connection as a Source occurred but was further debounced by the TCPM to find the Sink disconnected. In this case a Source Only or DRP should go back to its Unattached.Src state. This would result in ROLE_CONTROL staying the same. TCPC to MAINTAIN_STATE in Figure 4-11 1010 1010b RxOneMore. Configure the receiver to automatically clear the RECEIVE_DETECT register after sending the next GoodCRC. This is used to shutdown reception of packets at a known point regardless of packet separation or the depth of the receive FIFO in the TCPC. Reserved. No Action 1100 1100b 1101 1101b 1110 1110b 1111 1111b I2C Idle Note: All other values are reserved; shall be ignored by the receiver

Release 1.0

October 20, 2015 3.6.4 DRP Requirements

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Interface Specification

A TCPC, which supports Dual Role Port operation, is defined as follow:

1. A Dual Role TCPC shall contain CC logic to detect the insertion of a Source, Sink, and

Audio and debug accessory (see ROLE_CONTROL).

2. A Dual Role TCPC shall contain CC logic that implements a mechanism to present Rd

in a dead battery condition (see CC_STATUS).

3. A Dual Role TCPC shall provide control of VBUS source path (see COMMAND). 4. A Dual Role TCPC shall provide control for a Vconn switch (see

POWER_CONTROL.VCONNPowerSupported and POWER_CONTROL.EnableVCONN) 5. The TCPC shall include the monitoring of the presence of VCONN (see

POWER_STATUS.VCONNPresent).

6. A DRP TCPC shall provide a mechanism for detecting a Disconnect if it is capable of

sinking a voltage greater the vSafe5V (see Section 4.4.15.1). 7. A DRP TCPC shall provide a mechanism for detecting vSafe0V.

Name Functionality USB-PD VCONN Swap PR Swap Support USB-PD Support Optional Optional Optional CC CONTROL CC Detect Status Port Disable Roles Supported Required Required (Rp to zOpen) SRC (Rp default, 1.5A, 3A) indicated in DEVICE_CAPABILITIES_1.SourceResistorSupported SNK (Rd) Required PORT POWER CONTROL Power Status Supply VCONN Sink VBUS Supply VBUS Dead Battery Required Required Required if Dead Battery Supported Required Required (present Rd when no power) Copyright ? 2015 USB 3.0 Promoter Group. All rights reserved.

Release 1.0

October 20, 2015 - 22 - USB Type-C Port Controller

Interface Specification

4 USB Type-C Port Controller Interface

The USB Type-C Port Controller Interface (TCPCI) is a low level interface which handles VBUS and VCONN power connections, CC communication and USB-PD message delivery through a simple register interface. Communication between the TCPC and the USB Type-C Port Manager (TCPM) is over an I2C bus.

The TCPCI uses the I2C protocol with the following behaviors:

1. The TCPM is the only master on the I2C bus. 2. The TCPC is a slave device on the I2C bus.

3. The TCPM designer must meet the I2C bus loading requirements when determining

the maximum number of devices on the I2C bus. 4. Each USB Type-C port has its own unique I2C slave address. The TCPC may support

multiple USB Type-C ports. In case the TCPC supports multiple ports, each USB Type-C port shall have a unique I2C slave address. 5. The TCPC shall support Fast-mode (Fm+) bus speed. It may also support other bus

speeds. 6. The TCPC shall have an open drain output, active low Alert# Pin. This pin is used to

indicate a change of state, where Alert# pin is asserted when any Alert Bits are set. 7. The TCPCI shall support an I/O voltage range from 1.8V to 3.6V.

8. The TCPC as a slave device shall be accessible through I2C communication protocols

compliant with “I2C-bus specification and user manual Rev.6” (4th April 2014) http://www.nxp.com/documents/user_manual/UM10204.pdf 9. The TCPC should auto-increment the I2C internal register address of the last byte

transferred during a read independent of an ACK/NAK from the master. 10. The TCPC may implement the SMBus version 3 bus protocol (Section 6.5 of the

SMBus Specification, version 3.0 available at http://smbus.org/specs/). 11. The TCPC shall allow reads to every register even when defined as Write only. The

TCPM should assume the register information returned from a Write only register is not valid. 12. The TCPC shall not NAK if the TCPM writes to a register or bit that is not

implemented or reserved.

Release 1.0

October 20, 2015 4.1 Register Map

- 23 - USB Type-C Port Controller

Interface Specification

The 16-bit registers are used for notation convenience. Each 16-bit register occupies two contiguous bytes, with its 8 Least Significant bits stored in the first (lower address) byte and its 8 Most Significant bits stored in the second (higher address) byte.

Table 4-1. Register Map

Address 00h..01h 02h..03h 04h..05h 06h,,07h 08h..09h 0Ah..0Bh 0C..0Fh 10h..11h 12h..13h Register Name VENDOR_ID PRODUCT_ID DEVICE_ID USBTYPEC_REV USBPD_REV_VER PD_INTERFACE_REV Reserved ALERT ALERT_MASK Required /Optional? Required Required Required Required Required Required Required Required Required Type R R R R R R R/W R/W Reset Value VD VD VD VD VD VD 0000h 0FFFh Definition Table 4-2. VENDOR_ID Register Definition Table 4-3. PRODUCT_ID Register Definition Table 4-4. DEVICE_ID Register Definition Table 4-5. USBTYPEC_REV Register Definition Table 4-6. USBPD_REV_VER Register Description Table 4-7. PD_INTERFACE_REV Register Description Intentionally Blank Table 4-8. ALERT Register Definition Table 4-9. ALERT_MASK Register Definition 14h 15h 16..17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h..22h 23h 24h..25h 26h..27h 28h 29h 2Ah..2Dh 2Eh 2Fh POWER_STATUS_MASK FAULT_STATUS_MASK Reserved CONFIG_STANDARD_OUTPUT TCPC_CONTROL ROLE_CONTROL FAULT_CONTROL POWER_CONTROL CC_STATUS POWER_ STATUS FAULT_STATUS Reserved COMMAND DEVICE_CAPABILITIES_1 DEVICE_CAPABILITIES_2 STANDARD_INPUT_CAPABILITIES STANDARD_OUTPUT_CAPABILITIES Reserved MESSAGE_HEADER_INFO RECEIVE_DETECT Required Required Required Optional Required Required Partial R Partial R Required Required Required Required Required Required Required Required Required Required Required Required R/W R/W R/W R/W R/W R/W R/W R R R/W R W R R R R R R/W R/W 00h VD VD VD VD Table 4-15 00h FFh 7Fh 60h 00h Table 4-15 00h 10h Table 4-10. POWER_STATUS_MASK Register Definition Table 4-11. FAULT_STATUS_MASK Register Definition Intentionally Blank Table 4-12. CONFIG_STANDARD_OUTPUT Register Definition Table 4-13. TCPC_Control Register Definition Table 4-14. ROLE_CONTROL Register Definition Table 4-16. FAULT_CONTROL Register Definition Table 4-17. POWER_CONTROL Register Definition Table 4-20. CC_STATUS Register Definition Table 4-21. POWER_STATUS Register Definition Table 4-22. FAULT_STATUS Register Definition Intentionally Blank Table 4-23. COMMAND Register Definition Table 4-24. DEVICE_CAPABILITIES_1 Register Definition Table 4-25. DEVICE_CAPABILITIES_2 Register Definition Table 4-26. STANDARD_INPUT_CAPABILITIES Register Definition Table 4-27. STANDARD_OUTPUT_CAPABILITIES Register Definition Intentionally Blank Table 4-28. MESSAGE_HEADER_INFO Register Definition Table 4-29. RECEIVE_DETECT Register Definition RECEIVE_BUFFER 30h RECEIVE_BYTE_COUNT Required R 00h Number of Bytes in the RECEIVE_BUFFER that are not stale Table 4-30 Copyright ? 2015 USB 3.0 Promoter Group. All rights reserved.

Release 1.0

October 20, 2015

Address 31h 32h 33h 34h 35h 36h 37h 38h … 4Fh 50h Register Name RX_BUF_FRAME_TYPE RX_BUF_HEADER_BYTE_0 RX_BUF_HEADER_BYTE_1 RX_BUF_OBJ1_BYTE_0 RX_BUF_OBJ1_BYTE_1 RX_BUF_OBJ1_BYTE_2 RX_BUF_OBJ1_BYTE_3 RX_BUF_OBJ2_BYTE_0 RX_BUF_OBJn_BYTE_m RX_BUF_OBJ7_BYTE_3 TRANSMIT Required /Optional? Required Required Required Required Required Required Required Required Required Required Required - 24 -

Type R R R R R R R R R R USB Type-C Port Controller

Interface Specification

Reset Value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Definition Type of received frame (with a reference to a description of the register) Byte 0 (bits 7..0) of message header Byte 1 (bits 15..8) of message header Byte 0 (bits 7..0) of 1st data object Byte 1 (bits 15..8) of 1st data object Byte 2 (bits 23..16) of 1st data object Byte 3 (bits 31..24) of 1st data object Byte 0 (bits 7..0) of 2nd data object Byte m of nth data object byte 3 (bits 31..24) of 7th data object Table 4-34. TRANSMIT Register Definition R/W TRANSMIT_BUFFER 51h 52h 53h 54h … 6Fh 70..71h TRANSMIT_BYTE_COUNT TX_BUF_HEADER_BYTE_0 TX_BUF_HEADER_BYTE_1 TX_BUF_OBJ1_BYTE_0 TX_BUF_OBJn_BYTE_m TX_BUF_OBJ7_BYTE_3 VBUS_VOLTAGE Required Required Required Required Required Required Required if greater than vSafe5V Required Sink >vSafe5V Required Sink >vSafe5V Required >vSafe5V Required >vSafe5V Required Optional R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h 00h 00h 00h The number of bytes the TCPM will write Byte 0 (bits 7..0) of message header Byte 1 (bits 15..8) of message header Byte 0 (bits 7..0) of 1st data object Byte m of nth data object byte 3 (bits 31..24) of 7th data object Table 4-38. VBUS_VOLTAGE Register Definition R 72..73h 74..75h 76..77h 78..79h 7A..7Fh 80h..FF VBUS_SINK_DISCONNECT_THRESHOLD VBUS_STOP_DISCHARGE_THRESHOLD VBUS_VOLTAGE_ALARM_HI_CFG VBUS_VOLTAGE_ALARM_LO_CFG Reserved Vendor defined bits R/W R/W R/W R/W vSafe5V vSafe0V 00h 00h VD Table 4-39. VBUS_SINK_DISCONNECT_THRESHOLD Register Description Table 4-40. VBUS_STOP_DISCHARGE_THRESHOLD Register Description Table 4-41. VBUS_VOLTAGE_ALARM_HI_CFG Register Description Table 4-42. VBUS_VOLTAGE_ALARM_LO_CFG Register Description Intentionally Blank As many as Vendor Defines Notes:

VD - Vendor Defined

Release 1.0

October 20, 2015 - 25 - USB Type-C Port Controller

Interface Specification

4.2 TCPC SMBus Optional Normative Requirements

Each row of the register map table defines a register. Some TCPC-s implement the SMBus protocol on top of the I2C protocol and some do not. A TCPC that implements the SMBus protocol requires the TCPM to:

? Read/Write only a single register in a given I2C transaction. ? Write the complete register in a single I2C transaction. ? Begin reading a register from its first byte.

A TCPC that does not implement the SMBus protocol does not enforce these requirements.

If the TCPM attempts to write multiple registers in a single I2C transaction, the TCPC may assert ALERT.InterfaceError and ignore the write. If the TCPM attempts to read multiple registers in a single transaction, the TCPC may assert ALERT.InterfaceError and leave the SDA line open so the TCPM reads all 1’s in the following bytes. If the TCPM attempts to read a register address that is not the first byte in that register, the TCPC may assert ALERT.InterfaceError and leave the SDA line open so the TCPM reads all 1’s. 4.3 Writing and Reading TCPC Registers 4.3.1 Writing Single Byte Registers

To ensure correct behavior with TCPCs that implement SMBus, the TCPC cannot use the I2C short-cut to write consecutive registers in a single operation. The TCPM shall use two transactions to write ROLE_CONTROL and POWER_CONTROL as shown in Figure 4-1.

Slave AddressRegister address=1AhSA6A5A4A3A2A1A00WriteAC7C6C5C4C3C2C1C0AROLE_CONTROLRegister address=1AhAPStopSlave AddressRegister address=1BhSA6A5A4A3A2A1A00WriteAC7C6C5C4C3C2C1C0AFAULT_CONTROLRegister address=1BhAPStop

Figure 4-1. Writing Consecutive Registers with or without the SMBUS Protocol

Release 1.0

October 20, 2015

4.3.2 Reading Single Byte Registers

- 26 - USB Type-C Port Controller

Interface Specification

Figure 4-2 indicates how to read single byte registers with I2C or SMBus protocols.

Slave AddressRegister address=1AhSA6A5A4A3A2A1A00WriteAC7C6C5C4C3C2C1C0ASrRepeated StartSlave AddressA6A5A4A3A2A1A01ReadAROLE_CONTROLRegister address=1AhAPStopSlave AddressRegister address=1BhSA6A5A4A3A2A1A00WriteAC7C6C5C4C3C2C1C0ASrRepeated StartSlave AddressA6A5A4A3A2A1A01ReadAFAULT_CONTROLRegister address=1BhNPStop

Figure 4-2. Reading Consecutive Registers with or without the SMBus Protocol

4.3.3 Writing Multiple-Byte Registers

Bytes that are always written at the same time can be grouped into a register so the SMBus protocol has less overhead. The TCPM shall write both bytes in the ALERT register at the same time as depicted in the following Figure 4-3.

Slave AddressRegister address=10hSA6A5A4A3A2A1A00WriteAC7C6C5C4C3C2C1C0AALERT LowAALERT HighAPStop

Figure 4-3. Writing a 2-Byte Register with or without the SMBus Protocol

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October 20, 2015

4.3.4 Reading Multiple-Byte Registers

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Interface Specification

Bytes that are always read at the same time can be grouped into a register so the SMBus protocol has less overhead. The TCPM shall read both bytes in the VENDOR_ID register at the same time as depicted in the following Figure 4-4.

Slave AddressRegister address=00hSStartA6A5A4A3A2A1A00WriteAC7C6C5C4C3C2C1C0ASrRepeated StartSlave AddressA6A5A4A3A2A1A01AVendor ID Vendor ID Low (00h)AHigh (01h)NPReadStop

Figure 4-4. Reading a 2-Byte Register with or without the SMBus Protocol

4.3.5 Writing the TRANSMIT_BUFFER

Figure 4-5 illustrates how the transmit buffer can be written with or without the SMBus protocol.

Slave AddressRegister address=51hSA6A5A4A3A2A1A00AC7C6C5C4C3C2C1C0AWriteAssumeTransmit Byte Count = MTransmit Byte CountATransmit Header LowATransmit Header HighAByte MAPRegister Register Register Register Stopaddress=51haddress=52haddress=53haddress=51h+M

Figure 4-5. Writing the TRANSMIT_BUFFER with or without the SMBus Protocol

Release 1.0

October 20, 2015

4.3.6 Reading the RECEIVE_BUFFER

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Interface Specification

Figure 4-6 illustrates how the receive buffer can be read with or without the SMBus protocol.

Slave AddressRegister address=30hSStartA6A5A4A3A2A1A00WriteAC7C6C5C4C3C2C1C0ASrRepeated StartSlave AddressM bytesA6A5A4A3A2A1A01ReadAReceive Byte CountAByte A1Byte 2Byte MNPStop

Figure 4-6. Reading the RECEIVE_BUFFER with or without the SMBus Protocol

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October 20, 2015 4.4 Register Definition

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Interface Specification

This section defines the registers for the TCPC. 4.4.1 Identification Registers 4.4.1.1 VENDOR_ID (Required)

A Vendor ID, or VID, is used to identify the TCPC vendor. The VID is a unique 16-bit unsigned integer assigned by USB-IF.

Table 4-2. VENDOR_ID Register Definition

Bit(s) B15..0 Name Vendor ID (VID) Description A unique 16-bit unsigned integer assigned by the USB-IF to the Vendor. 4.4.1.2 PRODUCT_ID and DEVICE_ID (Required)

The Product ID, or PID, is used to identify the product. The Device ID, bcdDevice, is used to identify the release version of the product. Manufacturers should set the USB Product ID field to a unique value across all USB products from the vendor. The Product ID should identify the product from the vendor and the bcdDevice field should reflect a version number relevant to the release version of the product.

Table 4-3. PRODUCT_ID Register Definition

Bit(s) B15..0 Name USB Product ID (PID) Description A unique 16-bit unsigned integer assigned uniquely by the Vendor to identify the TCPC. Table 4-4. DEVICE_ID Register Definition

Bit(s) B15..0 Name bcdDevice Description A unique 16-bit unsigned integer assigned by the Vendor to identify the version of the TCPC. 4.4.1.3 USBTYPEC_REV (Required)

This register refers to USB Type-C Cable and Connector Specification Revision, USB Type-C represented by a unique 16-bit unsigned register. The format is packed binary coded decimal.

This specification revision 1.0 aligns with USB Type-C Version 1.1.

Table 4-5. USBTYPEC_REV Register Definition (Required)

Bit(s) B15..8 B7..0 Name Reserved USB Type-C Revision Description Set to 0 Revision number assigned by USB-IF

4.4.1.4 USBPD_REV_VER (Required)

This register refers to USB-PD Specification Revision and Version, USB PD represented by a unique 16-bit unsigned integer. The format is packed binary coded decimal.

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Interface Specification

This specification revision 1.0 aligns with USB-PD Revision 2.0 version 1.1.

Table 4-6. USBPD_REV_VER Register Description

Bit(s) B15..8 B7..0 Name bcdUSBPD Revision bcdUSBPD Version Description 0010 0000 – Revision 2.0 0001 0000 – Version 1.0 0001 0001 – Version 1.1 Etc.

4.4.1.5 USB-PD Inter-Block Specification Revision (Required)

The USB-PD Inter-Block Specification Revision register refers to this Specification Revision and Version represented by a unique 16-bit unsigned integer. The format is packed binary coded decimal.

Table 4-7. PD_INTERFACE_REV Register Description

Bit(s) B15..8 B7..0 Name bcd USB-PD Inter-Block Specification Revision bcd USB-PD Inter-Block Specification Version Description 0001 0000 – Revision 1.0 (this release) 0001 0000 – Version 1.0 (this release) 0001 0001 – Version 1.1 Etc.

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Interface Specification

4.4.4 CONFIGURE STANDARD OUTPUT (Optional Normative)

This register is required if it is reported as supported in the one of the DEVICE_CAPABILITES registers (Section 4.4.8.1). This read/write register is used to configure the Standard

Outputs or read the status of the Standard Outputs. The TCPM writes to this register to set the Standard Output Signal defined in Table 4-44. The Standard Outputs shall reset to open-drain per Table 4-1.

Table 4-12. CONFIG_STANDARD_OUTPUT Register Definition

Bit(s) B7 Name High Impedance outputs Type 0b: Standard output control (default) 1b: Force all outputs to high impedance May be used to save power in Sleep Controlled by the TCPM. 0b: Debug Accessory Connected# output is driven low 1b: Debug Accessory Connected# output is driven high (default) Controlled by either the TCPM or TCPC. The TCPC shall ignore writes to this bit if TCPC_CONTROL.DebugAccessoryControl = 0b. B6 Debug Accessory Connected# B5 Audio Accessory Connected# 0b: Audio Accessory connected Controlled by the TCPM 1b: No Audio Accessory connected (default) B4 Active Cable Connected 0b: No Active Cable connected (default) 1b: Active Cable connected Controlled by the TCPM 00b: No connection (default) 01b: USB3.1 Connected 10b: DP Alternate Mode – 4 lanes 11b: USB3.1 + Display Port Lanes 0 & 1 Controlled by the TCPM 0b: No Connection (default) 1b: Connection Controlled by the TCPM. 0b: Normal (CC1=A5, CC2=B5, TX1=A2/A3, RX1=B10/B11) default 1b: Flipped (CC2=A5, CC1=B5, TX1=B2/B3, RX1=A10/A11) Controlled by the TCPM The TCPC shall ignore writes to this bit if TCPC_CONTROL.DebugAccessoryControl = 0 B3..2 MUX Control B1 Connection Present B0 Connector Orientation Copyright ? 2015 USB 3.0 Promoter Group. All rights reserved.

Release 1.0

October 20, 2015

4.4.5 Control and Configuration Registers 4.4.5.1 TCPC_CONTROL (Required)

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Interface Specification

The TCPM writes to the TCPC_ CONTROL register to set the Plug Orientation and enable/disable clock stretching.

I2C_Clock_Stretching_Control allows the TCPM to control TCPC clock stretching on the I2C bus. Allowing clock stretching may result in lower power from the TCPC, but degrade

throughput. Disabling clock stretching will result in increased I2C bus throughput, but may result in higher TCPC power. The TCPC is not allowed to NAK I2C transfers no matter which clock stretching setting is chosen by the TCPM, unless the TCPM has put it to sleep using COMMAND.I2CIdle.

Table 4-13. TCPC_Control Register Definition

Bit(s) B7..5 B4 Name Description Shall be set to zero by sender and ignored by receiver 0b: Controlled by TCPC (power on default) 1b: Controlled by TCPM. The TCPM writes 1b to this register to take over control of asserting the DebugAccessoryConnected#. See Figure 4-13. Required (Register is required but output is not required) Reserved Debug Accessory Control B3..2 I2C Clock Stretching Control Clock Stretching Control 00b: Disable clock stretching. TCPC shall not perform any clock stretching during I2C transfers. 01b: Reserved 10b: Enable clock stretching. TCPC is allowed limited clock stretching during each I2C Transfer. 11b: Enable clock stretching only if the Alert pin is not asserted. As soon as Alert is asserted, clock stretching is disabled by the TCPC. The TCPC datasheet should contain details as to the power consequences of clock stretching as well as the max duration of clock stretching per I2C transaction. This is only necessary if clock stretching is implemented. The TCPC shall limit total clock stretching as detailed in Section 4.10. This feature is optional. The TCPC is allowed to ignore updates to this bit field if it has not implemented clock stretching. The power on default value is such to disable clock stretching. B1 BIST Test Mode Setting this bit to 1 is intended to be used only when a USB compliance tester is using USB BIST Test Data to test the PHY layer of the TCPC. The TCPM should clear this bit when a detach is detected. 0: Normal Operation. Incoming messages enabled by RECEIVE_DETECT passed to TCPM via Alert. 1: BIST Test Mode. Incoming messages enabled by RECEIVE_DETECT result in GoodCRC response but may not be passed to the TCPM via Alert. TCPC may temporarily store incoming messages in the Receive Message Buffer, but this may or may not result in a Receive SOP* Message Status or a Rx Buffer Overflow alert. The TCPM can mask or ignore received message alerts when this bit is set to 1 since the TCPC may or may not assert the alert. The TCPM may also treat received messages in this mode in the same way as received messages during normal operation. Copyright ? 2015 USB 3.0 Promoter Group. All rights reserved.

Release 1.0

October 20, 2015 Bit(s) B0 - 38 - USB Type-C Port Controller

Interface Specification

Description Name Plug Orientation 0b: When Vconn is enabled, apply it to the CC2 pin. Monitor the CC1 pin for BMC communications if PD messaging is enabled. 1b: When Vconn is enabled, apply it to the CC1 pin. Monitor the CC2 pin for BMC communications if PD messaging is enabled. Required

4.4.5.2 ROLE_CONTROL (Required)

The TCPM writes to this register to configure the CC pull up (Rp) or pull down (Rd) resistors.

Table 4-15 defines the power on default for ROLE_CONTROL and MESSAGE_HEADER_INFO. The TCPM shall first write B6 (DRP) = 0b and B3..0 (CC1/CC2) if it wishes to control the Rp/Rd directly. In this mode, the TCPM writes to B3..0 (CC1/CC2) each time it wishes to change the CC1/CC2 values.

The TCPM may configure the TCPC to autonomously perform a static search for connection (no toggle) by first writing B6 (DRP) = 0b and the static value of Rp/Rd to B3..0 (CC1/CC2). An example of this is for Source or Sink only conditions. Another example is when a

connection has been detected via DRP toggling but the TCPM wishes to attempt Try.Src or Try.Snk scenario.

The TCPM may configure the TCPC to autonomously toggle the Rp/Rd. The TCPM shall write B6 (DRP) =1b and the starting value of Rp/Rd to B3..0 (CC1/CC2) to indicate DRP

autonomous toggling mode to the TCPC. The TCPC shall not start the DRP toggling until

subsequently the TCPM writes to the COMMAND register to start the DRP toggling. Refer to Figure 4-11.

If DRP=1b, the only allowed values for CC1/CC2 are Rp/Rp or Rd/Rd.

COMMAND.Look4Connection shall do nothing if CC1/CC2 are not Rp/Rp or Rd/Rd.

When CC1 and CC2 are set to Open and DRP = 0b, the TCPC may power down the PHY and CC Status comparators.

Table 4-14. ROLE_CONTROL Register Definition

Bit(s) B7 B6 Name Reserved DRP Description Shall be set to zero by sender and ignored by receiver 0b: No DRP. Bits B3..0 determine Rp/Rd/Ra or open settings 1b: DRP The TCPC shall use the Rp value defined in B5..4 when a connection is resolved, ie. Upon entry to Potential_Connect_as_Src in Figure 4-11. TCPC State Machine before a Connection. The TCPC toggles CC1 & CC2 after receiving COMMAND.Look4Connection and until a connection is detected. Upon connection, the TCPC shall resolve to either an Rp or Rd and report the CC1/CC2 State in the CC_STATUS register. The CC pins shall stay in Potential_start_as_SRC or Potential_start_as_Sink until directed otherwise. Copyright ? 2015 USB 3.0 Promoter Group. All rights reserved.

Release 1.0

October 20, 2015 Bit(s) B5..4 - 39 - USB Type-C Port Controller

Interface Specification

Description Name Rp Value 00b: Rp default 01b: Rp 1.5A 10b: Rp 3.0A 11b: Reserved B3..2 CC2 00b: Ra 01b: Rp (Use Rp definition in B5..4) 10b: Rd 11b: Open (Disconnect or don’t care) B1..0 CC1 00b: Ra 01b: Rp (Use Rp definition in B5..4) 10b: Rd 11b: Open (Disconnect or don’t care) Table 4-15 defines the power on default for ROLE_CONTROL and MESSAGE_HEADER_INFO.

Table 4-15. Power on Default Conditions

DEVICE_CAPABILITIES.RolesSupported Source or Sink (000b) Source (001b) Sink (010b) Sink with Accessory (011b) DRP (100b) Source, Sink, DRP (101b and 110b) Applies to SOP Devices 0Ah 05h 0Ah 0Ah ROLE_CONTROL (Default) MESSAGE_HEADER_INFO (Default) 02h 0Bh 02h 02h 02h 02h 0Ah – dead battery 1Fh – non dead battery 0Ah – Source, Sink, or DRP dead battery 1Fh – DRP non dead battery

4.4.5.3 FAULT_CONTROL (Required)

The TCPM writes to FAULT_CONTROL to enable/disable FAULT circuitry.

Table 4-16. FAULT_CONTROL Register Definition

Bit(s) B7..5 B4 Reserved Name Force Off VBUS (Source or Sink) Description Shall be set to zero by sender and ignored by receiver 0b: Allow STANDARD INPUT SIGNAL Force Off Vbus control (default) 1b: Block STANDARD INPUT SIGNAL Force Off Vbus control This enables or disables the STANDARD INPUT SIGNAL Force Off Vbus (4.5.1) functionality for debug purposes. Required if STANDARD_INPUT_CAPABILITES.ForceOffVBUS Copyright ? 2015 USB 3.0 Promoter Group. All rights reserved.

Release 1.0

October 20, 2015 Bit(s) B3 - 40 -

Name USB Type-C Port Controller

Interface Specification

Description VBUS Discharge Fault Detection Timer 0b: VBUS Discharge Fault Detection Timer enabled 1b: VBUS Discharge Fault Detection Timer disabled This enables the timers for both FAULT_STATUTS.AutoDischargeFailed and FAULT_STATUS.ForceDischargeFailed Required B2 Internal or External OCP VBUS Over Current Protection Fault 0b: Internal and External OCP circuit enabled 1b: Internal and External OCP circuit disabled Required if DEVICE_CAPABILIITES_1.VBUSOCPReporting = 1b 0b: Internal and External OVP circuit enabled 1b: Internal and External OVP circuit disabled Required if DEVICE_CAPABILIITES_1.VBUSOVPReporting = 1b 0b: Fault detection circuit enabled 1b: Fault detection circuit disabled Required if DEVICE_CAPABILITIES_2.VCONNOvercurrentFaultCapable = 1b B1 Internal or External OVP VBUS Over Voltage Protection Fault B0 VCONN Over Current Fault

4.4.5.4 POWER_CONTROL (Required)

The timing parameters for the TCPM in conjunction with the TCPC must meet the USB PD requirements.

The TCPM reads the CC_STATUS, POWER_STATUS and VBUS_VOLTAGE registers to determine the connection state and the orientation of a USB Type-C port.

To source VCONN over one of the CC pins (irrespective of the status of VBUS), all of the following conditions are required:

? ?

The TCPM shall set EnableVCONN to logical 1

The TCPM shall write to TCPC_CONTROL.PlugOrientation to inform TCPC which CC pin (not connected through the cable) is repurposed as VCONN

Table 4-17. POWER_CONTROL Register Definition

Bit(s) B7 B6 Reserved Name VBUS_VOLTAGE Monitor Description Shall be set to zero by sender and ignored by receiver 0b: VBUS_VOLTAGE Monitoring is enabled (default) 1b: VBUS_VOLTAGE Monitoring is disabled Controls only VBUS_VOLTAGE Monitoring. VBUS_VOLTAGE shall report all zeroes if disabled. Required if DEVICE_CAPABILITIES_1.VBUSMeasuremen andAlarmCapable = 1b B5 Disable Voltage Alarms 0b: Voltage Alarms Power status reporting is enabled (default) 1b: Voltage Alarms Power status reporting is disabled Controls VBUS_VOLTAGE_ALARM_HI_CFG and VBUS_VOLTAGE_ALARM_LO_CFG. Required if DEVICE_CAPABILITIES_1.VBUSMeasuremen andAlarmCapable = 1b Copyright ? 2015 USB 3.0 Promoter Group. All rights reserved.

Release 1.0

October 20, 2015 Bit(s) B4 - 41 -

Name USB Type-C Port Controller

Interface Specification

Description AutoDischargeDisconnect 0b: The TCPC shall not automatically discharge VBUS based on VBUS voltage. 1b: The TCPC shall automatically discharge (default) Refer to 4.4.5.4.1 and 4.4.5.4.2. Strength of discharge set by tAutoDischarge in Table 4-18 Setting this bit in a Source TCPC triggers the following actions upon disconnection detection: 1. Disable sourcing power over VBUS 2. VBUS discharge Sourcing power over VBUS shall be disabled before or at same time as starting VBUS discharge. Setting this bit in a Sink TCPC triggers the following action upon disconnection detection: 1. VBUS discharge The TCPC shall automatically disable discharge once the voltage on VBUS is below vSafe0V (max) or VBUS_STOP_DISCHARGE_THRESHOLD. Disconnect detection is defined in Figure 4-12. VBUS_STOP_DISCHARGE_THRESHOLD, if enabled, takes priority over vSafe0V. Required B3 Enable Bleed Discharge 0b: Disable bleed discharge (default) 1b: Enable bleed discharge of VBUS Bleed Discharge is a low current discharge to provide a minimum load current if needed 10K Ohms or 2mA recommended Refer to 4.4.5.4.5 Required if DEVICE_CAPABILITIES_1.BleedDischarge = 1b B2 Force Discharge 0b: Disable forced discharge (default) 1b: Enable forced discharge of VBUS. Refer to 4.4.5.4.3 Required if DEVICE_CAPABILITIES_1.ForceDischarge = 1b B1 VCONN Power Supported 0b: TCPC delivers at least 1W on VCONN 1b: TCPC delivers at least the power indicated in DEVICE_CAPABILITIES.VCONNPowerSupported Refer to TCPC datasheet for actual power limit implemented Required B0 Enable VCONN 0b: Disable VCONN Source (default) 1b: Enable VCONN Source to CC Required

Table 4-18. Discharge Timing Parameters

Name tAutoDischarge Description Time to discharge 100uF and 400 Ohms maximum or 24mA minimum when AutoDischarge is engaged Time from Disconnect to detection of a Disconnect Min Max 50 Units ms tDisconnectDetect 6 ms Copyright ? 2015 USB 3.0 Promoter Group. All rights reserved.

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October 20, 2015 - 42 - USB Type-C Port Controller

Interface Specification

4.4.5.4.1 Automatic Source Full Discharge by the TCPC after a Disconnect (normative)

When in the Source mode and POWER_CONTROL.AutoDischargeDisconnect=1, the TCPC shall fully discharge VBUS to vSafe5V (max) within tSafe5V and then to vSafe0V within tSafe0V when a Disconnect occurs. The TCPC is in Source mode any time

MESSAGE_HEADER_INFO.PowerRole=1. A TCPC in Source mode shall detect a Disconnect if the CCState for the monitored CC pin indicates SRC.Open. The monitored CC pin is specified by TCPC_CONTROL.PlugOrientation.

The TCPC shall discharge Vbus to vSafe0V after a power on reset before applying the Rp. 4.4.5.4.2 Automatic Sink Discharge by the TCPC after a Disconnect (normative)

The TCPC is in the Sink mode any time MESSAGE_HEADER_INFO.PowerRole=0. A TCPC in Sink mode shall use either the POWER_STATUS.VbusPresent transition from 1b to 0b or VBUS falling below VBUS_SINK_DISCONNECT_THRESHOLD, Table 4-39, as a Sink disconnect

indicator. The mechanism used shall be defined in DEVICE_CAPABILITIES_2.SinkDisconnect. The Sink TCPC shall detect a cable removal within tDisconnectDetect, Table 4-18, of the Sink disconnect indicator change and enable the automatic discharge circuitry. Should a TCPM need to know when VBUS discharge is complete, it may set VBUS_VOLTAGE_ALARM_LO_CFG to vSafe0V if

DEVICE_CAPABILITIES_2.StopDischargeThreshold=1 or to vSafe0V (max) if DEVICE_CAPABILITIES_2.StopDischargeThreshold=0.

When in Sink mode and POWER_CONTROL.AutoDischargeDisconnect=1, the TCPC shall fully discharge VBUS to vSafe5V (max) within tSafe5V and then to vSafe0V within tSafe0V of the removal of the cable.

When the source is removed, the system load and/or bleed discharge will discharge the sink bulk capacitance cSnkBulkPd. The time required to discharge cSnkBulkPd to below the

disconnect detection threshold is tSinkDischargeBleed and depends upon the strength of the bleed discharge and the system load. The time required to discharge the sink bulk

capacitance to vSafe5V is tSinkDischargeFull and depends upon the strength of the full discharge and the system load. The total time tSinkDischargeBleed + tSinkDischargeFull shall not exceed tSafe5V (max) to transition to vSafe5V. As an example, if:

? ? ? ? ?

the bleed discharge pull down is 10kohm, the sink bulk capacitance cSnkBulkPd is 100uF, there is no system load,

the initial voltage is 21.5 V (20 V + 5% + vSrcValid), and VBUS_SINK_DISCONNECT_THRESHOLD = 16V (0.8*20V)

then tSinkDischargeBleed = 296ms. This means tSinkDischargeFull < 45ms required can be achieved with a full discharge pull down of 400 Ohm.

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October 20, 2015 - 43 - USB Type-C Port Controller

Interface Specification

VBUS_SINK_DISCONNECT_THRESHOLDvSafe5VtDisconnectDetectvSafe0VTimetSinkDischargeBleedtSinkDischargeFulltSafe5VtSafe0VCable unplugged

Figure 4-7. Automatic VBUS Sink Discharge by the TCPC after a Disconnect

4.4.5.4.3 Discharge by the Source TCPC during a Connection (Optional Normative)

While there is a valid Source-to-Sink connection, the TCPC acting as a Source shall discharge VBUS whenever POWER_CONTROL.ForceDischarge=1. The TCPC shall automatically disable discharge once the voltage on VBUS is below the value indicated by

VBUS_STOP_DISCHARGE_THRESHOLD. A Source TCPC transitioning from a higher to lower voltage shall disconnect the ForceDischarge in time to meet the USB PD vSrcValid requirement and remove the Force Discharge circuit.

The TCPC shall discharge Vbus to vSafe0V after a power on reset before applying the Rp. 4.4.5.4.4 Discharge by the Sink TCPC during a Connection (Optional Normative)

While there is a valid Source-to-Sink connection, the TCPC acting as a Sink shall reduce its current to less than iSnkSwapStdby within tSnkSwapStby (USB PD) when handling a Power Role Swap or Hard Reset. The TCPM shall write POWER_CONTROL.AutoDischargeDisconnect to 0 and COMMAND.DisableSinkVbus to disable the Sink disconnect detection and remove the Sink connection upon reception of or prior to transmitting a Power Role Swap or Hard Reset.

4.4.5.4.5 Bleed Discharge (Optional Normative)

Bleed discharge is enabled and disabled by the TCPM. The Bleed discharge is a low current discharge for providing a minimal load.

4.4.6 Status Registers

These registers indicate the state of the TCPC. These registers are set by the TCPC and read by the TCPM.

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October 20, 2015 - 44 - USB Type-C Port Controller

Interface Specification

The CC_STATUS and POWER_STATUS registers are not latched and are continually updated unless powered off. The FAULT_STATUS register is latched. 4.4.6.1 CC_STATUS (Required)

The TCPC updates this register on a Connect or Disconnect. The TCPC shall update the CC_STATUS register within tSetReg (Table 4-45) of a change in ROLE_CONTROL.DRP or a change on the CC1 or CC2 wires, after debounce.

The TCPM starts the DRP toggling by writing to the COMMAND register.

The TCPM reads this register upon detecting an Alert# and seeing the ALERT.CcStatus=1. The TCPC indicates the Connection status, the Connection result, and the current CC state in this register.

The TCPC shall set CC_STATUS.Looking4Connection = 0b when it has detected a potential connection. The Autonomous DRP toggling details are defined in Section 0.

The TCPM reads the Looking4Connection to determine if the TCPC is toggling Rp/Rd when operating as a DRP. The TCPM reads the CC_STATUS.ConnectResult to determine if a DRP TCPC is presenting an Rp or Rd. The TCPM shall read the CC1State and CC2State to determine the CC1 and CC2 states.

When reporting the state of the CC lines, the TCPC shall debounce for tTCPCfilter. The TCPC shall perform a minimal debounce and the TCPM must complete the debounce as defined in USB Type-C.

The TCPM as a Source detects a Sink attachment and detachment by reading Cc1State and Cc2State bits. The CC Status monitoring may be disabled per Section 4.8.3.

A TCPM which is using polling rather than Alerts should assume the data in the CC_STATUS register is not valid until at least tCcStatusDelay + tTCPCFilter (max) (Table 4-45) after the ROLE_CONTROL has been updated.

Table 4-19. Debounce requirements

tTCPCfilter

Min 4 Max 500 Units μs Table 4-20. CC_STATUS Register Definition

Bit(s) B7..6 B5 Name Reserved Looking4Connection Description Shall be set to zero by sender and ignored by receiver 0b: TCPC is not actively looking for a connection. A transition from '1' to '0' indicates a potential connection has been found. 1b: TCPC is looking for a connection (toggling as a DRP or looking for a connection as Sink/Source only condition) 0b: the TCPC is presenting Rp 1b: the TCPC is presenting Rd B4 ConnectResult Copyright ? 2015 USB 3.0 Promoter Group. All rights reserved.

Release 1.0

October 20, 2015 Bit(s) B3..2 - 45 - USB Type-C Port Controller

Interface Specification

Description Name CC2 State B1..0 CC1 State If (ROLE_CONTROL.CC2=Rp) or (ConnectResult=0) 00b: SRC.Open (Open, Rp) 01b: SRC.Ra (below maximum vRa) 10b: SRC.Rd (within the vRd range) 11b: reserved If (ROLE_CONTROL.CC2=Rd) or (ConnectResult=1) 00b: SNK.Open (Below maximum vRa) 01b: SNK.Default (Above minimum vRd-Connect) 10b: SNK.Power1.5 (Above minimum vRd-Connect) Detects Rp 1.5A 11b: SNK.Power3.0 (Above minimum vRd-Connect) Detects Rp 3.0A If ROLE_CONTROL.CC2=Ra, this field is set to 00b If ROLE_CONTROL.CC2=Open, this field is set to 00b This field always returns 00b if (Looking4Connection=1) or (POWER_CONTROL.EnableVconn=1 and TCPC_CONTROL.PlugOrientation=0). Otherwise, the returned value depends upon ROLE_CONTROL.CC2. If (ROLE_CONTROL.CC1 = Rp) or (ConnectResult=0) 00b: SRC.Open (Open, Rp) 01b: SRC.Ra (below maximum vRa) 10b: SRC.Rd (within the vRd range) 11b: reserved If (ROLE_CONTROL.CC1 = Rd) or ConnectResult=1) 00b: SNK.Open (Below maximum vRa) 01b: SNK.Default (Above minimum vRd-Connect) 10b: SNK.Power1.5 (Above minimum vRd-Connect) Detects Rp-1.5A 11b: SNK.Power3.0 (Above minimum vRd-Connect) Detects Rp-3.0A If ROLE_CONTROL.CC1=Ra, this field is set to 00b If ROLE_CONTROL.CC1=Open, this field is set to 00b This field always returns 00b if (Looking4Connection=1) or (POWER_CONTROL.EnableVconn=1 and TCPC_CONTROL.PlugOrientation=1). Otherwise, the returned value depends upon ROLE_CONTROL.CC1.

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