AHB总线规范详解

AHB总线规范读书笔记

中国科学院微电子研究所

韩健

序..............................................................................................................................................1 1、 2、 3、 4、 5、 6、 7、

概述...............................................................................................................................1 命名规则.......................................................................................................................1 总线结构.......................................................................................................................2 信号定义.......................................................................................................................3 总线操作概述...............................................................................................................5 基本传输.......................................................................................................................5 控制信号.......................................................................................................................7 7.1、传输类型..................................................................................................................7 7.2、Burst传输.................................................................................................................8 7.3、传输方向..................................................................................................................9 7.4、传输大小..................................................................................................................9 7.5、保护控制................................................................................................................10 8、地址译码...........................................................................................................................10 9、响应信号...........................................................................................................................11

9.1、传输完成................................................................................................................11 9.2、传输响应................................................................................................................11 10、仲裁.................................................................................................................................12 11、AHB组件........................................................................................................................13

11.1、slave......................................................................................................................13 11.2、master...................................................................................................................14 11.3、arbiter...................................................................................................................16 11.4、decoder.................................................................................................................17 12、其他.................................................................................................................................18

序

AHB总线规范是AMBA总线规范的一部分。AMBA总线规范是ARM公司提出的总线规范，被大多数SoC设计采用，它规定了AHB（Advanced High-performance Bus）ASB（Advanced System Bus）APB(Advanced Peripheral Bus)。AHB用于高性能、高时钟频率的系统结构，典型的应用如ARM核与系统内部的高速RAM，Nand Flash，DMA，Bridge的链接。APB用于连接外部设备，对性能要求不高，而考虑低功耗问题。ASB是AHB的一种替代方案，没有关注过它的使用，也没有见过其实际使用范例。因项目需要，阅读AHB总线规范，并做读书笔记。下面主要介绍AHB规范（AMBA Specification Rev2.0），预计今后加入APB协议部分。

1、 概述

AHB总线规范被用来作为SoC设计的内部高速总线，挂载高速设备，如图一所示。

图一、典型AHB总线系统

AHB总线具有如下特性：

? burst transfers

? split transactions

? single cycle bus master handover ? single clock edge operation ? non-tristate implementation

? wider data bus configurations (64/128 bits).

2、 命名规则

H：以H开头代表AHB总线定义的信号，以区别系统设计时的其他信号

n: 低电平有效。如HRESETn低电平有效的reset信号，也是AHB协议里唯一的低电

1

平有效信号。

x: 针对某一Master或Slave的信号，如HBUSREQx1为Master1的bus request信号。

3、 总线结构

AHB总线系统有Master、Slave和Infrastructure构成。Infrastructure由Arbiter，数据多路，地址控制多路，译码器构成。有需要占用总线的Master向Arbiter提出占用总线请求，Arbiter授权给指定的Master。任一时间周期只有一个Master可以接入总线，对其指定的Slave进行读写操作。总线统一规划slave的地址，译码器根据地址选择哪个slave与master进行数据通信。授权访问机制通过多路选择器实现：Arbiter将获得授权的master序号传输给地址和写数据多路，以选择哪个master接入总线；地址译码器根据master需要访问的地址选择master，并为写数据多路提供控制信号以选通相应的slave。下图取自ARM Specification p3-4，显示了三个Master，四个Slave的连接。

图二、多路选择器连接结构

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4、 信号定义

总线上传输的信号基本可以分为时钟复位信号、地址信号、控制信号、读写数据信号、申请信号、授权信号、反馈信号。表一列出了AHB总线的信号名称，用途等信息：

表一、AHB信号

Name

Source

To

Description

HCLK Bus clock HRESETn Reset HADDR[31:0] Address bus HTRANS[1:0] Transfer type HWRITE Transfer direction HSIZE[2:0] Transfer size

HBURST[2:0] Burst type HPROT[3:0] Protection control

HWDATA[31:0] Write data bus

Clock source

各个module

Clock source. 上升沿采样

Reset controller Master Master Master Master

各个module Reset signal. 低电平有效

decoder mux to Slave arbiter mux to Slave

mux to Slave

mux to Slave

32-bit system address bus.

Indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE or BUSY When HIGH this signal indicates a write and when LOW a read transfer

Indicates the size of the transfer, which is typically byte (8-bit), halfword (16-bit) or word (32-bit). The protocol allows for larger transfer sizes up to a maximum of 1024

Master

mux to Slave Arbiter

bits.

Master Indicates if the transfer forms part of a burst. Four, eight and sixteen beat bursts are supported and theburst may be either incrementing or wrapping. 保护机制 需要slave带有保护功能

（规范的slave接口结构图没有HPROT信号） The write data bus is used to transfer data from the master to the bus slaves during write operations. A minimum data bus width of 32 bits is recommended. However, this may easily be extended to allow for higher bandwidth operation.

Master mux to Slave

Master mux to Slave

HBUSREQx

Master Arbiter

A signal from bus master x to the bus arbiter which

3

Bus request

indicates that the bus master requires the bus. There is an HBUSREQx signal for each bus master in the system, up to a maximum of 16 bus masters.

HLOCKx Locked transfers HRDATA[31:0] Read data bus

Master Arbiter

When HIGH this signal indicates that the master requires locked access to the bus and no other master should be granted the bus until this signal is LOW.

Slave

mux to Master

The read data bus is used to transfer data from bus slaves to the bus master during read operations. A minimum data bus width of 32 bits is recommended. However, this may easily be extended to allow for higher bandwidth operation.

HREADY Transfer done

Slave

mux to Master Arbiter

When HIGH the HREADY signal indicates that a transfer has finished on the bus. This signal may be driven LOW to extend a transfer.

Note: Slaves on the bus require HREADY as both an input and an output signal.

HRESP[1:0] Transfer response

Slave

mux to Master Arbiter

The transfer response provides

additionalinformation on the status of a transfer.Four different responses are provided, OKAY,ERROR, RETRY and SPLIT.

HSPLITx[15:0] Split completion request

Slave

Arbiter

This 16-bit split bus is used by a slave to indicate to the arbiter which bus masters should be allowed to re-attempt a split transaction. Each bit of this split bus corresponds to a single bus master.

HSELx Slave select

Decoder

Slave

Each AHB slave has its own slave select signal and this signal indicates that the current transfer is intended for the selected slave. This signal is simply a combinatorial decode of the address bus.

HGRANTx Bus grant

Arbiter Master

This signal indicates that bus master x is currently the highest priority master. Ownership of the ddress/controlsignals changes at the end of a transfer when HREADY is HIGH, so a master gets access to the bus when both HREADY and HGRANTx are HIGH.

HMASTER[3:0] Master number

Arbiter

具有SPLIT功能的Slave

These signals from the arbiter indicate which bus master is currently performing a transfer and is used by the slaves which support SPLIT transfers to determine which master is attempting an access.

The timing of HMASTER is aligned with the timing of the address and control signals.

4

HMASTLOCK Locked sequence

Arbiter

具有SPLIT功能的Slave

Indicates that the current master is performing a locked sequence of transfers. This signal has the same timing as the HMASTER signal.

5、 总线操作概述

Master必须获得授权接入总线，才可以进行AHB传输。这一过程开始于总线向arbiter发出请求信号，然后arbiter决定哪个master可以获得授权接入总线。

获得授权的总线开始AHB传输，首先发出地址和控制信号。这些信号提供地址信息、传输方向和带宽以及burst类型。根据地址和控制信号确定master与哪个slave链接，进行数据传输，数据传输通过数据总线完成。为避免出现三态总线，AHB将读写总线分开，写数据总线用于从master到slave的数据传输，读数据总线用于从slave到master的数据传输。每比传输包括一个地址和控制周期，一个或多个数据周期。地址控制周期不能被扩展，因此slave必须在一个周期采样地址信号。数据周期可以通过HREADY信号扩展 。但HREADY为低时给传输加入一个等待状态以使slave获得额外的时间来提供或采样数据。另外slave通过响应信号HRESP反映传输状态。

一般情况下master完成的完整的burst传输，arbiter才会授权给其他的master接入总线。然而为避免过大的判决延迟，aibiter也可能打断burst传输。在这种情况下master必须请求再次接入总线以进行中断的burst的剩余部分的传输。

6、 基本传输

一笔传输由如下两部分组成： ? 地址段，一个周期

? 数据段，一个或多个周期，可以由HREADY发出请求延长一个周期 图三显示了一笔没有等待状态的简单的传输： ? HCLK上升沿master驱动地址和控制信号 ? HCLK下一周期上升沿slave采样地址和控制信息

? 获得地址和控制信息后，slave发出相应的放映信息，在第三个时钟上升沿被master采样，同时slave完成数据的读写操作。

这个简单的传输例子显示地址和数据传输发生在不同的周期。事实上，与这笔传输的地址段传输的同时发生的是上一笔传输的数据段传输。这种地址与数据的交叠是总线流水线的特征，允许高速传输，并为slave响应一笔传输留出充裕的时间。

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图四显示了带有等待状态的传输。写数据操作master必须在扩展的周期内保持总线上的数据稳定，而读数据操作则只需slave在传输完成前的一个周期提供有效的数据。 扩展数据周期的一个付效应是必须延长相应的下一笔传输的地址周期。图五显示了三笔不相关的传输。传输A、C为零等待传输，传输B加入了一个等待周期，因此相应的传输C的地址周期要进行扩展。

图三、简单传输

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图四、加入等待状态的传输

图五、多笔传输

7、 控制信号

7.1、传输类型

AHB规范定义了四种传输类型：IDLE、BUSY、RETRY、SPLIT，由信号HTRANS[1:0]定义。

HTRANS[1:0] 00 01

BUSY

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NONSEQ Type IDLE

Description

Indicates that no data transfer is required. The IDLE transfer type is used when a bus master is granted the bus, but does not wish to perform a data transfer. Slaves must always provide a zero wait state OKAY response to IDLE transfers and the transfer should be ignored by the slave. The BUSY transfer type allows bus masters to insert IDLE cycles in the middle of transfers. This transfer type indicates that the bus master is continuing with a burst of transfers, but the next transfer cannot take place immediately. When a master uses the BUSY transfer type the address and control signals must reflect the next transfer in the burst. The transfer should be ignored by the slave. Slaves must always provide a zero wait state OKAY response, in the same way that they respond to IDLE transfers.Indicates the first transfer of a burst or a single transfer. The address and control signals are unrelated to the previous transfer.Single transfers on the bus are treated as bursts of one and therefore the transfer type is NONSEQUENTIAL.

7

11

SEQ

The remaining transfers in a burst are SEQUENTIAL and the address is related to the previous transfer. The control information is identical to the previous transfer. The address is equal to the address of the previous transfer plus the size (in bytes). In the case of a wrapping burst the address of the transfer wraps at the address boundary equal to the size (in bytes) multiplied by the number of beats in the transfer (either 4, 8 or 16).

图六显示了含有不同传输类型的传输。Burst的第一笔传输为NONSEQ；下一周期master不能及时提供传输数据，因此为BUSY以延迟下一笔传输；第三笔传输master立即发出但是slave没有准备好，因此使用HREADY加入一个等待状态；第四笔传输不用等待直接完成。

图六、传输类型实例

7.2、Burst传输

AHB协议规定了4、8、16beat传输，以及未定义长度和single传输。其中beat数乘以transfer即为burst的长度。AHB协议支持incrementing和wrap burst，incrementing为递增的，没有边界；wrap将地址划分为传输burst长度的边界，超过边界部分折返回边界开始处。如传输一笔wrap4的burst，字长为4byte，第一笔传输的地址为0x34，会在16byte绕回，因此4笔传输的地址为0x34，0x38，0x3c，0x30。表三为Burst信号编码说明。

表三、Burst信号编码

HBURST[2:0] Type 000 SINGLE001

INCR

Description

Single transfer

Incrementing burst of unspecified length

010 WRAP4 4-beat wrapping burst 011

INCR4

4-beat incrementing burst

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图十一、slave时序图

11.2、master

图十二和图十三分别为master的接口图和时序图，图十四为master授权请求时序图。

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图十二、master接口图

图十三、master时序图

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图十四、授权请求时序图

11.3、arbiter

图十五和图十六分别为master的接口图和时序图。

图十五、arbiter接口图

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图十六、arbiter时序图

11.4、decoder

图十七和图十八分别为master的接口图和时序图。

图十七、decoder接口图

图十八、decoder时序图

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12、其他

AHB规范还有许多内容在这里没有详细写出，如SPLIT传输时arbiter和slave的工作情况，传输数据宽度与总线宽度不一致的问题的解决，Reset时序。这些问题都很重要，但是目前的项目还不需要考虑，因此没有写出。

我在读IEEE802.16协议和AMBA协议时遇到问题，在网上搜索资料，找到了一些中文的读书笔记。看到前辈们写的资料，让我受益良多。因此我在学习AHB规范的同时，做以上笔记，梳理知识脉络，记录学习心得，贡献出来供大家研究AHB规范。这篇笔记原本想写成总结的形式，但是写着写着竟变成对AHB规范的翻译了，而我又极力避免这种翻译，结果有些不伦不类。

第一次写了这么长的读书笔记也是一件值得庆祝的事。我写完之后很有成就感，并提倡

我的邮箱为大家也在学习的同时写读书笔记分享知识。如果内容有不对之处欢迎批评指正，

youlicar@163.com

Reference：

ARM，AMBA Specification Rev2.0 吴欣龙，Introduction to AMBA Bus System

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