FPGA可编程逻辑器件芯片XC2S200E-FG456中文规格书

RocketIO GTX Transceiver User Guide UG198 (v3.0) October 30, 2009

Decision Feedback Equalization

Use Mode – Fixed Tap Mode

This mode requires that DFE_CFG[9] = 1 (DFETAPx value override). It is recommended that DFE_CFG[8] = 0 (optimized DFE clock delay calibration). The remaining DFE_CFG bits must be held at their default values.

The values to be written to the DFE taps are applied to DFETAPx0/1; DFETAPxMONITOR0/1 reflects the value entered.

The chip-to-chip and backplane application examples provide starting points for setting DFETAP1 and RXEQMIX0/1 based on the trace length and the associated loss of the channel. DFETAP2, DFETAP3, and DFETAP4 are set to 0 in these examples. For channels with different characteristics or lengths than given in the examples, the designer should use the example with the closest match as a starting point.

Either the GTX Wizard example design or IBERT can be used to fine-tune the settings to the user’s particular channel.

Example RX Linear Equalizer and DFE Settings for Chip-to-Chip Applications

Table 7-7 provides DFETAP1 and RXEQMIX settings for 4.25Gb/s operation for chip-to-chip applications.In most chip-to-chip applications operating at 4.25Gb/s with a nominal trace length of up to 48 inches and around 13.25dB of attenuation at 2.125GHz, RX linear equalization is sufficient without any need for DFE.

Table 7-8 provides DFETAP1 and RXEQMIX settings for 5Gb/s operation for chip-to-chip applications.Table 7-7:

DFETAP1 and RXEQMIX at 4.25 Gb/s for Chip-to-Chip Applications

Nominal Trace Length on

FR4 Substrate (inches [mm])

Loss (dB) @ 2.125 GHz

DFETAP1

RXEQMIX = 10

RXEQMIX = 00

18 [457.2]50028 [711.2]7.510038 [965.2]10.5N/A 048 [1219.2]

13.25

N/A

Notes:

1.GTX TXDIFFCTRL = 111 and TXPREEMPHASIS = 000 (maximum TX swing and no TX pre-emphasis).

Table 7-8:

DFETAP1 and RXEQMIX at 5 Gb/s for Chip-to-Chip Applications

Nominal Trace Length on

FR4 Substrate (inches [mm])

Loss (dB) @ 2.5 GHz

DFETAP1

RXEQMIX = 10

RXEQMIX = 00

18 [457.2] 5.750028 [711.2]8.7510038 [965.2]12.25N/A 048 [1219.2]

15.5

N/A

5

Notes:

1.GTX TXDIFFCTRL = 111 and TXPREEMPHASIS = 000 (maximum TX swing and no TX pre-emphasis).

RocketIO GTX Transceiver User Guide UG198 (v3.0) October 30, 2009RX OOB/Beacon Signaling

Table7-14 defines the RX OOB/beacon signaling attributes. Table 7-14:RX OOB/Beacon Signaling Attributes

Attribute Type Description

OOB_CLK_DIVIDER Integer Sets the squelch clock rate. The squelch clock must be set between 25MHz and 37.5MHz, as close to 25MHz as possible for the SATA OOB detector to work correctly.

Squelch Clock rate = CLKIN/OOB_CLK_DIVIDER

Valid pider settings are 1, 2, 4, 6, 8, 10, 12, and 14.

OOBDETECT_THRESHOLD_0 OOBDETECT_THRESHOLD_13-bit Binary

Sets the minimum differential voltage between RXN and RXP.

When the differential voltage drops below this level, the

incoming signal is considered an OOB signal. This 3-bit binary

encoded attribute has the following nominal values of the OOB

threshold voltage(1):

Value OOB Nominal Threshold Voltage [mV]

000 – 101Not supported

110 (default)90

11195

RX_STATUS_FMT_0 RX_STATUS_FMT_1String

Defines which status encoding is used:

PCIE: PCI Express encoding

SATA: SATA encoding

SATA_BURST_VAL_0 SATA_BURST_VAL_13-bit Binary

Number of bursts required to declare a COM match. The default

for SATA_BURST_VAL is 4, which is the burst count specified in

SATA for COMINIT, COMRESET, and COMWAIT.

SATA_IDLE_VAL_0 SATA_IDLE_VAL_13-bit Binary

Number of idles required to declare a COM match. Each idle is an

OOB signal with a length that matches either

COMINIT/COMRESET or COMWAIT. When the SATA detector

starts to count one type of idle (for example,

COMRESET/COMINIT), it resets the count if it receives the other

type. This value defaults to 3 to match the SATA specification.

SATA_MAX_BURST_0 SATA_MAX_BURST_1Integer

Sets the threshold for the SATA detector to reject a burst in terms

of squelch clock cycles. SATA_MAX_BURST has valid values

between 1 and 61 (the default is 7) and must be greater than

SATA_MIN_BURST. See the “Description” section to learn how

to calculate the best value for a given squelch clock rate.

SATA_MAX_INIT_0 SATA_MAX_INIT_1Integer

Sets the maximum time allowed for a COMINIT/COMRESET

idle for the SATA detector in terms of squelch clock cycles.

SATA_MAX_INIT has valid values between 1 and 61 (the default

is 22) and must be greater than SATA_MIN_INIT. See the

“Description” section to learn how to calculate the best value for

a given squelch clock rate.

SATA_MAX_WAKE_0 SATA_MAX_WAKE_1Integer

Sets the maximum time allowed for a COMWAKE idle for the

SATA detector in terms of squelch clock cycles.

SATA_MAX_WAKE has valid values between 1 and 61 (the

default is 7) and must be greater than SATA_MIN_WAKE. See the

“Description” section to learn how to calculate the best value for

a given squelch clock rate.

Serial In to Parallel Out

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

Configurable Loss-of-Sync State Machine

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009Configurable Clock Correction

Description

Enabling Clock Correction

Each GTX transceiver includes a clock correction circuit that performs clock correction by controlling the pointers of the RX elastic buffer. To use clock correction, RX_BUFFER_USE is set to TRUE to turn on the RX elastic buffer, and CLK_CORRECT_USE is set to TRUE to turn on the clock correction circuit.

Clock correction is triggered when the RX elastic buffer latency is too high or too low, and the clock correction circuit detects a match sequence. To use clock correction, the clock correction circuit must be configured to set the following items:

?

RX elastic buffer limits ?Clock correction sequence

Setting RX Elastic Buffer Limits

The RX elastic buffer limits are set using CLK_COR_MIN_LAT (minimum latency) and CLK_COR_MAX_LAT (maximum latency). When the number of bytes in the RX elastic buffer drops below CLK_COR_MIN_LAT, the clock correction circuit writes an additional CLK_COR_SEQ_2_1_0CLK_COR_SEQ_2_1_110-bit Binary The CLK_COR_SEQ_2 attributes are used in conjunction with

CLK_COR_SEQ_2_ENABLE to define the second clock correction

sequence. This second sequence is used as an alternate sequence for

clock correction when CLK_COR_SEQ_2_USE is TRUE: if either

sequence 1 or sequence 2 arrives, clock correction is performed.

The sequence is made up of four subsequences. Each subsequence is

10 bits long. The rules for setting the subsequences depend on

INTDATAWIDTH and RX_DECODE_SEQ_MATCH. See the

“Description” section to learn how to set clock correction

subsequences.

Not all subsequences need to be used. CLK_COR_DET_LEN

determines how much of the sequence is used for a match. If

CLK_COR_DET_LEN = 1, only CLK_COR_SEQ_2_1 is used.

CLK_COR_SEQ_2_ENABLE can be used to make parts of the

sequence don't care. If CLK_COR_SEQ_2_ENABLE[k] is 0,

CLK_COR_SEQ_2_k is a don't care byte subsequence and is always

considered to be a match.

CLK_COR_SEQ_2_2_0CLK_COR_SEQ_2_2_1CLK_COR_SEQ_2_3_0CLK_COR_SEQ_2_3_1CLK_COR_SEQ_2_4_0CLK_COR_SEQ_2_4_1CLK_COR_SEQ_2_ENABLE_0CLK_COR_SEQ_2_ENABLE_14-bit

Binary CLK_COR_SEQ_2_USE_0CLK_COR_SEQ_2_USE_1Boolean

Determines if the second clock correction sequence is to be used.

When set to TRUE, the second clock correction sequence also

triggers clock correction.

RX_DECODE_SEQ_MATCH_0

RX_DECODE_SEQ_MATCH_1Boolean Determines whether sequences are matched against the input to the

8B/10B decoder or the output. Used for the clock correction circuit

and the channel bonding circuit.TRUE: Sequences are matched against the output of the 8B/10B

decoder. K characters and disparity information is used. Bit

ordering of the 8B/10B output is used.

FALSE: Sequences are matched against unencoded data. Bit

ordering is as for an unencoded parallel interface.

Table 7-38:Clock Correction Attributes (Cont’d)

Attribute Type Description

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