emmc_v451_153b_4gb 8gb_pb——MTFC4GMCDM-1M WT

e·MMC? Memory

MTFC4GMCDM-1M WT, MTFC8GLCDM-1M WT Features

?MultiMediaCard (MMC) controller and NAND Flash ?153-ball TFBGA

(RoHS compliant, "green package")?V CC : 2.7–3.6V

?V CCQ (dual voltage): 1.65–1.95V; 2.7–3.6V ?Temperature ranges

–Operating temperature: –25?C to +85?C –Storage temperature: –40?C to +85?C

MMC-Specific Features

?JEDEC/MMC standard version 4.51-compliant (JEDEC Standard No. 84-B451) – SPI mode not supported (see 856120c5866fb84ae45c8de2/sites/default/files/docs/JESD84-B451.pdf)

–Advanced 11-signal interface

–x1, x4, and x8 I/Os, selectable by host

–SDR/DDR modes up to 52 MHz clock speed –HS200 mode

–Command classes: class 0 (basic); class 2 (block read); class 4 (block write); class 5 (erase);class 6 (write protection); class 7 (lock card)–Temporary write protection

–Boot operation (high-speed boot)–Sleep mode

–Replay-protected memory block (RPMB)–Secure erase and secure trim –Hardware reset signal

–Multiple partitions with enhanced attribute –Permanent and power-on write protection –High-priority interrupt (HPI)

Figure 1: Micron e ·MMC Device

MMC-Specific Features (Continued)–Background operation –Reliable write

–Discard and sanitize –Extended partitioning –Context ID –Data TAG

–Packed commands

–Backward compatible with previous MMC ?ECC and block management implemented

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Products and specifications discussed herein are subject to change by Micron without notice.

e ·MMC Performance and Current Consumption

Table 1: MLC Partition Performance

Note:

1.Bus in x8 I/O mode. Sequential access of 1MB chunk; random access of 4KB chunk over 1GB span. Additional

performance data, such as system performance on a specific application board, will be provided in a sepa-rate document upon customer request.

Table 2: Current Consumption

Note:

1.Bus in x8 I/O mode; 25°C; V CCQ = 1.95V. Measurements done as average RMS current consumption.

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Part Numbering Information

Micron ? e ·MMC memory devices are available in different configurations and densities.Figure 2: e ·MMC Part Numbering

MT FC xx

x

x xx xx -x

ES

Micron Technology

FC = NAND Flash + Controller NAND Flash Density

NAND Flash Component Controller ID Package Codes

Design Revision Production Status

Wafer Process Applied

Operating Temperature Range Special Options

xx

Table 3: Ordering Information

Device Marking

Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead,an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: 856120c5866fb84ae45c8de2/decoder.

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General Description

Micron e ·MMC is a communication and mass data storage device that includes a Multi-MediaCard (MMC) interface, a NAND Flash component, and a controller on an ad-vanced 11-signal bus, which is compliant with the MMC system specification. Its low cost, small size, Flash technology independence, and high data throughput make

e ·MMC ideal for smartphones, digital cameras, PDAs, MP3s, and other portable applica-tions.

The nonvolatile e ·MMC draws no power to maintain stored data, delivers high perform-ance across a wide range of operating temperatures, and resists shock and vibration dis-ruption.Micron Confidential and Proprietary

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Signal Descriptions

Table 4: Signal Descriptions

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153-Ball Signal Assignments

Figure 3: 153 Ball (Top View, Ball Down)

A B C D E F G H J K L M N P

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Notes:

1.Some previous versions of the JEDEC product or mechanical specification had defined

reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the pre-vious specifications could have been connected to ground on the system board. To ena-ble new feature introduction, some of these balls are assigned as RFU in the v4.4 me-chanical specification. Any new PCB footprint implementations should use the new ball assignments and leave the RFU balls floating on the system board.

2.V CC , V CCQ , V SS , and V SSQ balls must all be connected on the system board.

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Package Dimensions

Figure 4: 153-Ball TFBGA – 11.50mm x 13.00mm x 1.20mm (Package Code: DM)

Ni/Au plated on pitch,

no solder balls.

Note: 1.Dimensions are in millimeters.

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Architecture

Figure 5: e ·MMC Functional Block Diagram

V V CC V CCQ DAT[7:0]V SS 1

V SSQ 1Note: 1.V SS and V SSQ are internally connected.

MMC Protocol Independent of NAND Flash Technology

The MMC specification defines the communication protocol between a host and a de-vice. The protocol is independent of the NAND Flash features included in the device.The device has an intelligent on-board controller that manages the MMC communica-tion protocol.

The controller also handles block management functions such as logical block alloca-tion and wear leveling. These management functions require complex algorithms and depend entirely on NAND Flash technology (generation or memory cell type).

The device handles these management functions internally, making them invisible to the host processor.

Defect and Error Management

Micron e ·MMC incorporates advanced technology for defect and error management. If a defective block is identified, the device completely replaces the defective block with one of the spare blocks. This process is invisible to the host and does not affect data space allocated for the user.

The device also includes a built-in error correction code (ECC) algorithm to ensure that data integrity is maintained.

To make the best use of these advanced technologies and ensure proper data loading and storage over the life of the device, the host must exercise the following precautions:?Check the status after WRITE, READ, and ERASE operations.

?Avoid power-down during WRITE and ERASE operations.

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OCR Register

The 32-bit operation conditions register (OCR) stores the V DD voltage profile of the card and the access mode indication. In addition, this register includes a status information bit.

Table 5: OCR Parameters

Note: 1.OCR = C0FF8080h after the device has completed power-up.

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CID Register

The card identification (CID) register is 128 bits wide. It contains the device identifica-tion information used during the card identification phase as required by e ·MMC proto-col. Each device is created with a unique identification number.

Table 6: CID Register Field Parameters

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CSD Register

The card-specific data (CSD) register provides information about accessing the device contents. The CSD register defines the data format, error correction type, maximum da-ta access time, and data transfer speed, as well as whether the DS register can be used.The programmable part of the register (entries marked with W or E in the following ta-ble) can be changed by the PROGRAM_CSD (CMD27) command.

Table 7: CSD Register Field Parameters

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Table 7: CSD Register Field Parameters (Continued)

Notes:

1.R = Read-only;

R/W = One-time programmable and readable;

R/W/E = Multiple writable with value kept after a power cycle, assertion of the RST_n signal, and any CMD0 reset, and readable 2.Reserved bits should be read as 0.

3.CMD0 restriction: CMD0 (SW RESET) is not supported during programming command. If

SW RESET is issued during programming commands, a power cycle is required.

4.The I PEAK, max driving capability can be modified according to the actual capacitive load

on the e ·MMC interface signals in the user application board, using CMD4. In HS200mode, the driver strength value is set in EXT_CSD[185], using CMD6.

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ECSD Register

The 512-byte extended card-specific data (ECSD) register defines device properties and selected modes. The most significant 320 bytes are the properties segment. This seg-ment defines device capabilities and cannot be modified by the host. The lower 192bytes are the modes segment. The modes segment defines the configuration in which the device is working. The host can change the properties of modes segments using the SWITCH command.

Table 8: ECSD Register Field Parameters

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Table 8: ECSD Register Field Parameters (Continued)

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Table 8: ECSD Register Field Parameters (Continued)

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Table 8: ECSD Register Field Parameters (Continued)

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Table 8: ECSD Register Field Parameters (Continued)

Notes:

1.R = Read-only;

R/W = One-time programmable and readable;

R/W/E = Multiple writable with the value kept after a power cycle, assertion of the RST_n signal, and any CMD0 reset, and readable;

R/W/C_P = Writable after the value is cleared by a power cycle and assertion of the RST_n signal (the value not cleared by CMD0 reset) and readable;

R/W/E_P = Multiple writable with the value reset after a power cycle, assertion of the RST_n signal, and any CMD0 reset, and readable;

W/E_P = Multiple writable with the value reset after power cycle, assertion of the RST_n signal, and any CMD0 reset, and not readable 2.Reserved bits should be read as 0.

3.Micron has tested power failure under best application knowledge conditions with posi-tive results. Customers may request a dedicated test for their specific application condi-tion.

4.The t IH parameter is 1.2ns. Refer to the JEDEC specification for the output timing dia-gram.

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DC Electrical Specifications – Device Power

The device current consumption for various device configurations is defined in the power class fields of the ECSD register.

V CC is used for the NAND Flash device and its interface voltage; V CCQ is used for the controller and the e ·MMC interface voltage.

Figure 6: Device Power Diagram

CLK CMD

DAT[7:0]

V CC

V DDIM

V CCQ

RST_n

Table 9: Absolute Maximum Ratings

Table 10: Power Domains

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Table 11: Capacitor and Resistance Specifications

Notes:

856120c5866fb84ae45c8de2ed to prevent bus floating.

2.If host does not use H/W RESET (RST_n), pull-up resistance is not needed on RST_n line

(Extended_CSD[162] = 00h).3.Impedance match.

4.The coupling capacitor should be connected with V CCQ and V SSQ as closely as possible.

5.The coupling capacitor should be connected with V CC and V SS as closely as possible.

6.The coupling capacitor should be connected with V DDIM and V SS as closely as possible.

Product Revision

The table below lists JEDEC v4.51 features not supported in the specified product revi-sion. See the full JEDEC/MMC Standard No. 84-B451 specification at 856120c5866fb84ae45c8de2/sites/default/files/docs/JESD84-B451.pdf for more details regarding v4.51 features.

Table 12: Product Revision

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Revision History

Rev. H – 6/14

?Changed "VFBGA" to "TFBGA" in the Features section

Rev. G – 4/14

?Added the "Absolute Maximum Ratings" table to the DC Electrical Specifications sec-

tion

Rev. F – 3/14

?Added updated specifications to the Performance and Current Consumption tables

Rev. E – 10/13

?Added t IH parameter note to ECSD register

Rev. D – 9/13

?Preliminary to production

Rev. C – 8/13

?Removed '"real-time clock" row from cover page

Rev. B – 4/13

?Part number fix

Rev. A – 4/13

?Initial release

8000 S. Federal Way, P .O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

856120c5866fb84ae45c8de2/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.Although considered final, these specifications are subject to change, as further product development and data characterization some-

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