基于quartus2十六进制8位数码管扫描显示频率计设计

Ftctrl时钟控制模块的vhdl代码：(clkk一定要是1s周期脉冲啊，没有的话就拿分频器分频) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FTCTRL IS

PORT (CLKK : IN STD_LOGIC; CNT_EN : OUT STD_LOGIC; RST_CNT: OUT STD_LOGIC; Load : OUT STD_LOGIC); END FTCTRL;

ARCHITECTURE behav OF FTCTRL IS SIGNAL Div2CLK : STD_LOGIC; BEGIN

PROCESS ( CLKK ) BEGIN

IF CLKK'EVENT AND CLKK = '1' THEN Div2CLK <= NOT Div2CLK; END IF; END PROCESS;

PROCESS (CLKK ,Div2CLK) BEGIN

IF CLKK='0' AND Div2CLK='0' THEN RST_CNT<='1'; ELSE RST_CNT <='0'; END IF; END PROCESS;

Load <= NOT Div2CLK; CNT_EN <=Div2CLK; END behav;

4位计数器cnt4b的vhdl代码： LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT4B IS

PORT (Fin,CLR,ENABL: IN STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT : OUT STD_LOGIC ); END CNT4B;

ARCHITECTURE behav OF CNT4B IS BEGIN

PROCESS(Fin,CLR,ENABL)

VARIABLE Q : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

IF CLR='1' THEN Q := (OTHERS=>'0'); ELSIF Fin'EVENT AND Fin='1' THEN IF ENABL='1' THEN IF Q<15 THEN Q :=Q+1; ELSE Q := (OTHERS=>'0'); END IF;

END IF; END IF; IF Q=\ ELSE COUT<='0'; END IF; DOUT <= Q; END PROCESS; END behav;

分频器模块fp的vhdl代码： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fp IS

PORT( inclk : IN STD_LOGIC; outclk : OUT STD_LOGIC); END fp;

ARCHITECTURE a OF fp IS

SIGNAL fp : STD_LOGIC_VECTOR(3 downto 0); SIGNAL f : STD_LOGIC; BEGIN

PROCESS(inclk) BEGIN IF inclk'event and inclk='0' THEN IF fp=4 then fp<=\ f<=not f; ELSE fp<=fp+1;

END IF; --“4”那里自己改，outclk频率是inclk频率的1/[2*(4+1)] END IF; END PROCESS; outclk<=f; END a;

---------------------------------------------------------------------------------------------------------------------------------

缓存信号输出模块topreg32b的vhdl代码： LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY TOPREG32B IS

PORT (LK : IN STD_LOGIC;

DIN :IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT0 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

DOUT1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END TOPREG32B;

ARCHITECTURE ONE OF TOPREG32B IS

SIGNAL Q0 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL Q1 : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL H1 : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN A:PROCESS (LK)

VARIABLE H : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN

IF LK='1' AND LK'EVENT THEN

IF H<=7 THEN H:=H+1;DOUT0<=Q0; DOUT1<=Q1;

ELSE H:= (OTHERS=>'0'); END IF; END IF; H1<=H;

END PROCESS A ; B:PROCESS (H1,DIN) BEGIN CASE H1 IS

WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN OTHERS => NULL; END CASE;

END PROCESS B; END ONE;

数码管decoder译码模块的vhdl代码： library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity decoder is

port(a : in std_logic_vector(3 downto 0); clk : in std_logic;

led7s : out std_logic_vector(6 downto 0); K : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); end;

architecture one of decoder is

signal h1: std_logic_vector(2 downto 0); signal k1 : std_logic_vector( 8 downto 0); begin

D:process(a)

begin case a is

when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when\ when others=>null; end case; end process D; B:PROCESS (clk)

VARIABLE H : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN

IF cLK='1' AND cLK'EVENT THEN IF H<=7 THEN H:=H+1; ELSE H:= (OTHERS=>'0'); END IF; END IF; H1<=H;

END PROCESS B ; C:PROCESS (H1) BEGIN CASE H1 IS

WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN OTHERS => NULL; END CASE;

END PROCESS C; k<=k1(8 downto 1); end;

然后上顶层文件原理图：

--------------------------------------------------------------------------------------------------------------------------------- 不知道啥是cnt32b？那是由8个cnt4b计数器组成的。再上图：

寄语：建立工程，元件例化，分层设计那些quartus ii里面最基本的你总不能不会吧？？？所以这里都省去不打了，基本上要给的就那么多。

本文来源：https://www.bwwdw.com/article/tg5g.html