TL7790 - LPDDR3 - 800M - Test - report - v1.00 - 20160125 -

Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 TL7790 LPDDR3 Test Report Approve Editor/DP Checker Approver Sign Philip/HW Jack Date 2015.12.31 Distribute Department □CEO □HR ? IC Design ? Hardware ?Soft ? QC ?AE Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 Modify history Date 2015-11-25 Version v1.00 Descriptions First version Revised by XX ATTENTION ACTIONS RECIPIENT： THIS DOCUMENT IS FOR INTERNAL DISTRIBUTION ONLY. OTHER DISTRIBUTION REQUIRES APPROVAL BY NUFRONT. NOTICE: The subject matter herein is covered by one or more pending or issued patents. By this document， NUFRONT does not convey any license under its rights of others，nor does it assume liability arising from the application or use of the subject matter herein. NUFRONT reserves the right to make changes to this document at any time. Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 Contents TL7790 LPDDR3 TEST REPORT .......................................................................................................................... 1 1. PRE-SPECIFICATION ......................................................................................................................................... 4 1.1. 1.2. 1.3. 1.4. 2. 2.1. Purpose .............................................................................................................................................. 4 Related guys ....................................................................................................................................... 4 Reference design documents ............................................................................................................. 4 Test tools and measurement instrument............................................................................................ 4 LPDDR3 functions ............................................................................................................................... 5 DRAM PARAMETER VERIFY ............................................................................................................................... 5 2.1.1. Simplify state diagram introduce ................................................................................................................... 5 2.1.2. Power on and off ............................................................................................................................................ 6 2.1.3. Initialization .................................................................................................................................................... 6 2.1.4. State power consumption .............................................................................................................................. 6 2.1.5. Memory test loop ........................................................................................................................................... 7 2.2. DC operating conditions ..................................................................................................................... 7 2.2.1. LPDDR3 VDD power DC conditions ................................................................................................................ 7 2.2.2. LPDDR3 VREF power DC conditions ............................................................................................................... 7 2.3. AC and DC input measurement level .................................................................................................. 8 2.3.1. Single ended AC and DC input level ............................................................................................................... 8 2.3.2. Differential AC and DC input level ................................................................................................................ 14 2.3.3. Differential Input Cross Point Voltage .......................................................................................................... 17 2.3.4. Slew Rate Definitions for Input Signals ......................................................................................................... 19 2.4. AC and DC output measurement level ............................................................................................. 21 2.4.1. Single Ended AC and DC Output Levels ........................................................................................................ 21 2.4.2. Differential AC and DC Output Levels ........................................................................................................... 25 2.4.3. Slew Rate Definitions for output Signals ...................................................................................................... 26 2.4.4. Output buffer characteristics ....................................................................................... 错误！未定义书签。 2.5. Electrical characteristics and AC timings.......................................................................................... 32 2.5.1. Clock parameters and AC timing .................................................................................................................. 32 2.5.2. CA/CS setup and hold ................................................................................................................................... 35 2.5.3. DQ/DM setup and hold ................................................................................................................................ 37 3. 4. DRAM DEVICES COMPATIBLE TEST ................................................................................................................... 39 VERIFY RESULT .............................................................................................................................................. 40 4.1. 4.2. Fail list .............................................................................................................................................. 40 Any issue .......................................................................................................................................... 40 5. SUMMARY ................................................................................................................................................... 40 Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 1. Pre-Specification 1.1. Purpose Verify TL7790 DDR PHY and DDR controller function well and performance 1.2. Related guys IC design：Yanyun System design：Philip Software design：Meinan 1.3. Reference design documents 《TL7790_Datasheet_v1.00.pdf》 1.4. Test tools and measurement instrument Oscilloscope：Agilent-DSA91304A Oscilloscope probe：Agilent Diff probe 1169A,Single probe N2795A Test EVB: TL7790_EVB_V1.0 Test soft version: U-Boot 2015.10-00596-g48b777b (Jan 07 2016 - 09:35:12 +0800) The revision of gic distributor is: 0x0100143b Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 2. DRAM parameter verify 2.1. LPDDR3 functions 2.1.1. Simplify state diagram introduce

Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 2.1.2. Power on and off Whenever power on or off sequence, the Voltage ramp conditions must flow the JEDEC specifications VDD1 must greater than VDD2 200mV VDD1 and VDD2 must greater than VDDCA/VDDQ 200mV Vref must always be less than all other supply voltage Figure-1: LPDDR3 power up sequence NOTE 1 Ta is the point when any power supply first reaches 300mV. NOTE 2 Noted conditions apply between Ta and power-off (controlled or uncontrolled). NOTE 3 Tb is the point at which all supply and reference voltages are within their defined operating ranges. NOTE 4 Power ramp duration tINIT0 (Tb - Ta) must not exceed 20ms. NOTE 5 The voltage difference between any of VSS, VSSQ, and VSSCA pins must not exceed 100mV. Figure-2: LPDDR3 power off sequence NOTE 1 While powering off, CKE must be held LOW; all other inputs must be between VILmin and VIHmax. NOTE 2 The device outputs remain at High-Z while CKE is held LOW. NOTE 3 Tx is the point where any power supply drops below the minimum value specified. NOTE 4 Tz is the point where all power supplies are below 300mV. After Tz, the device is powered off 2.1.3. Initialization Total sequence procedure contains power-on---reset command--- MRRs and DAI---ZQ CAL---Normal OP. Table-1: LPDDR3 initialization results DDR initialization Test result LPDDR3-800 LPDDR3-1066 LPDDR3-1333 LPDDR3-1600 2.1.4. State power consumption Table-2: Self-refresh, idle power down, active R/W consumption and leakage current Power consumption LPDDR3-800 VDD1=1.8V VDD2+CA+DQ=1.2V LPDDR3-1066 VDD1=1.8V VDD2+CA+DQ=1.2V Self-refresh(mA) Idle power down(mA) Active R/W(mA) Leakage(uA) Note that For CA, CKE, CS_n, CK_t, CK_c. Any input pins voltage must between 0 to VDDCA, but although DM is for input only, the DM leakage shall match the DQ and DQS_t/DQS_c output leakage specification. Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 2.1.5. Memory test loop Memory test under U-BOOT, test device total memory density 3 loop Table-3: Memory test loop result Memory test loop Test result LPDDR3-800 LPDDR3-1066 LPDDR3-1333 LPDDR3-1600 Pass 2.2. DC operating conditions Test voltage at the ball of DRAM package as close as possible and the recommended voltage is inclusive the noise up to 1M at the ball of DRAM package 2.2.1. LPDDR3 VDD power DC conditions Table-4: LPDDR3 DC operation conditions Symbol VDD1 VDD2 VDDCA VDDQ LPDDR3-1066 Core power1 Core power2 Input buffer power IO buffer power Test DC(V) 1.79845 1.19816 1.19816 1.19816 Recommended DC(V) 1.70-1.95 1.14-1.30 1.14-1.30 1.14-1.30 Test ripple(mV) 45.211 46.501 46.501 46.501 Recommended ripple(mV) ±50mV ±50mV ±50mV ±50mV NOTE 1 VDD1 uses significantly less current than VDD2. NOTE 2 the voltage range is for DC voltage only. DC is defined as the voltage supplied at the DRAM and is inclusive of all noise up to 1MHz at the DRAM package ball. 2.2.2. LPDDR3 VREF power DC conditions Table-5: LPDDR3 DC operation conditions Symbol VRefCA VRefDQ LPDDR3-1066 for CA and CS for DQ/DM ODT Test DC(V) 0.599 0.599 Recommended DC(V) (0.49-0.51)*VDDCA (0.49-0.51)*VDDDQ Test ripple(mV) ±10 ±10 Recommended ±12mV ±12mV Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 2.3. AC and DC input measurement level 2.3.1. Single ended AC and DC input level Note that CA0-9, CLK and CS VDD stands for VDDCA, DC voltage refer to VREFCA but CKE DC voltage refer to VDDCA. Table-6: AC and DC input levels for CA/CKE 1.AC and DC input levels for A0 /CKE0 Symbol VIHCA(AC) VILCA(AC) VIHCA(DC) VILCA(DC) VIHCKE VILCKE LPDDR3-1600 AC input logic high AC input logic low DC input logic high DC input logic low CKE Input High Level CKE Input Low Level Test voltage(V) 1.42 -0.56 1.27 -0.15 1.08 -0.02 Recommended voltage(V) 0.75-1.55 -0.35-0.45 0.7-1.2 0-0.5 0.78-1.55 -0.35-0.42 table6_VIHCA0_AC Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table6_VIHCA0_DC table6_VIHCKE0 Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 2. AC and DC input levels for A0 /CKE0 Symbol VIHCA9(AC) VILCA9(AC) VIHCA9(DC) VILCA9(DC) LPDDR3-1600 AC input logic high AC input logic low DC input logic high DC input logic low Test voltage(V) 1.46 -0.41 0.91 -0.14 Recommended voltage(V) 0.75-1.55 -0.35-0.45 0.7-1.2 0-0.5 table6_VIHCA9_AC table6_VIHCA9_DC

Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 Note that DQ, DM stands for VDDQ but DQ and DQM DC voltage refer to VREFDQ, VODTR=VDDQ*(2Ron+Rtt)/(Ron+Rtt) Table-1: AC and DC input levels for DQ/DQM 1. AC and DC input levels for DQ9 Symbol VIHDQ(AC) VILDQ(AC) VIHDQ(DC) VILDQ(DC) VREFDQ(ODT EN) LPDDR3-1600 AC input logic high AC input logic low DC input logic high DC input logic low DC input logic low Test voltage(V) 1.11 -0.12 0.96 - 0.63 Recommended voltage(V) 0.75-1.55 -0.35-0.45 0.7-1.2 0-0.5 ±0.01*VDDQ+0.5*VODTR table7_VIHDQ9_AC Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table7_VIHDQ9_DC 2. AC and DC input levels for DM1 Symbol VIHDQM1(AC) VILDQM1(AC) VIHDQM1(DC) VILDQM1(DC) VREFDQM(ODT EN) LPDDR3-1600 AC input logic high AC input logic low DC input logic high DC input logic low DC input logic low Test voltage(V) 1.51 -0.16 0.87 - 0.61 Recommended voltage(V) 0.75-1.55 -0.35-0.45 0.7-1.2 0-0.5 ±0.01*VDDQ+0.5*VODTR Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table7_VIHDM1_AC table7_VIHDM1_DC VODTR=VDDQ*(2Ron+Rtt)/(Ron+Rtt) Differential signals contain single ended characteristics. Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 2.3.2. Differential AC and DC input level Table-2: Differential AC and DC input levels for CK/DQS 1. Differential AC and DC input levels for CK Symbol VIHdiffCK(dc) VILdiffCK(dc) VIHdiffCK(ac) VILdiffCK(ac) LPDDR3-1600 Differential input high Differential input low Differential input high AC Differential input low AC Test voltage(V) 0.96 -0.97 1.14 -1.12 Recommended voltage(V) 0.2～1.2 -1.2～-0.2 0.3～1.5 -1.5～-0.3 table8_VIHdiffCK_AC table8_VIHdiffCK_DC Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 2. Differential AC and DC input levels for DQS1 Symbol VIHdiffDQS(dc) VILdiffDQS(dc) VIHdiffDQS(ac) VILdiffDQS (ac) LPDDR3-1600 Differential input high Differential input low Differential input high AC Differential input low AC Test voltage(V) 0.31 -0.33 0.59 -0.60 Recommended voltage(V) 0.2～1.2 -1.2～-0.2 0.3～1.5 -1.5～-0.3 table8_VIHdiffDQS1_AC table8_VIHdiffDQS1_DC

Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 Table-3: Differential AC characteristics for CK/DQS 1. Differential AC characteristics for CK Symbol VSEHCK(AC150) VSELCK(AC150) VSEHCK(AC135) VSELCK(AC135) LPDDR3-1600 Single-ended high-level for strobes/ck Single-ended low-level for strobes/ck Single-ended high-level for strobes/ck Single-ended low-level for strobes/ck Test voltage(V) 1.46 -0.08 1.46 -0.08 Recommended voltage(V) 0.75～1.55 -0.35～0.45 0.735～1.55 -0.35～0.465 table9_VSEHCK_AC150 2. Differential AC characteristics for DQS1 Symbol VSEHDQS(AC150) VSELDQS(AC150) VSEHDQS(AC135) VSELDQS(AC135) LPDDR3-1600 Single-ended high-level for strobes/ck Single-ended low-level for strobes/ck Single-ended high-level for strobes/ck Single-ended low-level for strobes/ck Test voltage(V) 0.90 0.27 0.90 0.27 Recommended voltage(V) 0.75～1.55 -0.35～0.45 0.735～1.55 -0.35～0.465 Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table9_VSEHDQS1_AC150 2.3.3. Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK_t, CK_c and DQS_t, DQS_c) must meet the requirements Table-4: Cross point voltage for CK/DQS1 Symbol VIXCA VIXDQ Parameter Differential Input Cross Point Voltage relative to VDDCA/2 for CK_t, CK_c Differential Input Cross Point Voltage relative to VDDQ/2 for DQS_t, DQS_c Test voltage(mV) 111 87 Recommended voltage(mV) -120～120 -120～120 Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table10_VIXCA table10_VIXDQ Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 2.3.4. Slew Rate Definitions for Input Signals Table-5: input signal slew rate for DQ/DM/DQS Symbol Parameter input falling slew Test slew(V/ns) 2.68 1.68 2.24 1.92 Recommended skew(V/ns) 1.5～4.0 1.5～4.0 1.5～4.0 1.5～4.0 DQ9 input rising slew input falling slew DQM1 input rising slew table11_DQ9_Fallingslew Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table11_DQ9_Risingslew table11_DQM1_Fallingslew

Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table11_DQM1_Risingslew 2.4. AC and DC output measurement level 2.4.1. Single Ended AC and DC Output Levels Table-6: AC and DC output Levels for CA/DQ 1. AC and DC output Levels for A0 Symbol VOHCA(DC) VOLCA(DC) ODT disabled VOLCA(DC) ODT enabled VOHCA(AC) VOLCA(AC) LPDDR3-1600 DC output high measurement level DC output low measurement level Test voltage(V) 1.24 0.40 Recommended voltage(V) >0.9*VDDQ <0.1*VDDQ DC output low measurement level AC output high measurement level AC output low measurement level - 1.35 -0.72 VREFDQ+0.12 0.9*VDDQ <0.1*VDDQ VREFDQ+0.12 0.9*VDDQ <0.1*VDDQ VREFDQ+0.12 0.2*VDDQ <-0.2*VDDQ table13_VOHdiffCK_AC 2. AC and DC output Levels for DQS1 Symbol VOHdiffDQS(AC) VOLdiffDQS(AC) LPDDR3-1600 AC differential output high measurement level AC differential output low measurement level Test voltage(V) 0.619 -0.612 Recommended voltage(V) >0.2*VDDQ <-0.2*VDDQ

Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table13_VOHdiffDQS1_AC 2.4.3. Slew Rate Definitions for output Signals Table-8: Output Slew rate for CA/CKE/DQ/DM/CK/DQS 1. Output Slew rate for CA9 Symbol Parameter Single-ended output slew rate for rising edge CA Single-ended output slew rate for falling edge 3.75 1.5～4.0 Test slew(V/ns) 3.85 Recommended skew(V/ns) 1.5～4.0 table14_CA9_slewrate_Rising Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table14_CA9_slewrate_Falling 2. Output Slew rate for CS0 Symbol Parameter Single-ended output slew rate for rising edge CS Single-ended output slew rate for falling edge 3.49 1.5～4.0 Test slew(V/ns) 2.54 Recommended skew(V/ns) 1.5～4.0 table14_CS0_slewrate Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 3. Output Slew rate for CKE0 Symbol Parameter Single-ended output slew rate for rising edge CKE Single-ended output slew rate for falling edge - 1.5～4.0 Test slew(V/ns) 2.8 Recommended skew(V/ns) 1.5～4.0 table14_CKE0_slewrate_Rising 4. Output Slew rate for DQ9 Symbol Parameter Single-ended output slew rate for rising edge DQ Single-ended output slew rate for falling edge 2.84 1.5～4.0 Test slew(V/ns) 1.57 Recommended skew(V/ns) 1.5～4.0 Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table11_DQ9_Risingslew table11_DQ9_Fallingslew 5. Output Slew rate for DM1 Symbol Parameter Single-ended output slew rate for rising edge DM Single-ended output slew rate for falling edge 2.53 1.5～4.0 Test slew(V/ns) 3.25 Recommended skew(V/ns) 1.5～4.0 Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table11_DQM1_Risingslew table11_DQM1_Fallingslew

Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 6. Output Slew rate for DQS1 Symbol Parameter Differential output slew rate for rising edge DQS Differential output slew rate for falling edge 3.45 3.0～8.0 Test slew(V/ns) 3.57 Recommended skew(V/ns) 3.0～8.0 table11_DQS1_Risingslew table11_DQS1_Fallingslew Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 2.5. Electrical characteristics and AC timings 2.5.1. Clock parameters and AC timing Table-9: Signals AC timing Symbol Clock tCK(avg) tCH(avg) tCL(avg) tJIT(per) LPDDR3-1600 Test Value Units Spec range Average Clock Period Average clock HIGH pulse width for clock duty check Average clock LOW pulse width for clock duty check Clock period jitter 1.251 0.501 0.499 46 ns tCK(avg) tCK(avg) ps 1.5/1.25~100 0.45~0.55 0.45~0.55 -70~70 Read Read command(CLK) to 1st DQS latching rising tDQSCK transition tDQS(avg) Average DQS Period tQSH tQSL tDQSQ DQS output HIGH pulse width DQS output LOW pulse width DQS to DQ skew（read） 2.5 0.52 0.48 44 ns tCK(avg) tCK(avg) ps 2.5~3.3 >tCH(abs)-0.05 >tCL(abs)-0.05 <165/135 3581 ps 2500-5500 Write tDQSS tDQSH tDQSL Write command to 1st DQS latching transition DQS input high-level width DQS input low-level width 1.2 0.51 0.49 tCK(avg) tCK(avg) tCK(avg) 0.75~1.25 >0.4 >0.4 Command Address Input tIPWCA Address and control input pulse width 0.48 tCK(avg) >0.35 Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table16_tDQSCK table16_tDQDS Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table16_tDQSQ table16_tDQSS Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table16_tIPWCA 2.5.2. CA/CS setup and hold Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. Table-10: Setup and hold time for CA/CS Symbol LPDDR3-1600 Test Value Units Spec range CA Setup and Hold Base-Values tISCA(base150) tIHCA(base100) Address and control input setup time Address and control input hold time 267 350 ps ps >100/75 >125/100 CS Setup and Hold Base-Values tISCA(base150) tIHCA(base100) Address and control input setup time Address and control input hold time - - ps ps >215/195 >240/220 Note that AC/DC referenced for 2V/ns CA slew rate and 4V/ns differential CK_t/CK_c slew rate.

Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table17_tISCA table17_tIHCA Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 2.5.3. DQ/DM setup and hold Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. Table-11: Setup and hold time for DQ/DM Symbol LPDDR3-1600 Test Value Units Spec range DQ9/DM1 Setup and Hold Base-Values tDS(base150) tDH(base100) tDS(base150) tDH(base100) DQ input setup time DQ input hold time DM input setup time DM input hold time 478 433 355 422 ps ps ps ps >100/75 >125/100 >100/75 >125/100 table18_tDS_DQ9 Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table18_tDH_DQ9 table18_tDS_DM1 Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 table18_tDH_DM1 Note that AC/DC referenced for 2V/ns DQ, DM slew rate and 4V/ns differential DQS_t/DQS_c slew rate and nominal VIX. 3. DRAM Devices compatible test Table-12: LPDDR3 devices compatible test results Devices PN AC/DC voltage level AC/DC timing Setup/Hold time memory test loop Security level Deliver date A 2015-12-31 TL7790 TEST REPORT Doc.No Version x-xxx-xxx-xxxx V1.00 4. Verify result 4.1. Fail list 1. CA有过冲。 4.2. Any issue 测试过程中发现一个问题： 下面图黄色线为DQS1，绿色线为DQ9，测量过程中DQ9的一个下降沿跨越了DQS1的两个沿，目前正在解决此问题。 5. Summary 1、whether compliance with JEDEC standard 2、CA有过冲，可以开启ODT或调整相应寄存器参数。

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