(MBD_DM6437_FPGA_en)DaVinci_lab5_speedway_f08_10_1_3_3

Creating FPGA-based Co-Processors for DSPs

Using Model Based Design Techniques

Lab 5

Creating a Stand-alone Video System

for Avnet Spartan-3A DSP DaVinci Development Kit

January 2008 Version 3.0

Lab Objectives

Upon completion of this lab, you will understand how to create a complete stand-alone video system based on the Avnet Spartan-3A DSP DaVinci Devlopment kit with PS Video EXP module and XGA flat panel LCD display, proceeding with the following steps:

generate an FPGA co-processor with VLYNQ interface to DM6437 processor;

integrate the co-processor into a larger system that contains the entire FPGA infrastructure for board-level functionality of the Avnet Spartan-3A DSP DaVinci Devlopment kit, including video input and output via the Avnet PS Video EXP module;

auto-generate code using The MathWorks Embedded Coder TC6 for the DM6437 DaVinci processor to create the stand-alone video stabilization system.

Lab Setup

This lab will require the following software and hardware setups. Software

The software requirements for this lab are:

WindowsXP

Xilinx ISE 10.1i with Service Pack 3

Xilinx System Generator for DSP 10.1 with Service Pack 3 IP Update #3

The Mathworks MATLAB/Simulink R2008a

o Video and Image Processing Toolbox and Blockset o Signal Processing Toolbox and Blockset

o Real Time Workshop with Target Support Package TC6 o Embedded IDE Link CC

Texas Instruments Code Composer Studio v3.3 with Service Release 10

Avnet Board Support Package v1.06 for Spartan-3A DSP DaVinci Development

Kit

MathWorks Spartan-3A DSP DaVinci Platform Support Package v1.06 Hardware

The hardware required for this lab is:

Avnet Spartan-3A DSP DaVinci Development Kit Rev B Avnet PS Video EXP module Rev D NEC XGA LCD flat panel display Xilinx JTAG download cable

BlackHawk USB 510L JTAG Emulator

Computer with 1 GB RAM

Introduction

In lab 4 we added robust flow control to the basic System Generator-based SAD model of lab 3. We then prepared the model for hardware co-simulation in anticipation of burst mode data flow between Simulink and FPGA. We ran hardware co-simulation to prove the model under test in FPGA hardware at full system clock rate as part of a larger Simulink system.

Using MPLAY, we demonstrated a method of single-stepping the system through individual frames of video to observe data at any node in the system. Armed with the confidence that the FPGA design-under-test performs as expected, we can move towards a stand-alone video system combining DSP and FPGA co-processor on the Avnet Spartan-3A DSP DaVinci board.

Experiment 1: Building the stand-alone FPGA co-processor

The starting point for the stand-alone FPGA co-processor is the final model of lab 4, which we will now augment with VLYNQ connectivity to the DM6437 DSP, as shown below.

Figure 1 – Stand-Alone Video Stabilization System

Lab Procedure:

1. From MATLAB, navigate to

C:\SpeedWay\Fall_08\co_processing\lab5 and double click the SAD_fpga_coprocessor_start.mdl file to open it in Simulink.

2. Hold down the Ctrl key and type ‘A’ to select All blocks, then hold down the Ctrl key

and type ‘G’ to create a subsystem. Rename the new subsystem ‘sad’.

3. In preparation for augmenting the SAD with a VLYNQ interface, you will add

several blocks from the Xilinx Blockset, starting with a ‘To Register’ shown below.

Figure 2 – Adding a Shared Memory ‘To Register’

The table below shows the locations of the next blocks to be added.

Block Constant

System Generator

Library

Xilinx Blockset > Basic Elements Xilinx Blockset > Basic Elements

Quantity

1 1

Block

Terminator

Library

Simulink > Sinks

Quantity

1

Figure 3 – Adding Boolean constant block

4. Next we add the Xilinx System Generator block, as shown below. System Generator

will propagate the FPGA clock period setting of 16 ns as a timing constraint for the VLYNQ interface to ISE Project Navigator. This corresponds to an FPGA system clock of 125 MHz divided by 2 on the Avnet Spartan-3A DSP DaVinci board.

The SAD engine is operated at 125 MHz (8 ns period constraint), set in the System Generator block of subsystem ‘sad’. If faster SAD computation time is desired of the

FPGA co-processor, then this clock period setting can be reduced. This is a design decision that is normally taken at step 32 in experiment 3.

Figure 4 -- Adding Xilinx System Generator block

5. At the MATLAB command line, type: avnet_s3adsp_dm6437_fpgalib

Figure 5 – FPGA Library, part of Avnet Board Support Package

6. Add the ‘DaVinci Processor’ and ‘dipsw’. The ‘dipsw’ block from the FPGA Library

maps to dip switch SW3 on the Avnet Spartan-3A DSP DaVinci board. The ‘To_Register’ allows the DM6437 to read the dip switch through the FPGA.

Figure 6 -- Adding 'DaVinci Processor' and 'dipsw' blocks

Double-click to open the ‘Davinci Processor’ GUI. Enumerate all shared memory in the model. Close the GUI when finished.

Figure 7 -- Enumerating Shared Memory

Shared memories in the System Generator model destined for the FPGA co-processor are associated with the DM6437 processor through the ‘DaVinci Processor’ VLYNQ

Interface block’s GUI. Expand all shared memories as shown above in Figure 7, and copy the information into the table below. DSP Æ FPGA indicates DM6437 writes to FPGA.

Name

Address (Hex) / (Dec) NOTE: ignore MS Hex digit

sad_roi sad_template

depth

direction

DSP Æ FPGA DSP Æ FPGA

n/a FPGA Æ DSP

min_SAD_Idx

SAD_NVals

FPGA Æ DSP

dip n/a FPGA Æ DSP

Table 1

In the following steps, the complete FPGA co-processor consisting of SAD + VLYNQ interface will be generated and memory-mapping information of table 1 exported to:

Xilinx ISE, passing memory-mapping the the VLYNQ LogiCore IP

Texas Instruments Code Composer Studio via The MathWorks Embedded Target TC6 tools

Exporting memory-mapping for shared memory is illustrated below, as presented in lecture 5.

Figure 8 -- Exporting Memory-Mapping for Shared memory

7. Follow the steps in Figure 9 to create a subsystem named ‘VLYNQ’, and add the

‘Multiple Subsystem Generator’ block from the Simulink Library Browser Æ Xilinx Blockset Æ Tools.

Figure 9 – Creating the VLYNQ Subsystem

Figure 10 – Adding a Multiple Subsystem Generator

8. Save the model as ‘sad_fpga_coprocessor.mdl’.

9. Close the model, and re-open it anew. As the model opens, note the text line at the

MATLAB console:

[DaVinci Processor] Successfully generated VLYNQ memory map to ‘vlynq_mmap’ workspace variable.

This confirms that all memory-mapping information for shared memory in the model is exported to the MATLAB workspace variable ‘vlynq_mmap’.

We are now ready for automatic code generation of the FPGA co-processor, as illustrated below.

Figure 11 -- Automatic Code Generation of the FPGA Co-Processor

10. Generate the top-level HDL for the FPGA co-processor as shown below.

Figure 12 -- Generating the Top-Level HDL component for the FPGA Co-Processor The Xilinx Multiple Subsystem Generator block wires two or more System Generator designs into a single top-level HDL component that incorporates multiple clock domains. This top-level component includes the logic associated with each System Generator design and additional logic to allow the designs to communicate with one another.

This completes experiment 1.

The FPGA co-processor is now complete, consisting of VLYNQ and SAD modules elaborated as netlists, stitched together in a top-level HDL component named ‘sad_fpga_coprocessor’. It is now ready for integration it into a larger system that contains the entire FPGA infrastructure for the Avnet Spartan-3A DSP DaVinci development Kit.

Experiment 2: Integrating the co-processor into the board-level FPGA infrastructure for the Avnet Spartan-3A DSP DaVinci Development Kit

In experiment 1 we developed the application-specific co-processor in Xilinx System Generator for DSP with MathWorks model-based design tools. In experiment 2, we will import the co-processor design into a larger system that contains the entire FPGA

infrastructure for the Avnet Spartan-3A DSP DaVinci. The design environment of choice for this task is Xilinx ISE Project Navigator.1

Lab Procedure:

1. From the Windows Start / All Programs menu, launch Xilinx Project Navigator:

Xilinx ISE Design Suite 10 Æ ISE Æ Project Navigator

2. From File Æ Open project, navigate to

3. Double click to open project davinci_coprocessor_sad_demo.ise

C:\SpeedWay\Fall_08\co_processing\lab5\avnet_s3adsp_dm6437_FPGA_top_level

Xilinx ISE Project Navigator is the main IDE for FPGA development. Although there is insufficient time to explore ISE in this seminar, Avnet and Xilinx offer a variety of introductory-level workshops featuring ISE.

1

Figure 13 – Open ISE project

This ISE project has been augmented from a baseline reference design called 'FPGA Co-Processing Design' that ships with the Avnet Spartan-3A DSP DaVinci Development Kit. The baseline reference design provides the complete FPGA infrastructure to connect to video sources and displays of the Avnet PS Video EXP module mounted onto the Avnet Spartan-3A DSP DaVinci board. To create the FPGA-side of a stand-alone video system, simply augment the baseline reference design with an application-specific co-processor block, in this case the SAD created in experiment 1.

Figure 14 -- Baseline Reference Design 'FPGA Co-Processing Design'

The FPGA-side baseline reference design is located in folder

C:\avnet_s3adsp_dm6437_1_06\bsl\fpga\ise\davinci_coprocessor

4. When the project opens, re-size the ‘sources’ pane in the top-left corner of Project

Navigator, enlarging it such that pathnames of the various components are fully visible.

Figure 15 – Project Navigator

Question #1:

What is the name of the application-specific co-processor in the Project

Navigator ‘sources’ pane ? __________________________________________ In what step of experiment 1 was the application-specific co-processor

generated? __________

We are now ready to compile the entire FPGA-side video system with SAD co-processor for stand-alone operation on the Avnet Spartan-3A DSP DaVinci Development Kit. We are at the point illustrated below.

Figure 16 -- Compiling the FPGA-side Video System

5. Highlight the top-level module ‘davinci_coprocessor_sad_demo’ and launch

‘Configure Target Device’, as shown below. This will execute all intermediate

processes in order to generate the bitstream for download to the FPGA. At this time, ensure the JTAG download cable to the board is still connected.

Figure 17 -- Generating the Bitstream for FPGA-side Stand-Alone Video System

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