GS88136BT-300中文资料
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GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
512K x 18, 256K x 32, 256K x 369Mb Sync Burst SRAMs
333 MHz –150 MHz 2.5 V or 3.3 V V DD 2.5 V or 3.3 V I/O
100-pin TQFP & 165-bump BGA Commercial Temp Industrial Temp Rev: 1.05 11/20051/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
Features
? IEEE 1149.1 JTAG-compatible Boundary Scan ? 2.5 V or 3.3 V +10%/–10% core power supply ? 2.5 V or 3.3 V I/O supply
? LBO pin for Linear or Interleaved Burst mode
? Internal input resistors on mode pins allow floating mode pins ? Byte Write (BW) and/or Global Write (GW) operation ? Internal self-timed write cycle
? Automatic power-down for portable applications
? JEDEC-standard 100-lead TQFP and 165-bump BGA packages
? RoHS-compliant 100-lead TQFP and 165-bump BGA packages available
Functional Description
Applications
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1, E2), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
SCD Pipelined Reads
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.
Paramter Synopsis
-333
-300
-250
-200
-150
Unit
Pipeline 3-1-1-1
KQ tCycle 3.0 3.3 4.0 5.0 6.7ns Curr (x32/x36)290265230195160mA Flow Through 2-1-1-1
KQ tCycle 4.54.5 5.05.0 5.55.5 6.56.57.57.5ns ns Curr (x18)Curr (x32/x36)
200230
185210
160185
140160
128145
mA mA
元器件交易网
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/2005
2/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
807978777675747372
7170
69686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B FT V DD NC V SS DQ B DQ B V DDQ V SS DQ B DQ B DQP B
V SS V DDQ V DDQ V SS DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A
A 1
A 0
T M S T D I V S S
V D D
T D O T C K A A A A A A
A A E 1
E 2
N C N C B B
B A
A C K G W
B W V D D
V S S
G A D S C A D S P A D V A A
A 512K x 18Top View DQP A A NC NC NC NC NC NC NC NC
NC NC NC NC NC NC NC
NC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950
GS88118B 100-Pin TQFP Pinout (Package T)
元器件交易网
807978777675747372
7170
69686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1
A 0
V S S
V D D
A A A A A A
A A E 1
E 2
B D
B C
B B
B A
A C K G W
B W V D D
V S S
G A D S C A D S P A D V A A
A 256K x 32Top View DQ
B N
C DQ B DQ B DQ B DQ A DQ A DQ A DQ A NC
DQ C DQ C DQ C DQ D DQ D DQ D NC
DQ C NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950
T M S T D I T D O T C K
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/2005
3/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
GS88132B 100-Pin TQFP Pinout (Package T)
元器件交易网
807978777675747372
7170
69686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1
A 0
V S S
V D D
A A A A A A
A A E 1
E 2
B D
B C
B B
B A
A C K G W
B W V D D
V S S
G A D S C A D S P A D V A A
A 256K x 36Top View DQ
B DQP B DQ B DQ B DQ B DQ A DQ A DQ A DQ A DQP A
DQ C DQ C DQ C DQ D DQ D DQ D DQP D
DQ C DQP C 100999897969594939291908988878685848382813132333435363738394041424344454647484950
T M S T D I T D O T C K
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/2005
4/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
GS88136B 100-Pin TQFP Pinout (Package T)
元器件交易网
TQFP Pin Description
Symbol
Type
Description
A 0, A 1I Address field LSBs and Address Counter preset Inputs
A I Address Inputs DQ A DQ
B DQ
C DQ
D I/O Data Input and Output pins
NC —No Connect
BW I Byte Write —Writes all enabled bytes; active low B A , B B, B C , B D
I Byte Write Enable for DQ A , DQ B Data I/Os; active low
CK I Clock Input Signal; active high
GW I Global Write Enable —Writes all bytes; active low
E 1I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active low
ADV I Burst address counter advance enable; active low ADSP, ADSC
I Address Strobe (Processor, Cache Controller); active low
ZZ I Sleep Mode control; active high
TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock
FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low
V DD I Core power supply V SS I I/O and Core Ground V DDQ
I
Output driver power supply
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/20055/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
元器件交易网
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/20056/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1
234567891011A NC A E1BB NC E3BW ADSC ADV A A A B NC A E2NC BA CK GW G ADSP A NC B C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQA C D NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA D E NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA E F NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA F G NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA G H FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ H J DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC J K DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC K L DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC L M DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC M N DQB NC V DDQ V SS NC NC NC V SS V DDQ NC NC N P NC NC A A TDI A1TDO A A A A P R
LBO
NC
A
A
TMS
A0
TCK
A
A
A
A
R
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
元器件交易网
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/20057/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
165 Bump BGA—x32 Common I/O—Top View 1
234567891011A NC A E1BC BB E3BW ADSC ADV A NC A B NC A E2BD BA CK GW G ADSP A NC B C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC NC C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N NC NC V DDQ V SS NC NC NC V SS V DDQ NC NC N P NC NC A A TDI A1TDO A A A A P R
LBO
NC
A
A
TMS
A0
TCK
A
A
A
A
R
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
(Package D)
元器件交易网
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/20058/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
165 Bump BGA—x36 Common I/O—Top View 1
234567891011A NC A E1BC BB E3BW ADSC ADV A NC A B NC A E2BD BA CK GW G ADSP A NC B C DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQPD NC V DDQ V SS NC NC NC V SS V DDQ NC DQPA N P NC NC A A TDI A1TDO A A A A P R
LBO
NC
A
A
TMS
A0
TCK
A
A
A
A
R
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
(Package D)
元器件交易网
165-Bump BGA Pin Description
Symbol
Type
Description
A 0, A 1I Address field LSBs and Address Counter Preset Inputs
A I Address Inputs DQ A DQ
B DQ
C DQ
D I/O Data Input and Output pins
B A , B B , B
C , B D
I Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active low
NC —No Connect
CK I Clock Input Signal; active high
BW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active low
E 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active low
ADV I Burst address counter advance enable; active l0w ADSC, ADSP
I Address Strobe (Processor, Cache Controller); active low
ZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low
TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCL —Must Connect Low V DD I Core power supply V SS I I/O and Core Ground V DDQ
I
Output driver power supply
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/20059/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
元器件交易网
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/200510/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
A1
A0
A0A1
D0
D1Q1Q0
Counter Load
D Q
D
Q
Register
Register
D
Q
Register
D
Q
Register
D
Q
Register
D Q
Register
D Q
Register
D Q
Register
D
Q
R e g i s t e r
D
Q
Register
A0–An
LBO ADV CK ADSC ADSP GW BW E 1G
ZZ
Power Down Control
Memory Array
36
36
4
A
Q
D
E 2E 3
DQx1–DQx9
Note: Only x36 version shown for simplicity.
1
B A
B B
B C
B D
FT GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) Block Diagram
元器件交易网
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control
ZZ
L or NC Active H
Standby, I DD = I SB
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/200511/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables.Note:
The burst counter wraps to initial state on the 5th clock.Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0]A[1:0]A[1:0]A[1:0]
1st address 000110112nd address 011011003rd address 101100014th address
11
00
01
10
Interleaved Burst Sequence
A[1:0]A[1:0]A[1:0]A[1:0]
1st address 000110112nd address 010011103rd address 101100014th address
11
10
01
00
Burst Counter Sequences
BPR 1999.05.18
元器件交易网
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/200512/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
Byte Write Truth Table
Function
GW
BW
B A
B B
B C
B D
Notes
Read H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes L X X X X X
1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2.Byte Write Enable inputs B A , B B , B C and/or B D may be used in any combination with BW to write single or multiple bytes.
3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4.Bytes “C ” and “D ” are only available on the x36 version.
元器件交易网
Synchronous Truth Table
Operation
Address Used
State Diagram Key 5
E 1
E 2
ADSP ADSC
ADV
W 3
DQ 4
Deselect Cycle, Power Down None X H X X L X X High-Z Deselect Cycle, Power Down None X L F L X X X High-Z Deselect Cycle, Power Down None X L F H L X X High-Z Read Cycle, Begin Burst External R L T L X X X Q Read Cycle, Begin Burst External R L T H L X F Q Write Cycle, Begin Burst External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW
H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst
Current
X
X
H
H
H
T
D
Write Cycle, Suspend Burst Current H X X H H T D 1.X = Don’t Care, H = High, L = Low
2. E = T (True) if E 2 = 1 and E 3 = 0; E = F (False) if E 2 = 0 or E 3 = 1
3.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/200513/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
元器件交易网
First Write First Read Burst Write Burst Read Deselect
R W
CR
CW
X
X
W R
R W R X X X S i m p l e S y n c h r o n o u s O p e r a t i o n S i m p l e B u r s t S y n c h r o n o u s O p e r a t i o n CR
R CW CR
CR Notes:
1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/200514/39© 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see . Simplified State Diagram
元器件交易网
First Write First Read Burst Write Burst Read
Deselect
R W CR
CW X X
W R
R W
R X X X CR R
CW CR
CR W
CW W CW Notes:
1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.
3.Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/200515/39© 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see . Simplified State Diagram with G
元器件交易网
Absolute Maximum Ratings
(All voltages reference to V SS )
Symbol
Description
Value
Unit
V DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage in V DDQ Pins –0.5 to 4.6
V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)
V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5W
T STG Storage Temperature –55 to 125o C T BIAS
Temperature Under Bias
–55 to 125
o
C
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/200516/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
3.3 V Supply Voltage V DD3 3.0 3.3 3.6V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 3.3 V V DDQ I/O Supply Voltage V DDQ3 3.0 3.3 3.6V 2.5 V V DDQ I/O Supply Voltage
V DDQ2
2.3
2.5
2.7
V
Notes:
1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.
2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
元器件交易网
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/200517/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
V DDQ3 Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V DD Input High Voltage V IH 2.0—V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.8V 1V DDQ I/O Input High Voltage V IHQ 2.0—V DDQ + 0.3V 1,3V DDQ I/O Input Low Voltage
V ILQ
–0.3
—
0.8
V
1,3
Notes:
1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.
2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.
V DDQ2 Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.3*V DD V 1V DDQ I/O Input High Voltage V IHQ 0.6*V DD —V DDQ + 0.3V 1,3V DDQ I/O Input Low Voltage
V ILQ
–0.3
—
0.3*V DD
V
1,3
Notes:
1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.
2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.
Recommended Operating Temperatures
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Ambient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)
T A
–40
25
85
°C
2
Notes:
1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.
2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
元器件交易网
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/200518/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
50% tKC
V SS – 2.0 V
50%V SS V IH
Undershoot Measurement and Timing
Overshoot Measurement and Timing
50% tKC
V DD + 2.0 V
50%V DD
V IL
Capacitance
o C, f = 1 MH Z , V DD Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/O
V OUT = 0 V
6
7
pF
Note:
These parameters are sample tested.AC Test Conditions
Parameter
Conditions
Input high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference level
V DDQ /2Output load
Fig. 1
Notes:
1.Include scope and jig capacitance.
2.Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3.Device is deselected as defined by the Truth Table.
DQ
V DDQ/2
50?30pF *
Output Load 1
* Distributed Test Jig Capacitance
(T A = 25= 2.5 V)
元器件交易网
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I IN1V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH
–1 uA –1 uA 1 uA 100 uA Output Leakage Current I OL Output Disable, V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V 1.7 V —Output High Voltage V OH3I OH = –8 mA, V DDQ = 3.135 V
2.4 V —Output Low Voltage
V OL
I OL = 8 mA
—
0.4 V
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/200519/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
元器件交易网
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/200520/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
Operating Currents
Parameter
Test Conditions
Mode
Symbol
-333
-300-250-200-150Unit
0to 70°C
–40 to 85°C
0to 70°C
–40 to 85°C
0to 70°C
–40 to 85°C
0to 70°C
–40to 85°C
0 to 70°C
–40to 85°C
Operating Current
Device Selected; All other inputs ≥V IH o r ≤ V IL Output open
(x32/x36)
Pipeline I DD I DDQ 25040270402303525035200302203017025190251402016020mA Flow Through I DD I DDQ 20525225251852520525160251802514020160201301515015mA (x18)
Pipeline
I DD I DDQ 23020250202102023020185152051515515175151301015010mA Flow Through I DD I DDQ 185152051517015190151451516515130101501012081408mA Standby Current
ZZ ≥ V DD – 0.2 V —
Pipeline
I SB 40504050405040504050mA Flow Through I SB 40504050405040504050mA Deselect Current
Device Deselected; All other inputs ≥ V IH or ≤ V IL
—
Pipeline
I DD 951009095859075806065mA Flow Through
I DD
65
60
60
65
60
65
50
55
50
55
mA
1.I DD and I DDQ apply to any combination of V DD3, V DD2, V DDQ3, and V DDQ2 operation.
2.All parameters listed are worst case scenario.
元器件交易网
AC Electrical Characteristics
Parameter
Symbol
-333
-300
-250
-200
-150
Unit
Min
Max Min Max Min Max Min Max Min Max Pipeline
Clock Cycle Time tKC 3.0— 3.3— 4.0— 5.0— 6.7—ns Clock to Output Valid tKQ — 2.5— 2.5— 2.5— 3.0— 3.8ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-Z
tLZ 1 1.5— 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.0— 1.0— 1.2— 1.4— 1.5—ns Hold time tH 0.1—0.1—0.2—0.4—0.5—ns Flow Through
Clock Cycle Time tKC 4.5— 5.0— 5.5— 6.5—7.5—ns Clock to Output Valid tKQ — 4.5— 5.0— 5.5— 6.5—7.5ns Clock to Output Invalid tKQX 2.0— 2.0— 2.0— 2.0— 2.0—ns Clock to Output in Low-Z
tLZ 1 2.0— 2.0— 2.0— 2.0— 2.0—ns Setup time tS 1.3— 1.4— 1.5— 1.5— 1.5—ns Hold time tH 0.3—0.4—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.0— 1.0— 1.3— 1.3— 1.5—ns Clock LOW Time tKL 1.2
— 1.2
— 1.5
— 1.5
— 1.7—ns Clock to Output in
High-Z tHZ 1 1.5 2.5 1.5 2.5 1.5 2.5 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.5— 2.5— 2.5— 3.0— 3.8ns G to output in Low-Z tOLZ 10—0—0—0—0—ns G to output in High-Z tOHZ 1— 2.5— 2.5— 2.5— 3.0— 3.8ns ZZ setup time tZZS 25—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—ns ZZ recovery
tZZR
20
—
20
—
20
—
20
—
20
—
ns
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
Rev: 1.05 11/200521/39© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see .
Notes:
1.These parameters are sampled and are not 100% tested
2.ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
元器件交易网
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