adc0809 fpga点正显示
更新时间：2023-05-17 08:41:01 阅读量： 实用文档 文档下载
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ad0809 IS
PORT (
clk,int : in std_logic; --时钟输入
cs,wr,rd : out std_logic; ---AD控制信号
tongdao :buffer std_logic_vector(1 DOWNTO 0); --通道选择信号
selout : out std_logic_vector(1 DOWNTO 0); --位选输出
datout : out std_logic_vector(15 DOWNTO 0) ); --段码输出
END ad0809 ;
------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
architecture arch of ad0809 is
type state is (s0,s1,s2,s3);---状态定义
signal current_state,next_state : state ;
signal cnt :std_logic_vector(2 DOWNTO 0);
signal sel :std_logic_vector(1 DOWNTO 0);
signal tongdao1,tongdao2,tongdao3,tongdao4:std_logic_vector(7 DOWNTO 0);
signal tmp :std_logic_vector(7 DOWNTO 0);
signal flag :std_logic;
begin
process(current_state)
begin
case current_state is
when s0 => cs<='1';wr<='1'; rd<='0';flag<= '0'; next_state <= s1;
when s1 => cs<='0';wr<='0'; rd<='0'; flag<= '0'; if int ='1' then
next_state<= s2;
else
next_state<= s1;
end if;
when s2 => cs<='1';wr<='0';rd<='1';flag<= '1'; --当flag=1时开始采集数据
next_state<= s3;
when s3 => cs<='0';wr<='0';rd<='0';flag<= '0';
next_state<= s0;
end case;
end process;
process (clk)
begin
if (clk'event and clk='1') then
current_state<=next_state; ---状态转换
end if; end process;
process(flag)
begin
if flag'event and flag='1' then
tongdao<= tongdao+1; --通道加1
sel<= sel+1; --位选加一
case tongdao is
when "00" => tongdao1<=data; ---将对应通道值送出
when "01" => tongdao2<=data;
when "10" => tongdao3<=data;
when "11" => tongdao4<=data;
when others => null;
end case;
------------------每个通道所对应的位选
case sel is
when "00" => tmp<=tongdao1; --将对应值送给tmp，进行输出处理
when "01" => tmp<=tongdao2;
when "10" => tmp<=tongdao3;
when "11" => tmp<=tongdao4;
when others => null;
end case;
selout<=sel;
end if;
end process;
process(sel)
begin
case tmp is ---将转换得来的值处理，并选择相应输出数据 when "00000000" => datout<="0000000000000001" ;
when "00010000" => datout<="0000000000000011" ;
when "00100000" => datout<="0000000000000111" ;
when "00110000" => datout<="0000000000001111" ;
when "01000000" => datout<="0000000000011111" ;
when "01010000" => datout<="0000000000111111" ;
when "01100000" => datout<="0000000001111111" ;
when "01110000" => datout<="0000000011111111" ;
when "10000000" => datout<="0000000111111111" ;
when "10010000" => datout<="0000001111111111" ;
when "10100000" => datout<="0000011111111111" ;
when "10110000" => datout<="0000111111111111" ;
when "11000000" => datout<="0001111111111111" ;
when "11010000" => datout<="0011111111111111" ;
when "11100000" => datout<="0111111111111111" ;
when "11110000" => datout<="1111111111111111" ;
when others => null;
end case;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---*******************************************************
--clk
--********************************************************
entity adc is
port( clk:in std_logic;
wr,rd,cs:out std_logic; --外部时钟输入
int:in std_logic; --数据转换完成
dat:in std_logic_vector(7 downto 0); --AD数据输入
sel:out std_logic_vector(3 downto 0); --点阵位选
datout:out std_logic_vector(15 downto 0)); --点阵段选
end entity;
--*********************************************************
--*********************************************************
architecture behave of adc is
type states is( s0,s1, s2, s3);
signal datin:std_logic_vector(7 downto 0); --输入数据
signal current_state,next_state:states:=s0; --现态和次态
signal eoc:std_logic; --转换完成标志
signal cnt:std_logic_vector(1 downto 0); -- 计数
--********************状态转换**************************************** begin
eoc<=int;
qdadc:process(current_state,eoc)
begin
case current_state is
when s0=> next_state<=s1;cs<='1';wr<='1';rd<='0';
when s1=> cs<='0';wr<='0';rd<='0';
if eoc='1' then
next_state<=s2; --如果转换完成则条到下一个状态
else
next_state<=s1;--否则将继续上一个状态等待
end if;
when s2=>next_state<=s3;cs<='1';wr<='0';rd<='1';datin<=dat; --转换完成接受数据 when s3=>next_state<=s0;cs<='0';wr<='0';rd<='0';
when others=> next_state<=s0;cs<='1';wr<='1';rd<='0';
end case;
end process;
fenpin:process(clk)
begin
if clk'event and clk='1' then
if cnt="11" then
current_state<=next_state; --将次态给现态的值
else cnt<=cnt+1;
end if;
end if;
end process;
dataa<=datin;
--***************************显示
***********************************************
disp: block
begin
with datin(7 downto 4)select ---对高四位数值进行判断
datout<="0000000000000001" when"0000",
"0000000000000011" when"0001",
"0000000000000111" when"0010",
"0000000000001111" when"0011",
"0000000000011111" when"0100",
"0000000000111111" when"0101",
"0000000001111111" when"0110",
"0000000011111111" when"0111",
"0000000111111111" when"1000",
"0000001111111111" when"1001",
"0000011111111111" when"1010",
"0000111111111111" when"1011",
"0001111111111111" when"1100",
"0011111111111111" when"1101",
"0111111111111111" when"1110",
"1111111111111111" when"1111",
"0000000000000000" when others;
sel<="0001";
end block;
--************************************************
end behave;
library ieee; 译码
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---*******************************************************
--clk系统时钟，sel位选 datout：段码输出
--********************************************************
entity adc is
port( clk:in std_logic;
wr,rd,cs:out std_logic;
int:in std_logic;
dat:in std_logic_vector(7 downto 0);
sel:out std_logic_vector(3 downto 0);
datout:out std_logic_vector(15 downto 0));
end entity;
--*********************************************************
--*********************************************************
architecture behave of adc is
type states is( s0,s1, s2, s3); --状态表
signal datin:std_logic_vector(7 downto 0);--输入数据
signal current_state,next_state:states:=s0;--现态，下一个状态
signal eoc:std_logic;
signal sel_dat:std_logic_vector(3 downto 0);--位选译码变量
signal temp:std_logic_vector(4 downto 0);--译码中间值
--************************************************************
--**************************ad转换---------------------------
begin
eoc<=int;
qdadc:process(current_state,eoc)
begin
case current_state is
when s0=> next_state<=s1;cs<='1';wr<='1';rd<='0';
when s1=> cs<='0';wr<='0';rd<='0';
if eoc='1' then
next_state<=s2; --如果转换成功，跳到下一个状态
else
next_state<=s1;--为转换成功，则继续等待
end if;
when s2=>next_state<=s3;cs<='1';wr<='0';rd<='1';datin<=dat;
when s3=>next_state<=s0;cs<='0';wr<='0';rd<='0';
when others=> next_state<=s0;cs<='1';wr<='1';rd<='0';
end case;
end process;
---************************************************************************
---*******************状态转换和译码************************************* zhuantai:process(clk)
begin
if clk'event and clk='1' then
current_state<=next_state;---状态变换
sel_dat<=sel_dat-1; ----产生列扫描值
sel<=sel_dat;
if(datin(7 downto 4)>sel_dat) then
temp<="01111";
elsif(datin(7 downto 4)=sel_dat)then
temp<='0'&datin(3 downto 0);
else
temp<="10000";
end if;
end if;
end process;
--******************************************************************* --temp由
--*****************************显示部分****************************** disp: block
begin
with temp select
datout<="0000000000000001" when"00000",
"0000000000000011" when"00001",
"0000000000000111" when"00010",
"0000000000001111" when"00011",
"0000000000011111" when"00100",
"0000000000111111" when"00101",
"0000000001111111" when"00110",
"0000000011111111" when"00111",
"0000000111111111" when"01000",
"0000001111111111" when"01001",
"0000011111111111" when"01010",
"0000111111111111" when"01011",
"0001111111111111" when"01100",
"0011111111111111" when"01101",
"0111111111111111" when"01110",
"1111111111111111" when"01111",
"0000000000000000" when others;
end block;
--************************************************
end behave;
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