附录 DE2-115引脚表

附录 DE2-115实验板引脚配置信息

DE2-115开发板：目标芯片Cyclone IV E EP4CE115F29C7；存储器：64MB x2 SDRAM、2MB SRAM、8MB Flash；通信端口：10/100/1000以太网口 x2、USB 2.0时钟：50MHz x3 振荡器、SMA in/out Altera 串行配置芯片– EPCS64

表 1 拨动开关引脚配置

Signal Name SW[0] SW[1] SW[2] SW[3] SW[4] SW[5] SW[6] SW[7] SW[8] SW[9] SW[10] FPGA Pin No. PIN_AB28 PIN_AC28 PIN_AC27 PIN_AD27 PIN_AB27 PIN_AC26 PIN_AD26 PIN_AB26 PIN_AC25 PIN_AB25 PIN_AC24 Description Slide Switch[0] Slide Switch[1] Slide Switch[2] Slide Switch[3] Slide Switch[4] Slide Switch[5] Slide Switch[6] Slide Switch[7] Slide Switch[8] Slide Switch[9] Slide Switch[10] I/O Standard Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 SW[11] SW[12] SW[13] SW[14] SW[15] SW[16] SW[17] PIN_AB24 PIN_AB23 PIN_AA24 PIN_AA23 PIN_AA22 PIN_Y24 PIN_Y23 Slide Switch[11] Slide Switch[12] Slide Switch[13] Slide Switch[14] Slide Switch[15] Slide Switch[16] Slide Switch[17] Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 表 2 按钮开关引脚配置

Signal Name KEY[0] KEY[1] KEY[2] KEY[3] FPGA Pin No. Description PIN_M23 PIN_M21 PIN_N21 PIN_R24 Push-button[0] Push-button[1] Push-button[2] Push-button[3] I/O Standard Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 表 3 LED 引脚配置

Signal Name LEDR[0] LEDR[1] LEDR[2] LEDR[3] LEDR[4] LEDR[5] LEDR[6] FPGA Pin No. Description PIN_G19 PIN_F19 PIN_E19 PIN_F21 PIN_F18 PIN_E18 PIN_J19 LED Red[0] LED Red[1] LED Red[2] LED Red[3] LED Red[4] LED Red[5] LED Red[6] I/OStandard 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V LEDR[7] LEDR[8] LEDR[9] LEDR[10] LEDR[11] LEDR[12] LEDR[13] LEDR[14] LEDR[15] LEDR[16] LEDR[17] LEDG[0] LEDG[1] LEDG[2] LEDG[3] LEDG[4] LEDG[5] LEDG[6] LEDG[7] LEDG[8] PIN_H19 PIN_J17 PIN_G17 PIN_J15 PIN_H16 PIN_J16 PIN_H17 PIN_F15 PIN_G15 PIN_G16 PIN_H15 PIN_E21 PIN_E22 PIN_E25 PIN_E24 PIN_H21 PIN_G20 PIN_G22 PIN_G21 PIN_F17 LED Red[7] LED Red[8] LED Red[9] LED Red[10] LED Red[11] LED Red[12] LED Red[13] LED Red[14] LED Red[15] LED Red[16] LED Red[17] LED Green[0] LED Green[1] LED Green[2] LED Green[3] LED Green[4] LED Green[5] LED Green[6] LED Green[7] LED Green[8] 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 表 4 七段数码管引脚配置

Signal NaFPGA Pin NDescription I/O Standard me HEX0[0] o. PIN_G18 Seven Segment Digit2.5V 0[0] HEX0[1] PIN_F22 Seven Segment Digit2.5V 0[1] HEX0[2] PIN_E17 Seven Segment Digit2.5V 0[2] HEX0[3] PIN_L26 Seven Segment DigitDepending on 0[3] JP7 HEX0[4] PIN_L25 Seven Segment DigitDepending on 0[4] JP7 HEX0[5] PIN_J22 Seven Segment DigitDepending on 0[5] JP7 HEX0[6] PIN_H22 Seven Segment DigitDepending on 0[6] JP7 HEX1[0] PIN_M24 Seven Segment DigitDepending on 1[0] JP7 HEX1[1] PIN_Y22 Seven Segment DigitDepending on 1[1] JP7 HEX1[2] PIN_W21 Seven Segment DigitDepending on 1[2] JP7 HEX1[3] PIN_W22 Seven Segment DigitDepending on 1[3] JP7 HEX1[4] PIN_W25 Seven Segment DigitDepending on 1[4] JP7 HEX1[5] PIN_U23 Seven Segment DigitDepending on 1[5] HEX1[6] PIN_U24 JP7 Seven Segment DigitDepending on 1[6] JP7 HEX2[0] PIN_AA25 Seven Segment DigitDepending on 2[0] JP7 HEX2[1] PIN_AA26 Seven Segment DigitDepending on 2[1] JP7 HEX2[2] PIN_Y25 Seven Segment DigitDepending on 2[2] JP7 HEX2[3] PIN_W26 Seven Segment DigitDepending on 2[3] JP7 HEX2[4] PIN_Y26 Seven Segment DigitDepending on 2[4] JP7 HEX2[5] PIN_W27 Seven Segment DigitDepending on 2[5] JP7 HEX2[6] PIN_W28 Seven Segment DigitDepending on 2[6] JP7 HEX3[0] PIN_V21 Seven Segment DigitDepending on 3[0] JP7 HEX3[1] PIN_U21 Seven Segment DigitDepending on 3[1] JP7 HEX3[2] PIN_AB20 Seven Segment DigitDepending on 3[2] JP6 HEX3[3] PIN_AA21 Seven Segment DigitDepending on 3[3] JP6 HEX3[4] PIN_AD24 Seven Segment DigitDepending on

3[4] HEX3[5] PIN_AF23 JP6 Seven Segment DigitDepending on 3[5] JP6 HEX3[6] PIN_Y19 Seven Segment DigitDepending on 3[6] JP6 HEX4[0] PIN_AB19 Seven Segment DigitDepending on 4[0] JP6 HEX4[1] PIN_AA19 Seven Segment DigitDepending on 4[1] JP6 HEX4[2] PIN_AG21 Seven Segment DigitDepending on 4[2] JP6 HEX4[3] PIN_AH21 Seven Segment DigitDepending on 4[3] JP6 HEX4[4] PIN_AE19 Seven Segment DigitDepending on 4[4] JP6 HEX4[5] PIN_AF19 Seven Segment DigitDepending on 4[5] JP6 HEX4[6] PIN_AE18 Seven Segment DigitDepending on 4[6] JP6 HEX5[0] PIN_AD18 Seven Segment DigitDepending on 5[0] JP6 HEX5[1] PIN_AC18 Seven Segment DigitDepending on 5[1] JP6 HEX5[2] PIN_AB18 Seven Segment DigitDepending on 5[2] JP6 HEX5[3] PIN_AH19 Seven Segment DigitDepending on 5[3] HEX5[4] JP6 PIN_AG19 Seven Segment DigitDepending on 5[4] JP6 HEX5[5] PIN_AF18 Seven Segment DigitDepending on 5[5] JP6 HEX5[6] PIN_AH18 Seven Segment DigitDepending on 5[6] JP6 HEX6[0] PIN_AA17 Seven Segment DigitDepending on 6[0] JP6 HEX6[1] PIN_AB16 Seven Segment DigitDepending on 6[1] JP6 HEX6[2] PIN_AA16 Seven Segment DigitDepending on 6[2] JP6 HEX6[3] PIN_AB17 Seven Segment DigitDepending on 6[3] JP6 HEX6[4] PIN_AB15 Seven Segment DigitDepending on 6[4] JP6 HEX6[5] PIN_AA15 Seven Segment DigitDepending on 6[5] JP6 HEX6[6] PIN_AC17 Seven Segment DigitDepending on 6[6] JP6 HEX7[0] PIN_AD17 Seven Segment DigitDepending on 7[0] JP6 HEX7[1] PIN_AE17 Seven Segment DigitDepending on 7[1] JP6 HEX7[2] PIN_AG17 Seven Segment DigitDepending on 7[2] HEX7[3] JP6 PIN_AH17 Seven Segment DigitDepending on 7[3] JP6 HEX7[4] PIN_AF17 Seven Segment DigitDepending on 7[4] JP6 HEX7[5] PIN_AG18 Seven Segment DigitDepending on 7[5] JP6 HEX7[6] PIN_AA14 Seven Segment Digit3.3V 7[6] 表 5 时钟信号引脚配置信息

Signal Name FPGA Pin NDescription o. CLOCK_50 CLOCK2_50 CLOCK3_50 PIN_Y2 50 MHz clock input I/O Standard 3.3V 3.3V Depending on JP6 PIN_AG14 50 MHz clock input PIN_AG15 50 MHz clock input SMA_CLKOUT PIN_AE23 External (SMA) clock oDepending on utput JP6 SMA_CLKIN PIN_AH14 External (SMA) clock i3.3V nput 表 6 LCD 模块引脚配置

Signal Name LCD_DATA[7] LCD_DATA[6] FPGAPinNo. PIN_M5 PIN_M3 Description LCD Data[7] LCD Data[6] I/O Standard 3.3V LCD_DATA[5] LCD_DATA[4] LCD_DATA[3] LCD_DATA[2] LCD_DATA[1] LCD_DATA[0] LCD_EN LCD_RW PIN_K2 PIN_K1 PIN_K7 PIN_L2 PIN_L1 PIN_L3 PIN_L4 PIN_M1 LCD Data[5] LCD Data[4] LCD Data[3] LCD Data[2] LCD Data[1] LCD Data[0] LCD Enable 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V LCD Read/Write Selec3.3V t, 0 = Write, 1 = Read LCD_RS PIN_M2 LCD Command/Data S3.3V elect, 0 = Command, 1 = Data LCD_ON LCD_BLON PIN_L5 PIN_L6 LCD Power ON/OFF 3.3V LCD Back Light ON/O3.3V FF 表 7 HSMC 接口引脚配置

Signal Name HSMC_CLKIN0 FPGA Pin No. Description PIN_AH15 I/O Standard Dedicated clockDepending on J input P6 HSMC_CLKIN_N1 PIN_J28 LVDS RX or CDepending on JMOS I/O or diffP7 erential clock input HSMC_CLKIN_N2 PIN_Y28 LVDS RX or CDepending on JMOS I/O or diffP7 erential clock input HSMC_CLKIN_P1 PIN_J27 LVDS RX or CDepending on JMOS I/O or diffP7 erential clock input HSMC_CLKIN_P2 PIN_Y27 LVDS RX or CDepending on JMOS I/O or diffP7 erential clock input HSMC_CLKOUT0 PIN_AD28 Dedicated clockDepending on J output HSMC_CLKOUT_N1 PIN_G24 P7 LVDS TX or CDepending on JMOS I/O or diffP7 erential clock input/output HSMC_CLKOUT_N2 PIN_V24 LVDS TX or CDepending on JMOS I/O or diffP7 erential clock input/output HSMC_CLKOUT_P1 PIN_G23 LVDS TX or CDepending on JMOS I/O or diffP7 erential clock input/output HSMC_CLKOUT_P2 PIN_V23 LVDS TX or CDepending on JMOS I/O or diffP7 erential clock in

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