ug_sopc_builder-Altera FPGA嵌入式软核开发官方教程

SOPC Builder

User Guide 101 Innovation Drive

San Jose, CA 95134

b9e4216eaeaad1f346933fb2

UG-01096-1.0

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& Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective

holders as described at b9e4216eaeaad1f346933fb2/common/legal. Altera warrants performance of its semiconductor products to current specifications in accordance

with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or

liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera

customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or

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SOPC Builder User Guide December 2010Altera Corporation

Contents Chapter1.Introduction to SOPC Builder

Architecture of SOPC Builder Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 SOPC Builder Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Functions of SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5 Defining and Generating the System Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5 Creating a Memory Map for Software Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 Creating a Simulation Model and Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 SOPC Builder Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 Visualization of SOPC Builder Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8 Operating System Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8 Talkback Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8 Chapter2.System Interconnect Fabric for Memory-Mapped Interfaces

High-Level Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Fundamentals of Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Functions of System Interconnect Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Datapath Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Wait State Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Pipelined Read Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 Dynamic Bus Sizing and Native Address Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 Dynamic Bus Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 Native Address Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8 Arbitration for Multimaster Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 Traditional Shared Bus Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 Slave-Side Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10 Arbiter Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11 Arbitration Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12 Burst Adapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 Inpidual Requests IRQ Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 Priority Encoded Interrupt Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 Assigning IRQs in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16 Reset Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16 Chapter3.System Interconnect Fabric for Streaming Interfaces

High-Level Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Avalon Streaming and Avalon Memory-Mapped Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Adapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 Data Format Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4 Timing Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4 Channel Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 Error Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 Multiplexer Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 Example to Double Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 Example to Double Data Width and Maintain Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 Example to Boost the Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 December 2010Altera Corporation SOPC Builder User Guide

ii Contents Chapter4.SOPC Builder Components

Component Providers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1 Component Hardware Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 Component Instances Inside the SOPC Builder System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 Components Outside the SOPC Builder System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Exported Connection Points—Conduit Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 SOPC Builder Component Search Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 Installing Additional Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 Copy to the IP Root Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 Reference Components in an .ipx File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6 Understanding IPX File Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7 Upgrading from Earlier Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 Component Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 Component Description File (_hw.tcl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Component File Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Component Versioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Classic Components in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10 b9e4216eaeaad1f346933fb2ing SOPC Builder with the Quartus II Software

Quartus II IP File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 Quartus II Incremental Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 TimeQuest Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2 Analyzing PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2 Analyzing Slow Asynchronous I/O Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3 Analyzing Single Data Rate SDRAM and SSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4 Analyzing Tristate Bridges and Asynchronous Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6 Analyzing DDR and DDR2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7 b9e4216eaeaad1f346933fb2ponent Editor

Component Hardware Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1 Starting the Component Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 HDL Files Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 Bottom-Up Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 Top-Down Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3 Signals Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3 Naming Signals for Automatic Type and Interface Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4 Templates for Interfaces to External Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5 Interfaces Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6 HDL Parameters Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6 Library Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7 Saving a Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7 Editing a Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 Software Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 Component Parameterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 b9e4216eaeaad1f346933fb2ponent Interface Tcl Reference

Information in a Hardware Component Description File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1 Component Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2 Writing a Hardware Component Description File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2 Providing Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3 Declaring Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3 Declaring Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5 Adding Files and Guiding Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5 SOPC Builder User Guide December 2010Altera Corporation

Contents iii Default Behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6 Validation Phase Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6 Elaboration Phase Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6 Generation Phase Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7 Edit Phase Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7 Overriding Default Behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8 Validation Callback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9 Elaboration Callback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9 Generation Callback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10 Editor Callback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11 Hardware Tcl Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12 Module Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Display Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–29 Interfaces and Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–32 Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–38 Deprecated Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–40 Chapter8.Archiving SOPC Builder Projects

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1 Required Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2 Chapter9.SOPC Builder Memory Subsystem Development Walkthrough

Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1 Example Design Starting Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3 Hardware and Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4 Component-Level Design in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4 SOPC Builder System-Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5 Quartus II Project-Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5 Board-Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5 Simulation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5 On-Chip RAM and ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–6 Component-Level Design for On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–6 SOPC Builder System-Level Design for On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8 Simulation for On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8 Quartus II Project-Level Design for On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8 Board-Level Design for On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8 Example Design with On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8 EPCS Serial Configuration Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9 Component-Level Design for an EPCS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9 SOPC Builder System-Level Design for an EPCS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9 Simulation for an EPCS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9 Quartus II Project-Level Design for an EPCS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10 Board-Level Design for an EPCS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10 Example Design with an EPCS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10 SDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11 Component-Level Design for SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11 SOPC Builder System-Level Design for SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11 Simulation for SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11 Quartus II Project-Level Design for SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12 Board-Level Design for SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12 December 2010Altera Corporation SOPC Builder User Guide

iv Contents Example Design with SDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12 DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14 DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14 Off-Chip SRAM and Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–15 Component-Level Design for SRAM and Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–15 SOPC Builder System-Level Design for SRAM and Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 9–17 Simulation for SRAM and Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–17 Quartus II Project-Level Design for SRAM and Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–18 Board-Level Design for SRAM and Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–18 Example Design with SRAM and Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–20

Chapter10.SOPC Builder Component Development Walkthrough

SOPC Builder Components and the Component Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1 Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1 Hardware and Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2 Component Development Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2 Typical Design Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2 Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3 Design Example: Checksum Hardware Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4 Software Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–6 Verifying the Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–6 Sharing Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–7 System Information Files (.sopcinfo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–7 Chapter11.Avalon Memory-Mapped Bridges

Structure of a Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2 Reasons for Using a Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2 Address Mapping for Systems with Avalon-MM Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–6 Avalon-MM Pipeline Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–8 Component Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–10 Clock Crossing Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–12 Choosing Clock Crossing Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–13 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–13 Instantiating the Avalon-MM Clock-Crossing Bridge in SOPC Builder . . . . . . . . . . . . . . . . . . . . . 11–17 Clock Domain Crossing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–17 Description of Clock Domain Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–18 Location of Clock Domain Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–19 Duration of Transfers Crossing Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–19 Implementing Multiple Clock Domains in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–20 Avalon-MM DDR Memory Half-Rate Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–20 Resource Usage and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–21 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–22 Instantiating the Core in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–23 Example System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–24 Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–25 Hardware Simulation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–25 Software Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–25 Chapter12.Avalon Streaming Interconnect Components

Interconnect Component Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2 Timing Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2 SOPC Builder User Guide December 2010Altera Corporation

Contents v Resource Usage and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4 Instantiating the Timing Adapter in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4 Data Format Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–5 Resource Usage and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–6 Instantiating the Data Format Adapter in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–6 Channel Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–7 Resource Usage and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–8 Instantiating the Channel Adapter in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–8 Error Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–9 Instantiating the Error Adapter in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–9 Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–10 Hardware Simulation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–10 Software Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–10

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 December 2010Altera Corporation SOPC Builder User Guide

vi Contents SOPC Builder User Guide December 2010Altera Corporation

1.Introduction to SOPC Builder

SOPC Builder is a powerful system development tool. SOPC Builder enables you to

define and generate a complete system-on-a-programmable-chip (SOPC) in much less

time than using traditional, manual integration methods. SOPC Builder is included as

part of the Quartus II software. For a quick introduction on how to use SOPC Builder,

follow these general steps:

■Install the Quartus? II software, which includes SOPC Builder. This is available at b9e4216eaeaad1f346933fb2.

■Take advantage of the one-hour online course, Using SOPC Builder.

■Download and run the checksum sample design described in Chapter9, SOPC

Builder Memory Subsystem Development Walkthrough.

You may have used SOPC Builder to create systems based on the Nios?II processor.

However, SOPC Builder is more than a Nios II system builder; it is a general-purpose

tool for creating systems that may or may not contain a processor and may include a

soft processor other than the Nios II processor.

SOPC Builder automates the task of integrating hardware components. Using

traditional design methods, you must manually write HDL modules to wire together

the pieces of the system. Using SOPC Builder, you specify the system components in a

GUI and SOPC Builder generates the interconnect logic automatically. SOPC Builder

generates HDL files that define all components of the system, and a top-level HDL file

that connects all the components together. SOPC Builder generates either Verilog

HDL or VHDL equally.

In addition to its role as a system generation tool, SOPC Builder provides features to

ease writing software and to accelerate system simulation. This chapter includes the

following sections:

■“Architecture of SOPC Builder Systems” on page1–1

■“Functions of SOPC Builder” on page1–5

■“Operating System Support” on page1–8

■“Talkback Support” on page1–8

Architecture of SOPC Builder Systems

An SOPC Builder component is a design module that SOPC Builder recognizes and

can automatically integrate into a system. You can also define and add custom

components or select from a list of provided components. SOPC Builder connects

multiple modules together to create a top-level HDL file called the SOPC Builder

system. SOPC Builder generates system interconnect fabric that contains logic to

manage the connectivity of all modules in the system.

December 2010Altera Corporation SOPC Builder User Guide

1–2Chapter 1:Introduction to SOPC Builder

Architecture of SOPC Builder Systems SOPC Builder Modules

1This document refers to components as the class definition for a module, for example a Nios?II processor. An instance is a parameterization of a component that's been added

to a system, for example cpu_0.

SOPC Builder modules are the building blocks for creating an SOPC Builder system.

SOPC Builder modules use Avalon? interfaces, such as memory-mapped, streaming,

and IRQ, for the physical connection of components. You can use SOPC Builder to

connect any logical device (either on-chip or off-chip) that has an Avalon interface.

There are different types of Avalon interfaces, as described in the Avalon Interface

Specifications.

f For details on the Avalon-MM interface refer to Chapter2, System Interconnect Fabric

for Memory-Mapped Interfaces. For details on the Avalon-ST interface, refer to

Chapter3, System Interconnect Fabric for Streaming Interfaces. For details about the

Avalon-ST interface protocol, refer to Avalon Interface Specifications.

SOPC Builder User Guide December 2010Altera Corporation

Chapter 1:Introduction to SOPC Builder1–3 Architecture of SOPC Builder Systems

Example System

Figure1–1 shows an FPGA design that includes an SOPC Builder system and custom

logic modules. You can integrate custom logic inside or outside the SOPC Builder

system. In this example, the custom component inside the SOPC Builder system

communicates with other modules through an Avalon-MM master interface. The

custom logic outside of the SOPC Builder system is connected to the SOPC Builder

system through a PIO interface. The SOPC Builder system includes two SOPC Builder

components with Avalon-ST source and sink interfaces. The system interconnect

fabric connects all of the SOPC Builder components using the Avalon-MM or

Avalon-ST system interconnect as appropriate.

Figure1–1.Example of an FPGA with a SOPC Builder System Generated by SOPC Builder

December 2010Altera Corporation SOPC Builder User Guide

1–4Chapter 1:Introduction to SOPC Builder

Architecture of SOPC Builder Systems

SOPC Builder User Guide December 2010Altera Corporation A component can be a logical device that is entirely contained within the SOPC

Builder system, such as the processor component shown in Figure 1–1. Alternately, a

component can act as an interface to an off-chip device, such as the DDR2 interface

component in Figure 1–1. In addition to the Avalon interface, a component can have

other signals that connect to logic outside the SOPC Builder system. Non-Avalon

signals can provide a special-purpose interface to the SOPC Builder system, such as

the PIO in Figure 1–1. These non-Avalon signals are described in Conduit Interface

chapter in the Avalon Interface Specifications .

Available Components

Altera and third-party developers provide ready-to-use SOPC Builder components,

including:

■

Microprocessors, such as the Nios II processor ■

Microcontroller peripherals, such as a Scatter-Gather DMA Controller and timer ■Serial communication interfaces, such as a UART and a serial peripheral interface

(SPI)

■General purpose I/O

■Communications peripherals, such as a 10/100/1000 Ethernet MAC

■

Interfaces to off-chip devices Custom Components

You can import HDL modules and entities that you write using Verilog HDL or

VHDL into SOPC builder as custom components. You use the following design flow

to integrate custom logic into an SOPC Builder system:

1.Determine the interfaces used to interact with your custom component.

2.Create the component logic using either Verilog HDL or VHDL.

b9e4216eaeaad1f346933fb2e the SOPC Builder component editor to create an SOPC Builder component

with your HDL files.

4.Instantiate your component in the system.

Once you have created an SOPC Builder component, you can use the component in

other SOPC Builder systems, and share the component with other design teams.

f For instructions on developin

g a custom SOPC Builder component, the details about

the file structure of a component, or the component editor, refer to Chapter 4, SOPC

Builder Components .

f For details on the Avalon-MM interface refer to Chapter 2, System Interconnect Fabric

for Memory-Mapped Interfaces . For details on the Avalon-ST interface, refer to

Chapter 3, System Interconnect Fabric for Streaming Interfaces .

Chapter 1:Introduction to SOPC Builder

1–5

Functions of SOPC Builder December 2010Altera Corporation SOPC Builder User Guide Third-Party Components

You can also use SOPC-ready components that were developed by third-parties.

Altera awards the SOPC Builder Ready certification to IP functions that are ready to integrate with the Nios II embedded processor or the system interconnect fabric via SOPC Builder. These cores support the Avalon-MM interface or the Avalon Streaming (Avalon-ST) interface and may include constraints, software drivers, simulation models, and reference designs when applicable.

To find SOPC Builder Ready third-party components that you can purchase and use in SOPC Builder systems, complete the following steps:

1.On the Tools menu in SOPC Builder, click Download Components .

2.On the Intellectual Property Solutions web page, type SOPC Builder ready r in

the box labeled Search for IP , Development Kits and Reference Designs .

Functions of SOPC Builder

This section describes the functions of SOPC Builder.

Defining and Generating the System Hardware

SOPC Builder allows you to design the structure of a hardware system. The GUI allows you to add components to a system, configure the components, and specify connectivity.

After you add and parameterize components, SOPC Builder generates the system interconnect fabric, and outputs HDL files to your project directory. During system generation, SOPC Builder creates the following items:

■An HDL file for the top-level SOPC Builder system and for each component in the

system. The top-level HDL file is named .v for Verilog HDL designs and .vhd for VHDL designs.

■Synopsis Design Constraints file (.sdc ) for timing analysis.

■ A Block Symbol File (.bsf ) representation of the top-level SOPC Builder system for use in Quartus II Block Diagram Files (.bdf ).

■An example of an instance of the top-level HDL file, .v or .vhd , which demonstrates how to instantiate the top-level HDL file in your code.

■ A data sheet called that provides a system overview

including the following information:

■

All external connections for the system ■ A memory map showing the address of each Avalon-MM slave with respect to

each Avalon-MM master to which it is connected

■

All parameter assignments for each component ■ A functional test bench for the SOPC Builder system and ModelSim ? simulation

project files

1–6Chapter 1:Introduction to SOPC Builder

SOPC Builder Design Flow

SOPC Builder User Guide December 2010Altera Corporation ■SOPC information file (.sopcinfo) that describes all of the components and

connections in your system. This file is a complete system description, and is used

by downstream tools such as the Nios II tool chain. It also describes the

parameterization of each component in the system; consequently, you can parse its

contents to get requirements when developing software drivers for SOPC Builder

components.

■ A Quartus II IP File (.qip ) that provides the Quartus II software with all required

information about your SOPC Builder system. The .qip file includes references to

the following information:

■

HDL files used in the SOPC Builder system ■

TimeQuest Timing Analyzer Synopsys Design Constraint (.sdc ) files ■Component definition files for archiving purposes

After you generate the SOPC Builder system, you can compile it with the Quartus II

software, or you can instantiate it in a larger FPGA design.

Creating a Memory Map for Software Development

When your SOPC Builder system includes a Nios II processor, SOPC Builder

generates a header file, cpu.h , that provides the base address of each Avalon-MM

slave component. In addition, each slave component can provide software drivers

and other software functions and libraries for the processor. You can create C header

files for your system using the sopc-create-header-files utility.

f For details type sopc-create-header-files --help in a Nios II Command shell.

f For more details about how to provide Nios II software drivers for components, refer

to the Developing Device Drivers for the Hardware Abstraction Layer chapter of the Nios II

Software Developer’s Handbook . The Nios II EDS is separate from SOPC Builder, but it

uses the output of SOPC Builder as the foundation for software development.

Creating a Simulation Model and Test Bench

You can simulate your system after generating it with SOPC Builder. During system

generation, SOPC Builder outputs a simulation test bench and a ModelSim setup

script that eases the system simulation effort. The test bench does the following:

■

Instantiates the SOPC Builder system ■

Drives all clocks and resets ■Instantiates simulation models for off-chip devices when available

SOPC Builder Design Flow

Figure 1–2 illustrates an example bottom-up design flow in SOPC Builder which

starts with component design. As this flow diagram illustrates, the typical design flow

includes the following high-level steps:

1.Package your component for SOPC Builder using the Component Editor.

Chapter 1:Introduction to SOPC Builder1–7 SOPC Builder Design Flow

2.Simulate at the unit-level, possibly incorporating Avalon BFMs to verify the

system.

b9e4216eaeaad1f346933fb2plete the SOPC Builder design by adding other components, specifying

interrupts, clocks, resets, and addresses.

4.Generate the SOPC Builder system.

5.Perform system level simulation.

6.Constrain and compile the design.

7.Download the design to an Altera device.

8.Test in hardware.

Figure1–b9e4216eaeaad1f346933fb2plete Qsys Design Flow

December 2010Altera Corporation SOPC Builder User Guide

1–8Chapter 1:Introduction to SOPC Builder

Visualization of SOPC Builder Systems 1In the alternative top-down valid design flow, you begin by designing the SOPC Builder system and then define and instantiate custom SOPC Buildder component.

This approach clarifies the system requirements earlier in the design process.

Designs targeting HardCopy devices are require specific design constraints.

Consequently, if you are targeting a HardCopy series device, you must verify you

design for the HardCopy companion device.

Follow these guidelines to verify your design for both devices:

1.In the Quartus II Device dialog box, select both the FPGA and the appropriate

HardCopy companion device.

2.In Step 8 of the design flow shown in Figure1–2, compile for both the FPGA and

HardCopy device.

3.After Step 10 of the design flow shown in Figure1–2, if FPGA passes all functional

simulation and hardware verification tests, generate the HardCopy handoff

archive and send this archive to the HardCopy Design Center for the backend flow

and tapeout.

Visualization of SOPC Builder Systems

You can use the Filters dialog box to customize the display of your system in the

connections panel. You can filter the display of your system by interface type, instance

name, interface type, or using custom tags. For example, you can use filtering to view

only instances that include an Avalon-MM interface or instances that are connected to

a particular Nios II processor. For more information, refer to Quartus II online Help.

Operating System Support

SOPC Builder supports all of the operating systems that the Quartus II software

supports.

f For details on installation and licensing, refer to the Altera Software Installation and

Licensing Manual.

Talkback Support

Talkback is a Quartus II software feature that provides feedback to Altera on tool and

IP feature usage. Altera uses the data to help guide future product planning efforts.

Talkback sends Altera information on the Altera components you use, including:

interface types, interface properties, parameter names and values, clocking, and

software assignments. For components from Altera, Talkback sends the component

parameter values to help understand what features of the component are being used.

For non-Altera components, Talkback collects information about how interfaces such

as Avalon-MM are being used. Connectivity between components is not sent. The

Talkback file does not include information about system connectivity, interrupts, or

the memory map seen by each master in the system. Talkback collects the same very

general information about your proprietary components.

The Talkback feature is enabled by default. You can disable Talkback from within the

Quartus II software if you do not wish to share your usage data with Altera.

SOPC Builder User Guide December 2010Altera Corporation

2.System Interconnect Fabric for

Memory-Mapped Interfaces The system interconnect fabric for memory-mapped interfaces is a high-bandwidth

interconnect structure for connecting components that use the Avalon?

Memory-Mapped (Avalon-MM) interface. The system interconnect fabric consumes

less logic, provides greater flexibility, and higher throughput than a typical shared

system bus. It is a cross-connect fabric and not a tristated or time domain multiplexed

bus. This chapter describes the functions of system interconnect fabric for

memory-mapped interfaces and the implementation of those functions.

High-Level Description

The system interconnect fabric is the collection of interconnect and logic resources

that connects Avalon-MM master and slaves on components in a system. SOPC

Builder generates the system interconnect fabric to match the needs of the

components in a system. The system interconnect fabric implements the connection

details of a system. It guarantees that signals are routed correctly between master and

slaves, as long as the ports adhere to the rules of the Avalon Interface Specifications. This

chapter provides information on the following topics:

■“Address Decoding” on page2–3

■“Datapath Multiplexing” on page2–4

■“Wait State Insertion” on page2–5

■“Pipelined Read Transfers” on page2–6

■“Dynamic Bus Sizing and Native Address Alignment” on page2–6

■“Arbitration for Multimaster Systems” on page2–9

■“Burst Adapters” on page2–14

■“Interrupts” on page2–15

■“Reset Distribution” on page2–16

f For details about the Avalon-MM interface, refer to the Avalon Interface Specifications.

System interconnect fabric for memory-mapped interfaces supports the following

items:

■Any number of master and slave components. The master-to-slave relationship can be one-to-one, one-to-many, many-to-one, or many-to-many.

■On-chip components.

■Interfaces to off-chip devices.

■Master and slaves of different data widths.

■Components operating in different clock domains.

■Components using multiple Avalon-MM ports.

December 2010Altera Corporation SOPC Builder User Guide

2–2

Chapter 2:System Interconnect Fabric for Memory-Mapped Interfaces

High-Level Description

SOPC Builder User Guide December 2010Altera Corporation

Figure 2–1 shows a simplified diagram of the system interconnect fabric in an example memory-mapped system with multiple masters.

1

All figures in this chapter are simplified to show only the particular function being discussed. In a complete system, the system interconnect fabric might alter the

address, data, and control paths beyond what is shown in any one particular figure.

SOPC Builder supports components with multiple Avalon-MM interfaces, such as the processor component shown in Figure 2–1. Because SOPC Builder can create system interconnect fabric to connect components with multiple interfaces, you can create complex interfaces that provide more functionality than a single Avalon-MM

interface. For example, you can create a component with two different Avalon-MM slaves, each with an associated interrupt interface.

System interconnect fabric can connect any combination of components, as long as each interface conforms to the Avalon Interface Specifications . It can, for example, connect a system comprised of only two components with unidirectional dataflow between them. Avalon-MM interfaces are suitable for random address transactions, such as to memories or embedded peripherals.

Figure 2–1.System Interconnect Fabric—Example System

Write Data & Control Si g nals Read Data

Interface to Off-Chip Device

M S

Avalon-MM Master Port

Avalon-MM Slave Port

Chapter 2:System Interconnect Fabric for Memory-Mapped Interfaces2–3 Fundamentals of Implementation

Generating system interconnect fabric is SOPC Builder’s primary purpose. In most

cases, you are not required to modify the generated HDL; however, a basic

understanding of how HDL works can help you optimize your system. For example,

knowledge of the arbitration algorithm can help designers of multimaster systems

minimize the impact of arbitration on the system throughput.

Fundamentals of Implementation

System interconnect fabric for memory-mapped interfaces implements a partial

crossbar interconnect structure that provides concurrent paths between master and

slaves. System interconnect fabric consists of synchronous logic and routing resources

inside the FPGA.

For each component interface, system interconnect fabric manages Avalon-MM

transfers, interacting with signals on the connected component. Master and slave

interfaces can contain different signals and the system interconnect fabric handle any

adaptation necessary between them. In the path between master and slaves, the

system interconnect fabric might introduce registers for timing synchronization, finite

state machines for event sequencing, or nothing at all, depending on the services

required by the specific interfaces.

f For more information, refer to the Avalon Memory-Mapped Design Optimizations

chapter in the Embedded Design Handbook.

Functions of System Interconnect Fabric

System interconnect fabric logic provides the following functions:

■“Address Decoding” on page2–3

■“Datapath Multiplexing” on page2–4

■“Wait State Insertion” on page2–5

■“Pipelined Read Transfers” on page2–6

■“Arbitration for Multimaster Systems” on page2–9

■“Burst Adapters” on page2–14

■“Interrupts” on page2–15

■“Reset Distribution” on page2–16

The behavior of these functions in a specific SOPC Builder system depends on the

design of the components in the system and the settings made in SOPC Builder. The

remaining sections of this chapter describe how SOPC Builder implements each

function.

Address Decoding

Address decoding logic in the system interconnect fabric forwards appropriate

addresses to each slave. Address decoding logic simplifies component design in the

following ways:

December 2010Altera Corporation SOPC Builder User Guide

2–4Chapter 2:System Interconnect Fabric for Memory-Mapped Interfaces

Datapath Multiplexing

SOPC Builder User Guide December 2010Altera Corporation ■The system interconnect fabric selects a slave whenever it is being addressed by a

master. Slave components do not need to decode the address to determine when

they are selected.

■Slave addresses are properly aligned to the slave interface.

■

Changing the system memory map does not involve manually editing HDL. Figure 2–2 shows a block diagram of the address-decoding logic for one master and

two slaves. Separate address-decoding logic is generated for every master in a system.

As Figure 2–2 shows, the address decoding logic handles the difference between the

master address width () and the inpidual slave address widths ( and ).

It also maps only the necessary master address bits to access words in each slave’s

address space.

In SOPC Builder, the user-configurable aspects of address decoding logic are

controlled by the Base setting in the list of active components on the System Contents

tab, as shown in Figure 2–3.

Datapath Multiplexing

Datapath multiplexing logic in the system interconnect fabric drives the writedata

signal from the granted master to the selected slave, and the readdata signal from the

selected slave back to the requesting master.

Figure 2–2.Block Diagram of Address Decoding Logic

Figure 2–3.Base Settings in SOPC Builder Control Address Decoding

Chapter 2:System Interconnect Fabric for Memory-Mapped Interfaces2–5 Wait State Insertion

Figure2–4 shows a block diagram of the datapath multiplexing logic for one master

and two slaves. SOPC Builder generates separate datapath multiplexing logic for

every master in the system.

Figure2–4.Block Diagram of Datapath Multiplexing Logic

In SOPC Builder, the generation of datapath multiplexing logic is specified using the

connections panel on the System Contents tab.

Wait State Insertion

Wait states extend the duration of a transfer by one or more cycles. Wait state insertion

logic accommodates the timing needs of each slave, and causes the master to wait

until the slave can proceed. System interconnect fabric inserts wait states into a

transfer when the target slave cannot respond in a single clock cycle. System

interconnect fabric also inserts wait states in cases when slave read_enable and

write_enable signals have setup or hold time requirements.

Wait state insertion logic is a small finite-state machine that translates control signal

sequencing between the slave side and the master side. Figure2–5 shows a block

diagram of the wait state insertion logic between one master and one slave.

Figure2–5.Block Diagram of Wait State Insertion Logic

System interconnect fabric can force a master to wait for several reasons in addition to

the wait state needs of a slave. For example, arbitration logic in a multimaster system

can force a master to wait until it is granted access to a slave.

December 2010Altera Corporation SOPC Builder User Guide