FPGA可编程逻辑器件芯片XC6VHX380T-2FFG1923I中文规格书

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

Shared PMA PLL

Overview

This section describes the shared PMA PLL of the GTX_DUAL tile (Figure 5-1). Each

GTX_DUAL tile includes one shared PMA PLL used to generate a high-speed serial clock from a high-quality reference clock (CLKIN). The high-speed clock from this block drives the TX and RX PMA blocks for both GTX transceivers in the tile.

The shared PMA PLL generates the high-speed clock (PLL clock) used by both transceivers in the GTX_DUAL tile. After the shared PMA PLL rate is set (PLL clock), the TX and RX output dividers (dividers ending with _OUT) are set to determine the TX and RX line rates for each transceiver.

Figure 5-1:Shared PMA PLL Detail

Notes:

1.The Serial In Parallel Out (SIPO) block in each receiver uses both edges of the high-speed clock. As a result, the effective RX serial clock rate is 2 x PLL Clock/PLL_RXDIVSEL_OUT_n.

2.The Parallel In Serial Out (PISO) block in each transmitter uses both edges of the high-speed clock. As a result, the effective TX serial clock rate is 2 x PLL Clock/PLL_TXDIVSEL_OUT_n.

3.The parallel clock rate is divided to match the internal datapath width. When INTDATAWIDTH = 0 (16-bit internal width), W =8. When INTDATAWIDTH =1 (20-bit internal width), W =10.

4.Refer to Chapter 9, “Loopback,” about the correct setting of these attributes for specific loopback modes.

5.Nominal operating range.

6.The nominal operating range of the shared PMA PLL in a GTX_DUAL tile is 1.5GHz to 3.25GHz. The nominal operation range of the shared PMA PLL in a GTP_DUAL tile is 1.0GHz to 2.0GHz.

RocketIO GTX Transceiver User Guide UG198 (v3.0) October 30, 2009

Reset

The reset that occurs after configuration and the GTXRESET port are the most common ways to prepare GTX_DUAL(s) for operation, but certain situations can require the use of other reset ports. Table 5-9 outlines some of these situations and indicates the recommended resets.

RX PMA SIPO ????RX CDR

????

RX Termination and Equalization ???RX OOB

????

Loopback Loopback paths

?

?

?

Table 5-8:Available Resets Pins and the Components Reset by These Reset Pins (Cont’d)

Component

Configuration

GTXRESET

PLLPOWERDOWN (Falling Edge)

TXRESET0TXRESET1

RXCDRRESET0RXCDRRESET1

RXRESET0RXRESET1

RXBUFRESET0RXBUFRESET1

PRBSCNTRESET0PRBSCNTRESET1

Table 5-9:

Recommended Resets for Common Situations Situation

Components to be Reset Recommended Reset (1)

After power up and configuration Entire GTX_DUAL tile Reset after configuration is automatic After turning on a reference clock Shared PMA PLL GTXRESET After changing a reference clock Shared PMA PLL

GTXRESET

Parallel clock source reset TX PCS, RX PCS, Phase Alignment TXRESET0, TXRESET1, RXRESET0,

RXRESET1After remote power up

RX CDR A built-in reset sequencer automatically sets these situations by setting RX_EN_IDLE_RESET_PH, RX_EN_IDLE_RESET_FR,

RX_EN_IDLE_HOLD_CDR to TRUE.After PCI Express electrical idle condition

RX CDR After connecting RXN/RXP RX CDR After a TX buffer error TX Buffer TXRESET0, TXRESET1

After an RX buffer error RX Elastic Buffer

RXBUFRESET0, RXBUFRESET1

Before channel bonding

RX CDR, then RXBUFFER after CDR is locked

Either assert RXBUFRESET, or automatically reset by setting

RX_EN_IDLE_RESET_BUF =TRUE to enable the RXBUFRESET0/RXBUFRESET1 sequence

After PRBS error PRBS Error counter PRBSCNTRESET0, PRBSCNTRESET1After oversampler error

Oversampler

RXRESET0, RXRESET1

Notes:

1.The recommended reset has the smallest impact on the other components of the GTX_DUAL tile.

Chapter 5:Tile Features

Examples

Power-up and Configuration

All GTX_DUAL tiles are reset automatically after configuration. The supplies for the

calibration resistor and calibration resistor reference must be powered up before

configuration to ensure correct calibration of the termination impedance of all transceivers.

After Turning on a Reference Clock

The reference clock source(s) and the power to the GTX_DUAL tile must be available

before configuring the FPGA. The reference clock must be stable before configuration

especially when using PLL based clock sources (e.g., voltage controlled crystal oscillators).

If the reference clock(s) or GTX_DUAL tile(s) are powered up after configuration, apply

GTXRESET to allow the shared PMA PLL(s) to lock.

After Changing a Reference Clock

Whenever the reference clock input to a GTX_DUAL tile is changed, the shared PMA PLL

must be reset afterwards to ensure that it locks to the new frequency. The GTXRESET port

must be used for this purpose.

Parallel Clock Source Reset

The clocks driving TXUSRCLK, RXUSRCLK, TXUSRCLK2, and RXUSRCLK2 must be

stable for correct operation. These clocks are often driven from a PLL or DCM in the FPGA

to meet phase and frequency requirements. If the DCM or PLL loses lock, and begins

producing incorrect output, TXRESET and RXRESET must be used to hold transceiver PCS

in reset until the clock source is locked again.

If the TX or RX buffer is bypassed and phase alignment is in use, phase alignment must be

performed again after the clock source relocks.

Note:Bypassing the TX or RX buffer is an advanced feature and is not recommended for normal

operation. TX or RX buffer bypass operation can be guaranteed only under certain system-level

conditions and data rates.

After Remote Power-up

If the remote source of incoming data is powered up after the GTX transceiver receiving its

data is operating, the RX CDR must be reset to ensure a clean lock to the incoming data. By

following the guidelines in “Link Idle Reset Support,” page 105, the electrical idle reset

situation is automatically managed.

Electrical Idle Reset

When the differential voltage of the RX input to a GTX transceiver drops to OOB or

electrical idle levels, the RX CDR can be pulled out of lock by the apparent sudden change

in frequency. By following the guidelines in “Link Idle Reset Support,” page 105, the

electrical idle reset situation is automatically managed.

After Connecting RXP/RXN

When the RX data to the GTX transceiver comes from a connector that can be plugged in

and unplugged, the RX CDR must be reset when the data source is plugged in to ensure

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

Reset

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

RocketIO GTX Transceiver User Guide UG198 (v3.0) October 30, 2009Chapter 5:Tile Features

Power Control

Overview

The GTX_DUAL tiles support a range of power-down modes. These modes support both

generic power management capabilities as well as those defined in the PCI Express and

SATA standards.

Ports and Attributes

Table 5-10 defines the power ports.

Table 5-10:Power Ports Port

Dir Domain Description CLKIN In N/A Reference clock input to the shared PMA PLL. The CLKIN rate in conjunction with CLK25_DIVIDER determines the timing of

power-down state transitions for PCI Express designs.

PLLPOWERDOWN (1)In Async Powers down the shared PMA PLL:

0: Shared PMA PLL is powered up

1: Shared PMA PLL is powered down

REFCLKPWRDNB (2)In Async Powers down the part of the GTX reference clock circuit between

the differential clock pair input pin and the dedicated clock

routing circuit:

0: Circuit used to bring in CLKP and CLKN is powered down

1: Circuit used to bring in CLKP and CLKN is powered up

RXPOWERDOWN0[1:0]RXPOWERDOWN1[1:0]In Async Powers down the RX lanes. The encoding complies with PCI

Express encoding. TX and RX can be powered down separately.

However, for PCI Express compliance, TXPOWERDOWN and

RXPOWERDOWN must be used together.

00: P0 (normal operation)

01: P0s (low recovery time power down)

10: P1 (longer recovery time; Receiver Detection is still on)

11: P2 (lowest power state)

TXDETECTRX0TXDETECTRX1In TXUSRCLK2Activates the receive detection sequence. The sequence ends when

PHYSTATUS is asserted to indicate that the results of the test are

ready on RXSTATUS.

TXELECIDLE0TXELECIDLE1In TXUSRCLK2

Drives TXN and TXP to the same voltage to perform electrical

idle/beaconing for PCI Express designs.

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