IC design flow& relevant desing tools（集成电路设计流程与EDA

Design Flow Code Editors/Doc Editors FrontEnd

Design Details Simulation Debug Lint Checking Equivalence Checking Coverage Tools Vi/Vim Emacs FrameMake Office VCS NC-Verilog(IUS) Verilog XL ModelSim Debussy Verdi Simvision DVE HAL SpyGlass 0-in Checklist nLint LEC Conformal ASIC SLV HDLScore ICC InfiniteStream VCS Coverage Company GNU GNU Adobe Microsoft Sunopsys Cadence Cadence Mentor SpringSoft/Novas SpringSoft/Novas Cadence Synopsys Cadence Atrenta Archer SpringSoft/Novas Cadence/Verplex Cadence Cadence Summit Cadence Cacence Synopsys

Metrics FrontEnd-BackEnd DFT

Formal Verification SV Verification Assertion Based Verification CDC ECO Low Power Analysis Emulation Synthesis STA Fromality BlackTie IFV Open Vera Specman Elite VCS/SystemVerilog Incisive Questa SVA OVL CBV 0-In CDC nECO Power Compiler Power Theater Palladium Design Compiler RTL Compiler Physical Compiler PrimeTime DFT Compiler Synopsys Cadence/Verplex Cadence Synopsys Verisity Synopsys Cadence Mentor Mentor SpringSoft/Novas Synopsys Sequence Cadence Synopsys Cadence Synopsys Synopsys Synopsys

BackEnd P&R LVS/DRC BSD Compiler DFT MAX TetraMAX ATPG Encounter Silicon Ensemble IC Compiler Appollo Magma Dracula Hercules Calibre Synopsys Synopsys Synopsys Cadence Cadence Synopsys Magma Cadence Synopsys Mentor Graphics

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