VHDL设计的12进制可调时钟带闹铃功能 - 图文

VHDL设计的12进制可调时钟带闹铃功能

1、 顶层原理图如下：

2、 各模块生成的电路符号如下：

分频模块 计数模块 闹铃模块

二选一模块

设置闹铃时间模块 显示模块

3、 各模块程序清单如下：

（1）、分频模块（将开发板上的50Mhz的信号进行分频得

到1hz的计时信号和1khz的位选信号）

library ieee; --对开发板上的50MHZ信号进行分频得到1khz和1hz信号 use ieee.std_logic_1164.all;

entity div_freq is

port(freq_in:in std_logic;

flag_1khz,flag_1hz: buffer std_logic); end entity;

architecture one of div_freq is signal complete_1khz: integer range 0 to 50000; signal complete_1hz: integer range 0 to 1000; signal test_out:std_logic; begin process(freq_in) --此进程得到的是1khz的信号 begin if(freq_in 'event and freq_in='1') then complete_1khz<=complete_1khz+1; if(complete_1khz=50000) then complete_1khz<=0; elsif(complete_1khz<25000) then flag_1khz<='0'; else flag_1khz<='1'; end if; end if; end process; process(flag_1khz) --此进程是得到1hz信号 begin if(flag_1khz 'event and flag_1khz='1') then complete_1hz<=complete_1hz+1; if(complete_1hz=1000)then complete_1hz<=0; flag_1hz<='0'; else flag_1hz<='1'; end if; end if; test_out<=flag_1hz; end process; end architecture one;

（2）、计时模块

library ieee; --此模块是时分秒计时程序 use ieee.std_logic_1164.all;

entity counter is

port(flag_1hz:in std_logic; --1hz信号到来时开始计时

pause:in std_logic; --计时与调整的选择，决定是自动计时还是按

键调整时间

add_min:in std_logic; --按键调整分的信号 add_hour:in std_logic; --按键调整时的信号 cnt_60s:out integer range 0 to 59; --秒计数值 cnt_60m:out integer range 0 to 59; --分计数值 cnt_12h:out integer range 0 to 11); --时计数值 end entity;

architecture one of counter is signal sc_c:std_logic; --秒的进位信号 signal min_c:std_logic; --分的进位信号 signal selector_min:std_logic; --存放秒的进位信号或者分调整

的按键信号

signal selector_hour:std_logic; --存放分的进位信号或者时调整

的按键信号

begin process(flag_1hz) --此进程是进行60秒计时 variable cnt_60s_v:integer range 0 to 59; --存放秒计时

的中间变量，最后传到秒输出端cnt_60s

begin if(flag_1hz 'event and flag_1hz='1') then if(cnt_60s_v=59) then cnt_60s_v:=0; sc_c<='1'; else cnt_60s_v:=cnt_60s_v+1; sc_c<='0'; end if; end if; cnt_60s<=cnt_60s_v; --将计数的中间变量传给

秒的输出端

end process;

process(sc_c,add_min) --此进程是进行60分计时 variable cnt_60m_v:integer range 0 to 59 ; --存放分计时的中间变量，最后传到分输出端cnt_60m begin

if(pause='0') then

selector_min<=sc_c; --当计时/ 调整信号为0时正常计时,否则按键调整时间 else

selector_min<=add_min; end if;

if(selector_min 'event and selector_min='1') then if(cnt_60m_v=59) then cnt_60m_v:=0;

min_c<='1'; --分的进位信号 else

cnt_60m_v:=cnt_60m_v+1; min_c<='0'; end if; end if;

cnt_60m<=cnt_60m_v; --将计数的中间变量传给分输出端 end process;

process(min_c,selector_hour) --此进程是进行12小时计时 variable cnt_12h_v:integer range 0 to 11; --存放时的中间变量，最后传到分输出端cnt_60h begin

if(pause='0') then

selector_hour<=min_c; else

selector_hour<=add_hour; end if;

if(selector_hour 'event and selector_hour='1') then if(cnt_12h_v=11) then cnt_12h_v:=0; else

cnt_12h_v:=cnt_12h_v+1; end if; end if;

cnt_12h<=cnt_12h_v; end process;

end architecture one;

（3）、设置闹铃时间模块

library ieee; --设置闹铃时间，定时闹铃 use ieee.std_logic_1164.all;

entity setalarmtime is

port(set_alarm,set_sc,set_min,set_hour:in std_logic; sc_data,min_data: out integer range 0 to 59; hour_data:out integer range 0 to 11); end entity ;

architecture one of setalarmtime is begin

process(set_sc)

variable set_sc_data:integer range 0 to 59; --定义局部变量 begin

if(set_alarm='1') then

if(set_sc 'event and set_sc='1') then if(set_sc_data=59)then set_sc_data:=0; else

set_sc_data:=set_sc_data+1; --设置秒 end if; end if; end if;

sc_data<=set_sc_data; --秒设置好赋值给输出端 end process;

process(set_min)

variable set_min_data:integer range 0 to 59; begin

if(set_alarm='1') then

if(set_min 'event and set_min='1') then if(set_min_data=59)then set_min_data:=0; else

set_min_data:=set_min_data+1; --设置分 end if;

end if; end if;

min_data<=set_min_data; --分设置好赋值给输出端 end process;

process(set_hour)

variable set_hour_data:integer range 0 to 11; begin

if(set_alarm='1') then

if(set_hour 'event and set_hour='1') then if(set_hour_data=11)then set_hour_data:=0; else

set_hour_data:=set_hour_data+1; --设置时 end if; end if; end if;

hour_data<=set_hour_data; --时设置好赋值给输出端 end process; end architecture one;

(4)、闹铃模块

library ieee;--闹铃模块，时间相等则开始闹铃 use ieee.std_logic_1164.all;

entity alarm is

port(sc,min:in integer range 0 to 59;

hour:in integer range 0 to 11; --正常计时的时分秒 set_sc,set_min:in integer range 0 to 59;

set_hour:in integer range 0 to 11; --设置闹铃时间的时分秒 clear_alarm:in std_logic; --停止闹铃信号 flag_1s:in std_logic; --1hz信号

alarm_start:out bit; --开始闹铃信号 alarm_end:out bit; --结束闹铃信号 flag_alarm:out bit); --闹铃标志信号 end entity;

architecture one of alarm is

signal flag_alarm_start:bit; --定义开始闹铃信号

signal flag_alarm_end:bit; --定义结束闹铃信号 begin

process(sc,min,hour) begin

if(flag_1s 'event and flag_1s='1') then

if(sc=set_sc and min=set_min hour=set_hour) then

flag_alarm_start<=not flag_alarm_start; --如果正常计时的时间和

设置的闹铃时间相等时开始闹铃

else

flag_alarm_start<='0'; --如果时间不相等则不闹铃 end if; end if;

alarm_start<=flag_alarm_start; 将信号赋值给输出端 end process;

process(clear_alarm) begin if(clear_alarm 'event and clear_alarm='1') then flag_alarm_end<=not flag_alarm_end; --如果停止闹铃

信号到来则停止闹铃

end if;

alarm_end<=flag_alarm_end; end process;

process(flag_alarm_start,flag_alarm_end) begin

flag_alarm<=flag_alarm_start xor flag_alarm_end; end process; end architecture one;

（5）、二选一模块

library ieee; --选择正常计时时间或者设置闹铃时间 use ieee.std_logic_1164.all;

entity two_sel_one is

port(selector:in std_logic;--选择信号

sc,min:in integer range 0 to 59;

hour: in integer range 0 to 11;--正常计时时间输入端 set_sc,set_min:in integer range 0 to 59;

set_hour:in integer range 0 to 11; --设置闹铃时间的输入端 sc_out,min_out: out integer range 0 to 59;

hour_out:out integer range 0 to 11);--二选一选择后输出 end entity ;

architecture one of two_sel_one is begin

process(sc,min,hour,set_sc,set_min,set_hour) begin

if(selector='0') then sc_out<=sc; min_out<=min;

hour_out<=hour;--如果选择信号为0时，输出的是正常计时时间 else

sc_out<=set_sc; min_out<=set_min;

hour_out<=set_hour; --如果选择信号为1时，输出的是设置的闹铃

时间

end if; end process; end architecture one;

（6）、显示模块

library ieee; --此程序是将时分秒的十位和个位数分开并且转换成段码，还有

位选

use ieee.std_logic_1164.all;

entity display is

port(sc_data:in integer range 0 to 59; min_data:in integer range 0 to 59; hour_data:in integer range 0 to 11;

flag_1khz:in std_logic; --1khz的位选信号 Q:out std_logic_vector(7 downto 0); --接数码管的段码引脚 S:out std_logic_vector(7 downto 0)); --接数码管的位选引脚 end entity display;

architecture one of display is

signal sc_l,sc_h,min_l,min_h,hour_l,hour_h:integer range 0 to 9;

signal sc_l_q,sc_h_q,min_l_q,min_h_q,hour_l_q,hour_h_q: std_logic_vector(7

downto 0);

begin

process(sc_data,min_data,hour_data) --将时分秒的十位和各位分开 begin

sc_l<=sc_data mod 10; sc_h<=integer(sc_data/10); min_l<=min_data mod 10; min_h<=integer(min_data/10); hour_l<=hour_data mod 10; hour_h<=integer(hour_data/10); end process;

process(sc_l,sc_h,min_l,min_h,hour_l,hour_h) 转换成数码管显示的段码

begin

case(sc_l)is --秒各位 when 0 => sc_l_q<=\ when 1 => sc_l_q<=\ when 2 => sc_l_q<=\ when 3 => sc_l_q<=\ when 4 => sc_l_q<=\ when 5 => sc_l_q<=\ when 6 => sc_l_q<=\ when 7 => sc_l_q<=\ when 8 => sc_l_q<=\ when 9 => sc_l_q<=\ when others=>null; end case;

case(sc_h)is --秒十位 when 0 => sc_h_q<=\ when 1 => sc_h_q<=\ when 2 => sc_h_q<=\ when 3 => sc_h_q<=\ when 4 => sc_h_q<=\ when 5 => sc_h_q<=\

when others=>null; end case;

--将时分秒的个位和十位

case(min_l)is --分个位 when 0 => min_l_q<=\ when 1 => min_l_q<=\ when 2 => min_l_q<=\ when 3 => min_l_q<=\ when 4 => min_l_q<=\ when 5 => min_l_q<=\ when 6 => min_l_q<=\ when 7 => min_l_q<=\ when 8 => min_l_q<=\ when 9 => min_l_q<=\ when others=>null; end case;

case(min_h)is --分十位 when 0 => min_h_q<=\ when 1 => min_h_q<=\ when 2 => min_h_q<=\ when 3 => min_h_q<=\ when 4 => min_h_q<=\ when 5 => min_h_q<=\

when others=>null; end case;

case(hour_l)is --时个位 when 0 => hour_l_q<=\ when 1 => hour_l_q<=\ when 2 => hour_l_q<=\ when 3 => hour_l_q<=\ when 4 => hour_l_q<=\ when 5 => hour_l_q<=\ when 6 => hour_l_q<=\ when 7 => hour_l_q<=\ when 8 => hour_l_q<=\ when 9 => hour_l_q<=\ when others=>null; end case;

case(hour_h)is --时十位 when 0 => hour_h_q<=\ when 1 => hour_h_q<=\ when others=>null;

end case; end process;

process(flag_1khz) --此进程是实现数码管动态显示 variable counter_10:integer range 0 to 10; begin

if(flag_1khz 'event and flag_1khz='1') then if(counter_10=7) then counter_10:=0; else

counter_10:=counter_10+1; end if; end if;

case (counter_10)is when 0 => S<=\ when 1 => S<=\ when 2 => S<=\

--显示'-'

when 3 => S<=\ when 4 => S<=\ when 5 => S<=\

--显示'-'

when 6 => S<=\ when 7 => S<=\ when others=>null; end case; end process; end architecture one;

4、 硬件仿真如下：

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