AD9226-LQFP-EB中文资料

a

FEATURES

Signal-to-Noise Ratio: 69 dB @ fIN = 31 MHz

Spurious-Free Dynamic Range: 85 dB @ fIN = 31 MHzIntermodulation Distortion of –75 dBFS @ fIN = 140 MHzENOB = 11.1 @ fIN = 10 MHz

Low-Power Dissipation: 475 mWNo Missing Codes Guaranteed

Differential Nonlinearity Error: 0.6 LSBIntegral Nonlinearity Error: 0.6 LSBClock Duty Cycle Stabilizer

Patented On-Chip Sample-and-Hold with Full Power Bandwidth of 750 MHz

Straight Binary or Two’s Complement Output Data28-Lead SSOP, 48-Lead LQFP

Single 5 V Analog Supply, 3 V/5 V Driver SupplyPin-Compatible to AD9220, AD9221, AD9223,AD9224, AD9225

PRODUCT DESCRIPTION

The AD9226 is a monolithic, single-supply, 12-bit, 65 MSPSanalog-to-digital converter with an on-chip, high-performancesample-and-hold amplifier and voltage reference. The AD9226uses a multistage differential pipelined architecture with a pat-ented input stage and output error correction logic to provide12-bit accuracy at 65 MSPS data rates. There are no missingcodes over the full operating temperature range (guaranteed).The input of the AD9226 allows for easy interfacing to bothimaging and communications systems. With a truly differentialinput structure, the user can select a variety of input ranges andoffsets including single-ended applications.

The sample-and-hold amplifier (SHA) is well suited for IFundersampling schemes such as in single-channel communi-cation applications with input frequencies up to and wellbeyond Nyquist frequencies.

The AD9226 has an on-board programmable reference. For sys-tem design flexibility, an external reference can also be chosen.A single clock input is used to control all internal conversioncycles. An out-of-range signal indicates an overflow conditionthat can be used with the most significant bit to determine lowor high overflow.

REV.0

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

Complete 12-Bit, 65 MSPS

ADC Converter

AD9226

FUNCTIONAL BLOCK DIAGRAM

OTRBIT 1(MSB)BIT 12(LSB)

MODE

AVSS

DRVSS

The AD9226 has two important mode functions. One will setthe data format to binary or two’s complement. The second willmake the ADC immune to clock duty cycle variations.

PRODUCT HIGHLIGHTS

IF Sampling—The patented SHA input can be configured foreither single-ended or differential inputs. It will maintain out-standing AC performance up to input frequencies of 300 MHz.Low Power—The AD9226 at 475 mW consumes a fraction ofthe power presently available in existing, high-speed monolithicsolutions.

Out of Range (OTR)—The OTR output bit indicates whenthe input signal is beyond the AD9226’s input range.

Single Supply—The AD9226 uses a single 5 V power supplysimplifying system power supply design. It also features a sepa-rate digital output driver supply line to accommodate 3V and5V logic families.

Pin Compatibility—The AD9226 is similar to the AD9220,AD9221, AD9223, AD9224, and AD9225 ADCs.

Clock Duty Cycle Stabilizer—Makes conversion immune tovarying clock pulsewidths.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700World Wide Web Site: Fax: 781/326-8703© Analog Devices, Inc., 2000

AD9226–SPECIFICATIONS

DC SPECIFICATIONS

Parameter

RESOLUTION

ACCURACY

Integral Nonlinearity (INL)Differential Nonlinearity (DNL)No Missing Codes GuaranteedZero ErrorGain Error

TEMPERATURE DRIFTZero ErrorGain Error1Gain Error2POWER SUPPLY REJECTIONAVDD (5 V ± 0.25 V)INPUT REFERRED NOISEVREF = 1.0 VVREF = 2.0 VANALOG INPUT

Input Span (VREF = 1 V)

(VREF = 2 V)

Input (VINA or VINB) RangeInput Capacitance

INTERNAL VOLTAGE REFERENCEOutput Voltage (1 V Mode)

Output Voltage Tolerance (1 V Mode)Output Voltage (2.0 V Mode)

Output Voltage Tolerance (2.0 V Mode)

Output Current (Available for External Loads)Load Regulation3REFERENCE INPUT RESISTANCEPOWER SUPPLIESSupply VoltagesAVDDDRVDDSupply CurrentIAVDD4

IDRVDD

5

(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, Differential inputs, TMIN to TMAX unless otherwisenoted.)

Temp

Test Level

Min12

Full25°CFull25°CFullFull25°C25°CFullFullFullFullFull25°CFullFullFullFullFullFullFull25°CFull25°CFullFull25°CFull

VIVIIVIIVVVVVIVVVVIVVVIVIVVIV

±0.6

±1.6

±0.6

±1.0

12

±0.3

±1.4±2.0

±0.6±2±26±0.4±0.05

±0.4

0.50.2512

71.0

±15

2.0

±29

1.00.7

1.5

5

AVDD

Typ

Max

UnitBitsLSBLSBLSBLSBBits% FSR% FSR% FSR% FSRppm/°Cppm/°Cppm/°C% FSR% FSRLSB rmsLSB rmsV p-pV p-pVpFVmVVmVmAmVmVk

FullFullFull25°CFull25°CFull25°C

VVVIVIVI

4.752.85

5

5.255.25V (±5% AVDD Operating)V (±5% DRVDD Operating)mA (2 V External VREF)mA (2 V External VREF)mA (2 V External VREF)mA (2 V External VREF)mW (2 V External VREF)

86

90.5

14.6

16.5

475

500

POWER CONSUMPTION4, 5

NOTES1

Includes internal voltage reference error.2

Excludes internal voltage reference error.3

Load regulation with 1 mA load current (in addition to that required by the AD9226).4

AVDD = 5 V5

DRVDD = 3 V

Specifications subject to change without notice.

–2–REV. 0

AD9226

DIGITAL SPECIFICATIONS

(AVDD = 5 V, DRVDD = 3 V, f

SAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, unless otherwise noted.)

NOTES1

The clock period may be extended to 10 µs without degradation in specified performance @ 25°C.2

When MODE pin is tied to AVDD or grounded, the AD9226 SSOP is not affected by clock duty cycle.3

LQFP package.

Specifications subject to change without notice.

ANALOGINPUT

CLOCK

DATAOUT

3.5 MIN

Figure 1.Timing Diagram

REV. 0–3–

AD9226–SPECIFICATIONS

AC SPECIFICATIONS

Parameter

SIGNAL-TO-NOISE RATIOfIN = 2.5 MHzfIN = 15 MHzfIN = 31 MHzfIN = 60 MHzfIN = 200 MHz1

SIGNAL-TO-NOISE RATIO AND DISTORTIONfIN = 2.5 MHzfIN = 15 MHzfIN = 31 MHzfIN = 60 MHzfIN = 200 MHz1

TOTAL HARMONIC DISTORTIONfIN = 2.5 MHzfIN = 15 MHzfIN = 31 MHzfIN = 60 MHzfIN = 200 MHz1

SECOND AND THIRD HARMONIC DISTORTIONfIN = 2.5 MHzfIN = 15 MHzfIN = 31 MHzfIN = 60 MHzfIN = 200 MHz1

SPURIOUS FREE DYNAMIC RANGEfIN = 2.5 MHzfIN = 15 MHzfIN = 31 MHzfIN = 60 MHzfIN = 200 MHz1

ANALOG INPUT BANDWIDTH

NOTES1

1.0 V Reference and Input Span

Specifications subject to change without notice.

(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, Differential Input unless otherwise noted.)

TempFull

25°C

Test LevelVIVIVVVVIVIVVVVIVIVVVVIVIVVVVIVIVVVV

MinTyp68.9

MaxUnitdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcdBcMHz

68

68.4

67.4

68686568.8

67.9

68.3

67.3

676760–84

–77.0

–82.3

–76.0

–68–68–61–86.5

–78

–86.7

–76

–83–82–7586.4

78

85.5

76

828160750

Full

25°C

FullFullFullFull

25°C

Full

25°C

FullFullFullFull

25°C

Full

25°C

FullFullFullFull

25°C

Full

25°C

FullFullFullFull

25°C

Full

25°C

FullFullFull25°C

–4–REV. 0

AD9226

EXPLANATION OF TEST LEVELSTest Level

ABSOLUTE MAXIMUM RATINGS1

I.100% production tested.

Pin Name

With

Respect to

Min–0.3–0.3–0.3–6.5–0.3–0.3–0.3–0.3–0.3–0.3–0.3–0.3–0.3–0.3–65

Max

+6.5+6.5+0.3+6.5+0.3

AVDD + 0.3DRVDD + 0.3AVDD + 0.3AVDD + 0.3AVDD + 0.3AVDD + 0.3DRVDD + 0.3AVDD + 0.3AVDD + 0.3150+150300

UnitVVVVVVVVVVVVVV°C°C°C

II.100% production tested at 25°C and sample tested at

specified temperatures. AC testing done on sample basis.III.Sample tested only.

IV.Parameter is guaranteed by design and characterization

testing.V.Parameter is a typical value only.

VI.All devices are 100% production tested at 25°C; sample tested

at temperature extremes.

AVDDAVSSDRVDDDRVSSAVSSDRVSSAVDDDRVDDREFCOMAVSSCLK, MODEAVSSDigital OutputsDRVSSVINA, VINBAVSSVREFAVSSSENSEAVSSCAPB, CAPTAVSS

2

OEBDRVSS

2

CM LEVELAVSS2

AVSSVR

Storage Temperature

Lead Temperature (10 sec)

NOTES1

Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those indicated in the operationalsections of this specification is not implied. Exposure to absolute maximum ratingsfor extended periods may affect device reliability.2

LQFP package.

THERMAL RESISTANCE

θJC SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23°C/WθJA SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63.3°C/WθJC LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17°C/WθJA LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76.2°C/W

ORDERING GUIDE

Model

AD9226ARSAD9226ASTAD9226-EB

AD9226-LQFP-EB

Temperature Range–40°C to +85°C–40°C to +85°C

Package Description

28-Lead Shrink Small Outline (SSOP)

48-Lead Thin Plastic Quad Flatpack (LQFP)Evaluation Board (SSOP)Evaluation Board (LQFP)

Package OptionRS-28ST-48

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe AD9226 features proprietary ESD protection circuitry, permanent damage may occur ondevices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions arerecommended to avoid performance degradation or loss of functionality.

REV. 0–5–

AD9226

PIN CONNECTION48-Lead LQFP

MODE1CAPTCAPTCAPBCAPBREF COM (AVSS)

PIN CONNECTION28-Lead SSOP

VREF

VINBVINACM LEVELNC

VR

AVSSAVSSAVDDAVDD

SENSE

NCNCCLKNCOEBNCNC(LSB) BIT 12MODE2AVDDAVSSAVSS

AVDDDRVSSDRVDDOTR

BIT 1 (MSB)

BIT 2BIT 3

BIT 11

DRVSSDRVDDBIT 10BIT 9

DRVDDBIT 4

DRVSS

BIT 8BIT 7BIT 6BIT 5

48-PIN FUNCTION DESCRIPTIONS

28-PIN FUNCTION DESCRIPTIONS

Pin

Number1, 2, 32, 333, 4, 31, 345, 6, 8, 10,11, 44791213

14, 22, 3015, 23, 2916–21,24–2627283536373839, 4041, 424345464748

NameAVSSAVDDNCCLKOEBBIT 12BIT 11DRVSSDRVDDBITS 10–5,BITS 4–2BIT 1OTRMODE2SENSEVREFREFCOM(AVSS)CAPBCAPTMODE1CM LEVELVINAVINBVR

DescriptionAnalog Ground5 V Analog SupplyNo Connect

Clock Input Pin

Output Enable (Active Low)Least Significant Data Bit (LSB)Data Output Bit

Digital Output Driver Ground3 V to 5 V Digital OutputDriver SupplyData Output Bits

Most Significant Data Bit (MSB)Out of Range

Data Format SelectReference SelectReference In/OutReference CommonNoise Reduction PinNoise Reduction PinClock Stabilizer

Midsupply ReferenceAnalog Input Pin (+)Analog Input Pin (–)Noise Reduction Pin

Pin

Number123–12131415, 2616, 2517181920212223242728

NameCLKBIT 12BITS 11–2BIT 1OTRAVDDAVSSSENSEVREFREFCOM(AVSS)CAPBCAPTMODEVINAVINBDRVSSDRVDD

Description

Clock Input Pin

Least Significant Data Bit (LSB)Data Output Bits

Most Significant Data Bit (MSB)Out of Range

5 V Analog SupplyAnalog GroundReference Select

Input Span Select (Reference I/O)Reference Common

Noise Reduction PinNoise Reduction Pin

Data Format Select/Clock StabilizerAnalog Input Pin (+)Analog Input Pin (–)

Digital Output Driver Ground3 V to 5 V Digital OutputDriver Supply

–6–REV. 0

AD9226

DEFINITIONS OF SPECIFICATIONSINTEGRAL NONLINEARITY (INL)

EFFECTIVE NUMBER OF BITS (ENOB)

INL refers to the deviation of each inpidual code from a linedrawn from “negative full scale” through “positive full scale.”The point used as “negative full scale” occurs 1/2 LSB beforethe first code transition. “Positive full scale” is defined as a level1 1/2 LSB beyond the last code transition. The deviation ismeasured from the middle of each particular code to the truestraight line.

DIFFERENTIAL NONLINEARITY (DNL, NO MISSINGCODES)

For a sine wave, SINAD can be expressed in terms of the num-ber of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

it is possible to obtain a measure of performance expressed asN, the effective number of bits.

Thus, effective number of bits for a device for sine wave inputsat a given input frequency can be calculated directly from itsmeasured SINAD.

TOTAL HARMONIC DISTORTION (THD)

An ideal ADC exhibits code transitions that are exactly 1 LSBapart. DNL is the deviation from this ideal value. Guaranteedno missing codes to 12-bit resolution indicates that all 4096codes, respectively, must be present over all operating ranges.

ZERO ERROR

THD is the ratio of the rms sum of the first six harmonic com-ponents to the rms value of the measured input signal and isexpressed as a percentage or in decibels.

SIGNAL-TO-NOISE RATIO (SNR)

The major carry transition should occur for an analog value1/2 LSB below VINA = VINB. Zero error is defined as thedeviation of the actual transition from that point.

GAIN ERROR

SNR is the ratio of the rms value of the measured input signal tothe rms sum of all other spectral components below the Nyquistfrequency, excluding the first six harmonics and dc. The valuefor SNR is expressed in decibels.

SPURIOUS FREE DYNAMIC RANGE (SFDR)

The first code transition should occur at an analog value1/2 LSB above negative full scale. The last transition shouldoccur at an analog value 1 1/2 LSB below the positive full scale.Gain error is the deviation of the actual difference between firstand last code transitions and the ideal difference between firstand last code transitions.

TEMPERATURE DRIFT

SFDR is the difference in dB between the rms amplitude of theinput signal and the peak spurious signal.

ENCODE PULSEWIDTH DUTY CYCLE

The temperature drift for zero error and gain error specifies themaximum change from the initial (25°C) value to the value atTMIN or TMAX.

POWER SUPPLY REJECTION

Pulsewidth high is the minimum amount of time that the clockpulse should be left in the logic “1” state to achieve rated per-formance; pulsewidth low is the minimum time the clock pulseshould be left in the low state. At a given clock rate, these specsdefine an acceptable clock duty cycle.

MINIMUM CONVERSION RATE

The specification shows the maximum change in full scale fromthe value with the supply at the minimum limit to the value withthe supply at its maximum limit.

APERTURE JITTER

The clock rate at which the SNR of the lowest analog signalfrequency drops by no more than 3 dB below the guaranteed limit.

MAXIMUM CONVERSION RATE

The encode rate at which parametric testing is performed.

OUTPUT PROPAGATION DELAY

Aperture jitter is the variation in aperture delay for successivesamples and can be manifested as noise on the input to the ADC.

APERTURE DELAY

The delay between the clock logic threshold and the time whenall bits are within valid logic levels.

TWO TONE SFDR

Aperture delay is a measure of the sample-and-hold amplifier(SHA) performance and is measured from the rising edge of theclock input to when the input signal is held for conversion.

SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)RATIO

The ratio of the rms value of either input tone to the rms valueof the peak spurious component. The peak spurious componentmay or may not be an IMD product. May be reported in dBc(i.e., degrades as signal levels are lowered) or in dBFS (alwaysrelated back to converter full scale).

S/N+D is the ratio of the rms value of the measured inputsignal to the rms sum of all other spectral components belowthe Nyquist frequency, including harmonics but excluding dc.The value for S/N+D is expressed in decibels.

REV. 0–7–

d.AINe.CAPT, CAPB, MODE, SENSE, VREF

Equivalent Circuits

–8–

REV. 0

AD9226

Figure 2.

Typical Performance Characteristics–AD9226

(AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK Stabilizer Enabled, TA = 25 C, 2 V Differential Input Span, VCM = 2.5 V, AIN = –0.5 dBFS,VREF = 2.0V, unless otherwise noted.)

0–10–20

–30–40

S

–50FBd–60–70–80–90–100–110–120

FREQUENCY – MHz

TPC 1.Single-Tone 8K FFT with fIN = 5 MHz––––S

–FBd–––––––0

FREQUENCY – MHz

TPC 2.Dual-Tone 8K FFT with fIN–1 = 18 MHz andfIN–2 = 20 MHz (AIN–1 = AIN–2 = –6.5 dBFS)

––––S

–FBd–––––––0

6.5

13

19.5

26

32.5

FREQUENCY – MHz

TPC 3.Single-Tone 8K FFT with fIN = 31 MHzREV. 0c

Bd DNA SFBd–30

–15–10AIN – dBFS

TPC 4.Single-Tone SNR/SFDR vs. AIN with fIN

= 5 MHz

TPC 5.Dual-Tone SNR/SFDR vs. AIN with fIN–1 = 18MHzand fIN–2 = 20 MHz

TPC 6.Single-Tone SNR/SFDR vs. AIN with fIN = 31 MHz

–9–

AD9226

75

70

ENOB – Bits

SNR – dBc

65

SINAD – dBc

60

9.8

55

8.9

50

8.1

7.31

10

1001000FREQUENCY – MHz

TPC 7.

SINAD/ENOB vs. Frequency––––

c

Bd– – DH–T––––1

10

1001000

FREQUENCY – MHz

TPC 8.THD vs. Frequency72

70

c

B68d – RNS66

6462

1

10

1000

FREQUENCY – MHz

TPC 9.SNR vs. Temperature and Frequency1

101001000

FREQUENCY – MHz

TPC 10.

SNR vs. Frequency

9080

c

Bd – RDFS60501

10

1001000

FREQUENCY – MHz

TPC 11.SFDR vs. Frequency

–70–72–74–76

c

B–78

d – D–80HT

–82–84

–86–88

–90

1

10

100

FREQUENCY – MHz

TPC 12.THD vs. Temperature and Frequency

–10–REV. 0

105

95

Bc

d –85

CSINOMR75

AH65

55

1

10

1000

FREQUENCY – MHz

TPC 13.Harmonics vs. Frequency

95

c

Bd – R90

DFS85

80

SAMPLE RATE – MSPS

TPC 14.SFDR vs. Sample Rate

TPC 15.Typical INL

REV. 0AD9226

TPC 16.SINAD vs. Sample Rate

90

85

80

B

c

75

d

–

R

D

70

F

/

S

D

65

A

N

IS60

55

50

45

% POSITIVE DUTY CYCLE

TPC 17.

SINAD/SFDR vs. Duty Cycle @ f

IN

= 20 MHz

10.8

0.60.4

B

S0.2L – L0ND–0.2–0.4–0.6–0.8

–1

05001k1500

2k25003k35004k

CODE

TPC 18.Typical DNL

–11–

AD9226–Typical IF Sampling Performance Characteristics

(AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK Stabilizer Enabled, TA = 25 C, 2 V Differential Input Span, VCM = 2.5 V, AIN = –6.5dBFS,VREF = 2.0V, unless otherwise noted.)

––––S

–FBd–––––––FREQUENCY – MHz

TPC 19.Dual-Tone 8K FFT with fIN–1 = 44.2 MHz andfIN–2 = 45.6 MHz––––S

–FBd–––––––FREQUENCY – MHz

TPC 20. Dual-Tone 8K FFT with fIN–1 = 69.2 MHz andfIN–2 = 70.6 MHz––––S

–FBd–––––––FREQUENCY – MHz

TPC 21.Dual-Tone 8K FFT with fIN–1 = 139.2 MHz andfIN–2 = 140.7 MHzz

H/S

FSFBBdd –– RDRFSOOL/RF NESSINOAIN – dBFS

TPC 22.Dual-Tone SNR and SFDR with fIN–1 = 44.2 MHzand fIN–2 = 45.6 MHz

9085z

H/S

F80

SFBd Bd –– R75

RDFSOOL/RF NES70

SINO65

60AIN – dBFS

TPC 23.Dual-Tone SNR and SFDR with fIN–1 = 69.2 MHzand fIN–2 = 70.6 MHz

z

H/S

SFFBBdd –– RRDFSOOL/RF NESSINOAIN – dBFS

TPC 24.Dual-Tone SNR and SFDR with fIN–1 = 139.2 MHzand fIN–2 = 140.7 MHz

–12–REV. 0

––––S

–FBd–––––––FREQUENCY – MHz

TPC 25.Single-Tone 8K FFT at IF = 190 MHz–WCDMA(fIN = 190.82 MHz, fSAMPLE = 61.44 MSPS)––––S

–FBd–––––––0

12

16

24

28

FREQUENCY –

MHz

TPC 26.Dual-Tone 8K FFT with fIN–1 = 239.1 MHz andfIN–2

= 240.7 MHz–35

–45

–55

c

Bd – R–65RMC–75

–85–FREQUENCY – MHz

TPC 27.CMRR vs. Frequency (AIN = –0 dBFS andCML = 2.5 V)

REV. 0AD9226

zH/S

SFFBBdd –– RRDFSOOL/RF NESSINOAIN – dBFS

TPC 28.Single-Tone SNR and SFDR vs. AIN at IF = 190MHz–WCDMA (fIN–1 = 190.8 MHz, fSAMPLE = 61.44MSPS)

z

H/S

SFFBBdd –– RRDOFSOL/RF NESSIONAIN – dBFS

TPC 29.Dual-Tone SNR and SFDR with fIN–1 = 239.1 MHzand fIN–2 = 240.7 MHz

–13–

AD9226

THEORY OF OPERATION

The AD9226 is a high-performance, single-supply 12-bit ADC.The analog input of the AD9226 is very flexible allowing for bothsingle-ended or differential inputs of varying amplitudes that canbe ac- or dc-coupled.

It utilizes a nine-stage pipeline architecture with a wideband,sample-and-hold amplifier (SHA) implemented on a cost-effective CMOS process. A patented structure is used in theSHA to greatly improve high frequency SFDR/distortion. Thisalso improves performance in IF undersampling applications.Each stage of the pipeline, excluding the last stage, consists of alow resolution flash ADC connected to a switched capacitorDAC and interstage residue amplifier (MDAC). The residueamplifier amplifies the difference between the reconstructed DACoutput and the flash input for the next stage in the pipeline. Onebit of redundancy is used in each of the stages to facilitate digitalcorrection of flash errors. The last stage simply consists of aflash ADC.

Factory calibration ensures high linearity and low distortion.

ANALOG INPUT OPERATION

and/or shunt capacitor can help limit the wideband noise at theADC’s input by forming a low-pass filter. The source imped-ance driving VINA and VINB should be matched. Failure toprovide matching will result in degradation of the AD9226’sSNR, THD, and SFDR.

Figure 3.Equivalent Input Circuit

Figure 3 shows the equivalent analog input of the AD9226 whichconsists of a 750 MHz differential SHA. The differential inputstructure of the SHA is highly flexible, allowing the device to beeasily configured for either a differential or single-ended input.The analog inputs, VINA and VINB, are interchangeable withthe exception that reversing the inputs to the VINA and VINBpins results in a data inversion (complementing the output word).The optimum noise and dc linearity performance for either

differential or single-ended inputs is achieved with the largest inputsignal voltage span (i.e., 2 V input span) and matched inputimpedance for VINA and VINB. Only a slight degradation indc linearity performance exists between the 2 V and 1 V inputspans.

High frequency inputs may find the 1 V span better suited toachieve superior SFDR performance. (See Typical Perfor-mance Characteristics.)

The ADC samples the analog input on the rising edge of the clockinput. During the clock low time (between the falling edge andrising edge of the clock), the input SHA is in the sample mode;during the clock high time it is in hold. System disturbances justprior to the rising edge of the clock and/or excessive clock jitteron the rising edge may cause the input SHA to acquire the wrongvalue and should be minimized.

When the ADC is driven by an op amp and a capacitive load isswitched onto the output of the op amp, the output will momen-tarily drop due to its effective output impedance. As the outputrecovers, ringing may occur. To remedy the situation, a seriesresistor can be inserted between the op amp and the SHAinput as shown in Figure 4. A shunt capacitance also acts likea charge reservoir, sinking or sourcing the additional chargerequired by the hold capacitor, CH, further reducing currenttransients seen at the op amp’s output.

The optimum size of this resistor is dependent on several factors,including the ADC sampling rate, the selected op amp, and theparticular application. In most applications, a 30 to 100 resistor is sufficient.

For noise-sensitive applications, the very high bandwidth of theAD9226 may be detrimental and the addition of a series resistor

Figure 4.Series Resistor Isolates Switched-CapacitorSHA Input from Op Amp; Matching Resistors ImproveSNR Performance

OVERVIEW OF INPUT AND REFERENCECONNECTIONS

The overall input span of the AD9226 is equal to the potentialat the VREF pin. The VREF potential may be obtained fromthe internal AD9226 reference or an external source (seeReference Operation section).

In differential applications, the center point of the span isobtained by the common-mode level of the signals. In single-ended applications, the center point is the dc potential appliedto one input pin while the signal is applied to the opposite inputpin. Figures 5a–5f show various system configurations.

DRIVING THE ANALOG INPUTS

The AD9226 has a very flexible input structure allowing it tointerface with single-ended or differential input interface circuitry.The optimum mode of operation, analog input range, and asso-ciated interface circuitry will be determined by the particularapplications performance requirements as well as power supplyoptions.

DIFFERENTIAL DRIVER CIRCUITS

Differential operation requires that VINA and VINB be simulta-neously driven with two equal signals that are 180 out of phasewith each other.

Differential modes of operation (ac- or dc-coupled input) providethe best THD and SFDR performance over a wide frequencyrange. They should be considered for the most demanding

spectral-based applications (e.g., direct IF conversion to digital).

REV. 0

–14–

Figure 5a.1 V Single-Ended Input, Common-ModeVoltage = 1V

Figure 5b.1V Differential Input, Common-Mode

Voltage = 1 V

Figure 5c.2 V Differential Input, Common-ModeVoltage = 2 V

Figure 5d.2 V Single-Ended Input, Common-ModeVoltage = 2 V

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AD9226

Figure 5e.2 V Differential Input, Common-ModeVoltage = 2.5 V

Figure 5f.1 V Differential Input, Common-Mode

Voltage = 2.5 V (Recommended for IF Undersampling)

The differential input characterization for this data sheet wasperformed using the configuration shown in Figure 7.

Since not all applications have a signal preconditioned fordifferential operation, there is often a need to perform a single-ended-to-differential conversion. In systems that do not need tobe dc-coupled, an RF transformer with a center tap is the bestmethod to generate differential inputs for the AD9226. It pro-vides all the benefits of operating the ADC in the differentialmode without contributing additional noise or distortion. An RFtransformer also has the added benefit of providing electricalisolation between the signal source and the ADC. An improvementin THD and SFDR performance can be realized by operatingthe AD9226 in the differential mode. The performance enhance-ment between the differential and single-ended mode is mostnoteworthy as the input frequency approaches and goes beyondthe Nyquist frequency (i.e., fIN > FS /2).

The circuit shown in Figure 6a is an ideal method of applyinga differential dc drive to the AD9226. It uses an AD8138 toderive a differential signal from a single-ended one. Figure 6billustrates its performance.

Figure 7 presents the schematic of the suggested transformercircuit. The circuit uses a Minicircuits RF transformer, modelT1-1T, which has an impedance ratio of four (turns ratio of 2).The schematic assumes that the signal source has a 50 sourceimpedance. The center tap of the transformer provides a con-venient means of level-shifting the input signal to a desiredcommon-mode voltage. In Figure 7 the transformer centertapis connected to a resistor pider at the midsupply voltage.–15–

AD9226

SINGLE-ENDED DRIVER CIRCUITS

F

F

F

The AD9226 can be configured for single-ended operation usingdc- or ac-coupling. In either case, the input of the ADC must bedriven from an operational amplifier that will not degrade theADC’s performance. Because the ADC operates from a singlesupply, it will be necessary to level-shift ground-based bipolarsignals to comply with its input requirements. Both dc- andac-coupling provide this necessary function, but each methodresults in different interface issues which may influence thesystem design and performance.

Single-ended operation requires that VINA be ac- or dc-coupledto the input signal source, while VINB of the AD9226 be biasedto the appropriate voltage corresponding to the middle of the inputspan. The single-ended specifications for the AD9226 are char-acterized using Figure 9a circuitry with input spans of 1 V and2V. The common-mode level is 2.5 V.

If the analog inputs exceed the supply limits, internal parasiticdiodes will turn on. This will result in transient currents withinthe device. Figure 8 shows a simple means of clamping an input.It uses a series resistor and two diodes. An optional capacitor isshown for ac-coupled applications. A larger series resistor canbe used to limit the fault current through D1 and D2. Thiscan cause a degradation in overall performance. A similarclamping circuit can also be used for each input if a differen-tial input signal is being applied. A better method to ensurethe input is not overdriven is to use amplifiers powered by a single5 V supply such as the AD8138.

Figure 6a.Direct-Coupled Drive Circuit with AD8138Differential Op Amp

––dBc

––––0

4

8

12

16MHz

20

24

28

32

Figure 6b.FS = 65 MSPS, fIN = 30 MHz, Input Span = 1 V p-p

The same midsupply potential may be obtained from theCMLEVEL pin of the AD9226 in the LQFP package.

Referring to Figure 7, a series resistor, RS, is inserted between theAD9226 and the secondary of the transformer. The value of33 ohm was selected to specifically optimize both the THD andSNR performance of the ADC. RS and the internal capacitancehelp provide a low-pass filter to block high-frequency noise.Transformers with other turns ratios may also be selected tooptimize the performance of a given application. For example, agiven input signal source or amplifier may realize an improve-ment in distortion performance at reduced output power levelsand signal swings. By selecting a transformer with a higherimpedance ratio (e.g., Minicircuits T16-6T with a 1:16 imped-ance ratio), the signal level is effectively “stepped up” thusfurther reducing the driving requirements of signal source.

Figure 8.Simple Clamping Circuit

AC-COUPLING AND INTERFACE ISSUES

For applications where ac-coupling is appropriate, the op ampoutput can be easily level-shifted by means of a couplingcapacitor. This has the advantage of allowing the op amp’s com-mon-mode level to be symmetrically biased to its midsupplylevel (i.e., (AVDD/2). Op amps that operate symmetrically withrespect to their power supplies typically provide the best acperformance as well as greatest input/output span. Various high-speed performance amplifiers that are restricted to +5 V/–5 Voperation and/or specified for 5 V single-supply operation can beeasily configured for the 2 V or 1 V input span of the AD9226.

Simple AC Interface

Figure 7.Transformer-Coupled Input

Figure 9a shows a typical example of an ac-coupled, single-ended configuration of the SSOP package. The bias voltageshifts the bipolar, ground-referenced input signal to approxi-mately AVDD/2. The capacitors, C1 and C2, are 0.1 µF ceramicand 10 µF tantalum capacitors in parallel to achieve a lowcutoff frequency while maintaining a low impedance over awide frequency range. The combination of the capacitor and theresistor form a high-pass network with a high-pass –3 dB fre-quency determined by the equation,

f–3 dB = 1/(2 × π × R × (C1 + C2))

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The low-impedance VREF output can be used to provide dcbias levels to the fixed VINB pin and the signal on VINA. Fig-ure 9b shows the VREF configured for 2.0 V, thus the inputrange of the ADC is 1.0 V to 3.0 V. Other input ranges couldbe selected by changing VREF.

When the inputs are biased from the reference (Figure 9b),there may be a slight degeneration of dynamic performance. Amidsupply output level is available at the CM LEVEL pin of theLQFP package.

Figure 10 illustrates the relation between common-mode voltageand THD. Note that optimal performance occurs when thereference voltage is set to 2.0 V (input span = 2.0 V).

DC-COUPLING AND INTERFACE ISSUES

Many applications require the analog input signal to be dc-coupledto the AD9226. An operational amplifier can be configured torescale and level-shift the input signal to make it compatiblewith the selected input range of the ADC.

The selected input range of the AD9226 should be consideredwith the headroom requirements of the particular op amp toprevent clipping of the signal. Many of the new high-performanceop amps are specified for only ±5 V operation and have limitedinput/output swing capabilities. Also, since the output of a dualsupply amplifier can swing below absolute minimum (–0.3 V),clamping its output should be considered in some applications(see Figure 8). When single-ended, dc-coupling is needed, theuse of the AD8138 in a differential configuration (Figure 9a) ishighly recommended.

Simple Op Amp Buffer

Figure 9a.AC-Coupled Input Configuration

In the simplest case, the input signal to the AD9226 will alreadybe biased at levels in accordance with the selected input range. Itis necessary to provide an adequately low source impedance forthe VINA and VINB analog pins of the ADC.

REFERENCE OPERATION

The AD9226 contains an on-board bandgap reference thatprovides a pin-strappable option to generate either a 1 V or2V output. With the addition of two external resistors, the usercan generate reference voltages between 1 V and 2 V. SeeFigures 5a-5f for a summary of the pin-strapping options for theAD9226 reference configurations. Another alternative is to usean external reference for designs requiring enhanced accuracyand/or drift performance described later in this section.Figure 11a shows a simplified model of the internal voltage refer-ence of the AD9226. A reference amplifier buffers a 1 V fixedreference. The output from the reference amplifier, A1, appearson the VREF pin. The voltage on the VREF pin determinesthe full-scale input span of the ADC. This input span equals,

Full-Scale Input Span = VREF

The voltage appearing at the VREF pin, and the state of theinternal reference amplifier, A1, are determined by the voltageappearing at the SENSE pin. The logic circuitry contains com-parators that monitor the voltage at the SENSE pin. If theSENSE pin is tied to AVSS, the switch is connected to theinternal resistor network thus providing a VREF of 2.0 V. If theSENSE pin is tied to the VREF pin via a short or resistor, theswitch will connect to the SENSE pin. This connection will pro-vide a VREF of 1.0 V. An external resistor network will providean alternative VREF between 1.0 V and 2.0 V (see Figure 12).Another comparator controls internal circuitry that will disablethe reference amplifier if the SENSE pin is tied to AVDD.Disabling the reference amplifier allows the VREF pin to bedriven by an external voltage reference.

Figure 9b.Alternate AC-Coupled Input Configuration

–84–83–82–81dBc

–80–79–78–77–76

0.5

1.0

1.5

2.0

2.5volts

3.0

3.5

4.0

4.5

5.0

Figure 10.THD vs. Common-Mode Voltage(2 V Differential Input Span, fIN = 10 MHz)

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AD9226

sets the input span to be 1.5 V p-p. The midscale voltage canalso be set to VREF by connecting VINB to VREF. Alterna-tively, the midscale voltage can be set to 2.5 V by connectingVINB to a low-impedance 2.5 V source as shown in Figure 12.

Figure 12.Resistor Programmable Reference (1.5 V p-pInput Span, Differential Input VCM = 2.5 V)USING AN EXTERNAL REFERENCE

Figure 11a.Equivalent Reference Circuit

Figure 11b.CAPT and CAPB DC-Coupling

The AD9226 contains an internal reference buffer, A2 (seeFigure 11b), that simplifies the drive requirements of an externalreference. The external reference must be able to drive about5k (±20%) load. Note that the bandwidth of the referencebuffer is deliberately left small to minimize the reference noisecontribution. As a result, it is not possible to rapidly change thereference voltage in this mode.

Figure 13 shows an example of an external reference drivingboth VINB and VREF. In this case, both the common-modevoltage and input span are directly dependent on the value ofVREF. Both the input span and the center of the input span areequal to the external VREF. Thus the valid input range extendsfrom (VREF + VREF/2) to (VREF – VREF/2). For example,if the REF191, a 2.048 V external reference, is selected, theinput span extends to 2.048 V. In this case, 1 LSB of the AD9226corresponds to 0.5mV. It is essential that a minimum of a 10 µFcapacitor, in parallel with a 0.1 µF low-inductance ceramiccapacitor, decouple the reference output to ground.

To use an external reference, the SENSE pin must be connectedto AVDD. This connection will disable the internal reference.

The actual reference voltages used by the internal circuitry of theAD9226 appear on the CAPT and CAPB pins. The voltageson these pins are symmetrical about the analog supply. Forproper operation when using an internal or external reference, itis necessary to add a capacitor network to decouple these pins.Figure 11b shows the recommended decoupling network. Theturn-on time of the reference voltage appearing between CAPTand CAPB is approximately 10 ms and should be evaluated inany power-down mode of operation.

USING THE INTERNAL REFERENCE

The AD9226 can be easily configured for either a 1 V p-p inputspan or 2 V p-p input span by setting the internal reference.Other input spans can be realized with two external gain-setting resistors as shown in Figure 12 of this data sheet, orusing an external reference.

Pin Programmable Reference

By shorting the VREF pin directly to the SENSE pin, the inter-nal reference amplifier is placed in a unity-gain mode and theresultant VREF output is 1 V. By shorting the SENSE pindirectly to the REFCOM pin, the internal reference amplifier isconfigured for a gain of 2.0 and the resultant VREF output is2.0 V. The VREF pin should be bypassed to the REFCOM pinwith a 10 µF tantalum capacitor in parallel with a low-inductance0.1 µF ceramic capacitor as shown in Figure 11b.

Resistor Programmable Reference

Figure ing an External Reference

MODE CONTROLSClock Stabilizer

Figure 12 shows an example of how to generate a reference

voltage other than 1.0 V or 2.0 V with the addition of two exter-nal resistors. Use the equation,

VREF = 1 V × (1 + R1/R2)

to determine appropriate values for R1 and R2. These resistorsshould be in the 2 k to 10 k range. For the example shown,R1 equals 2.5 k and R2 equals 5 k . From the equation above,the resultant reference voltage on the VREF pin is 1.5 V. This

The clock stabilizer is a circuit that desensitizes the ADC fromclock duty cycle variations. The AD9226 eases system clockconstraints by incorporating a circuit that restores the internal dutycycle to 50%, independent of the input duty cycle. Low jitter onthe rising edge (sampling edge) of the clock is preserved whilethe noncritical falling edge is generated on-chip.

It may be desirable to disable the clock stabilizer, and may benecessary when the clock frequency speed is varied or completely

–18–

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AD9226

stopped. Once the clock frequency is changed, over 100 clock

Table IV.Output Data Format

DIGITAL INPUTS AND OUTPUTSDigital Outputs

Table IV details the relationship among the ADC input, OTR, andstraight binary output.

Figure 15.Overrange or Underrange Logic

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