ADG1611_1612_1613

数字模拟开关

1 Ω Typical On Resistance, ±5 V, +12 V,+5 V, and +3.3 V Quad SPST Switches

FEATURES

1 Ω typical on resistance 0.2 Ω on resistance flatness

±3.3 V to ±8 V dual-supply operation 3.3 V to 16 V single-supply operation No VL supply required

3 V logic-compatible inputs Rail-to-rail operation

Continuous current per channel LFCSP package: 280 mA TSSOP package: 175 mA

16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP

APPLICATIONS

Communication systems Medical systems Audio signal routing Video signal routing

Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Relay replacements

GENERAL DESCRIPTION

The ADG1611/ADG1612/ADG1613 contain four independent single-pole/single-throw (SPST) switches. The ADG1611 and ADG1612 differ only in that the digital control logic is inverted. The ADG1611 switches are turned on with Logic 0 on the appropriate control input, while Logic 1 is required for the ADG1612 switches. The ADG1613 has two switches with digital control logic similar to that of the ADG1611; the logic is inverted on the other two switches. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked.

The ADG1613 exhibits break-before-make switching action for use in multiplexer applications. Inherent in the design is the low charge injection for minimum transients when switching the digital inputs. The ultralow on resistance of these switches make them ideal solutions for data acquisition and gain switching applications

where low on resistance and distortion is critical. The on resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. The CMOS construction ensures ultralow power dissipation, making them ideally suited for portable and battery-powered instruments.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADG1611/ADG1612/ADG1613

IN1

IN2

IN3

S4

IN4

1

0NOTES

0-181. SWITCHES SHOWN FOR A LOGIC 1 INPUT.

970Figure 1.

IN2

S3IN3

S4

IN4

330NOTES

-181. SWITCHES SHOWN FOR A LOGIC 1 INPUT.

970Figure 2.

S1

D1S2

IN2

D2S3IN3

D3S4

IN4

D4

4

30NOTES

-181. SWITCHES SHOWN FOR A LOGIC 1 INPUT.

970Figure 3.

PRODUCT HIGHLIGHTS

1. 1.6 Ω maximum on resistance over temperature. 2. Minimum distortion: THD + N = 0.007%.

3. 3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. 4. No VL logic power supply required. 5. Ultralow power dissipation: <16 nW.

6.

16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.

数字模拟开关

ADG1611/ADG1612/ADG1613

3.3 V Single Supply ........................................................................6 Continuous Current per Channel, S or D ..................................7 Absolute Maximum Ratings ............................................................8 ESD Caution...................................................................................8 Pin Configurations and Function Descriptions ............................9 Typical Performance Characteristics ........................................... 10 Test Circuits ..................................................................................... 13 Terminology .................................................................................... 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16 

TABLE OF CONTENTS

Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams ............................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 ±5 V Dual Supply ......................................................................... 3 12 V Single Supply ........................................................................ 4 5 V Single Supply .......................................................................... 5 

REVISION HISTORY

9/09—Rev. 0 to Rev. A

Changes to On Resistance (RON) Parameter, On Resistance Match Between Channels (ΔRON) Parameter, and On Resistance Flatness (RFLATON) Parameter, Table 4 ............................................................ 6 Changes to Figure 7 Caption ......................................................... 10

1/09—Revision 0: Initial Version

Rev. A | Page 2 of 16

数字模拟开关

ADG1611/ADG1612/ADG1613

SPECIFICATIONS

±5 V DUAL SUPPLY

VDD = +5 V ± 10%, VSS = 5 V ± 10%, GND = 0 V, unless otherwise noted. Table 1.

40°C to 40°C to

+85°C Test Conditions/Comments ANALOG SWITCH Analog Signal Range VDD to VSS On Resistance (RON) 1 VS = ±4.5 V, IS = 10 mA; see Figure 24 1.2 VDD = ±4.5 V, VSS = ±4.5 V On Resistance Match Between Channels ( RON0.04 VS = ±4.5 V, IS = 10 mA On Resistance Flatness (RFLAT(ON)) 0.2 VS = ±4.5 V, IS = 10 mA 0.25 LEAAGE CURRENTS VDD = +5.5 V, VSS = 5.5 V Source Off Leakage, IS (Off) ±0.1 nA typ VS = ±4.5 V, VD = 4.5 V; see Figure 25

Drain Off Leakage, ID (Off)

±0.3 ±0.1 nA typ VS = ±4.5 V, VD = 4.5 V; see Figure 25

K ±0.3

Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = ±4.5 V; see Figure 26 DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINHVIN = VGND or VDD Digital Input Capacitance, CIN 5 DYNAMIC CHARACTERISTICS1 tON 165 RL = 300 Ω, CL = 35 pF 212 VS = 2.5 V; see Figure 31 tOFF 105 RL = 300 Ω, CL = 35 pF 137 VS = 2.5 V; see Figure 31 Break-Before-Make Time Delay, tD 25 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 2.5 V; see Figure 32 Charge Injection 140 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33 Off Isolation 70 RL = 50 Ω, CL = 5 pF, f = 1 MHz;

see Figure 27

Channel-to-Channel Crosstalk 110 RL = 50 Ω, CL = 5 pF, f = 1 MHz;

see Figure 28

Total Harmonic Distortion + Noise (THD + N) 0.007 % typ RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz;

see Figure 30

3 dB Bandwidth 42 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29 CS (Off) 63 pF typ VS = 0 V, f = 1 MHz CD (Off) 63 pF typ VS = 0 V, f = 1 MHz CD, CS (On) 154 pF typ VS = 0 V, f = 1 MHz POWER REQUIREMENTS VDD = +5.5 V, VSS = 5.5 V IDD 0.001 μA typ Digital inputs = 0 V or VDD 1.0 μA max VDD/VSS

1

Guaranteed by design, not subject to production test.

Rev. A | Page 3 of 16

数字模拟开关

ADG1611/ADG1612/ADG1613

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2.

40°C to 40°C to

+85°C Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD On Resistance (RONVS = 0 V to 10 V, IS = 10 mA; see Figure 24 VDD = 10.8 V, VSS = 0 V On Resistance Match Between Channels ( RON Ω typ VS = 0 V to 10 V, IS = 10 mA On Resistance Flatness (RFLAT(ON) VS = 0 V to 10 V, IS = 10 mA LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V Source Off Leakage, IS (Off) ±0.1 nA typ VS = 1 V/10 V, VS = 10 V/1 V, see Figure 25 Drain Off Leakage, ID (Off) ±0.1 nA typ VS = 1 V/10 V, VS = 10 V/1 V see Figure 25 Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = 1 V or 10 V; see Figure 26 DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINHVIN = VGND or VDD Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS1

tONRL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 31 tOFFRL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 31 Break-Before-Make Time Delay, tD (ADG1613 Only) 35 ns typ RL = 300 Ω, CL = 35 pF VS1 = VS2 = 8 V; see Figure 32 Charge Injection 170 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 33 Off Isolation 70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 Channel-to-Channel Crosstalk 110 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 Total Harmonic Distortion + Noise 0.012 % typ RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz;

see Figure 30

3 dB Bandwidth 38 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29 CS (Off) 60 pF typ VS = 6 V, f = 1 MHz CD (Off) 60 pF typ VS = 6 V, f = 1 MHz CD, CS (On) 154 pF typ VS = 6 V, f = 1 MHz POWER REQUIREMENTS VDD = 12 V IDD 0.001 μA typ Digital inputs = 0 V or VDD 1 μA max IDD 320 μA typ Digital inputs = 5 V 480 μA max VDD

1

Guaranteed by design, not subject to production test.

Rev. A | Page 4 of 16

数字模拟开关

ADG1611/ADG1612/ADG1613

5 V SINGLE SUPPLY

VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3.

40°C to 40°C to

+85°C Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD On Resistance (RONVS = 0 V to 4.5 V, IS = 10 mA; see Figure 24 VDD = 4.5 V, VSS = 0 V On Resistance Match Between Channels ( RON Ω typ VS = 0 V to 4.5 V, IS = 10 mA On Resistance Flatness (RFLAT(ON) VS = 0 V to 4.5 V, IS = 10 mA LEAKAGE CURRENTS VDD = 5.5 V, VSS = 0 V Source Off Leakage, IS (Off) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 25 Drain Off Leakage, ID (Off) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 25 ±0.3 ±1 ±6 nA max Channel On Leakage, ID, IS (On) ±0.15 nA typ VS = VD = 1 V or 4.5 V; see Figure 26 DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINHVIN = VGND or VDD ±0.1 μA max Digital Input Capacitance, CIN 5 pF typ DYNAMIC CHARACTERISTICS1

tONRL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 31 tOFFRL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 31 Break-Before-Make Time Delay, tD (ADG1613 Only) 35 ns typ RL = 300 Ω, CL = 35 pF VS1 = VS2 = 2.5 V; see Figure 32 Charge Injection 80 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33 Off Isolation 70 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;

see Figure 27

Channel-to-Channel Crosstalk 110 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;

see Figure 28

Total Harmonic Distortion + Noise 0.093 % typ RL = 110 Ω, f = 20 Hz to 20 kHz,

VS = 3.5 V p-p; see Figure 30

3 dB Bandwidth 42 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29 CS (Off) 72 pF typ VS = 2.5 V, f = 1 MHz CD (Off) 72 pF typ VS = 2.5 V, f = 1 MHz CD, CS (On) 160 pF typ VS = 2.5 V, f = 1 MHz POWER REQUIREMENTS VDD = 5.5 V IDD 0.001 μA typ Digital inputs = 0 V or VDD 1 μA max VDD

1

Guaranteed by design, not subject to production test.

Rev. A | Page 5 of 16

数字模拟开关

ADG1611/ADG1612/ADG1613

3.3 V SINGLE SUPPLY

VDD = 3.3 V, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4.

40°C to 40°C to

+85°C Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to VDD On Resistance (RONVS = 0 V to VDD, IS = 10 mA, VDD = 3.3 V,

VSS = 0 V; see Figure 24

On Resistance Match Between Channels ( RON0.07 0.08 Ω typ VS = 0 V to VDD, IS = 10 mA On Resistance Flatness (RFLAT(ON)1.3 VS = 0 V to VDD, IS = 10 mA LEAKAGE CURRENTS VDD = 3.6 V, VSS = 0 V Source Off Leakage, IS (Off) ±0.02 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 25 ±0.3 ±1 ±6 nA max Drain Off Leakage, ID (Off) ±0.02 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 25 ±0.3 ±1 ±6 nA max Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = 0.6 V or 3 V; see Figure 26 ±0.4 ±1.5 ±10 nA max DIGITAL INPUTS Input High Voltage, VINH 2.0 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINHVIN = VGND or VDD ±0.1 μA max Digital Input Capacitance, CIN 3 pF typ DYNAMIC CHARACTERISTICS1 tON 350 ns typ RL = 300 Ω, CL = 35 pF VS = 1.5 V; see Figure 31 tOFF 190 ns typ RL = 300 Ω, CL = 35 pF VS = 1.5 V; see Figure 31 Break-Before-Make Time Delay, tD (ADG1613 Only) 25 ns typ RL = 300 Ω, CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 32 Charge Injection 50 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 33 Off Isolation 70 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;

see Figure 27

Channel-to-Channel Crosstalk 110 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;

see Figure 28

Total Harmonic Distortion + Noise 0.18 % typ RL = 110 Ω, f = 20 Hz to 20 kHz,

VS = 2 V p-p; see Figure 30

3 dB Bandwidth 52 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29 CS (Off) 76 pF typ VS = 1.5 V, f = 1 MHz CD (Off) 76 pF typ VS = 1.5 V, f = 1 MHz CD, CS (On) 160 pF typ VS = 1.5 V, f = 1 MHz POWER REQUIREMENTS VDD = 3.6 V IDD 0.001 μA typ Digital inputs = 0 V or VDD 1.0 1.0 μA max VDD

1

Guaranteed by design, not subject to production test.

Rev. A | Page 6 of 16

数字模拟开关

ADG1611/ADG1612/ADG1613

CONTINUOUS CURRENT PER CHANNEL, S OR D

Table 5.

Parameter

CONTINUOUS CURRENT, S OR D VDD = +5 V, VSS = 5 V

TSSOP (θJA = 150.4°C/W) LFCSP (θJA = 48.7°C/W) VDD = 12 V, VSS = 0 V

TSSOP (θJA = 150.4°C/W) LFCSP (θJA = 48.7°C/W) VDD = 5 V, VSS = 0 V

TSSOP (θJA = 150.4°C/W) LFCSP (θJA = 48.7°C/W) VDD = 3.3 V, VSS = 0 V

TSSOP (θJA = 150.4°C/W) LFCSP (θJA = 48.7°C/W)

175 119 70 280 175 95 206 135 84 336 203 108 140 91 63 220 140 84 140 98 70 228 150 91

Unit

mA maximum mA maximum

mA maximum mA maximum

mA maximum mA maximum

mA maximum mA maximum

Rev. A | Page 7 of 16

数字模拟开关

ADG1611/ADG1612/ADG1613

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Table 6.

VDD to VSSV VDD to GND 0.3 V to +18 V VSS to GND +0.3 V to 18 V Analog Inputs1 VSS 0.3 V to VDD + 0.3 V or

30 mA, whichever occurs first

1

Digital Inputs GND 0.3 V to VDD + 0.3 V or

30 mA, whichever occurs first

Peak Current, S or D 630 mA (pulsed at 1 ms,

10% duty-cycle maximum)

Continuous Current, S or D2 Data + 15% Operating Temperature Range Industrial (Y Version) 40°C to +125°C Storage Temperature Range 65°C to +150°C Junction Temperature 150°C

150.4°C/W 16-Lead TSSOP, θJA Thermal

Impedance (2-Layer Board)

48.7°C/W 16-Lead LFCSP, θJA Thermal

Impedance (4-Layer Board)

260°C Reflow Soldering Peak

Temperature, Pb free

Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. 2

See Table 5.

1

ESD CAUTION

Rev. A | Page 8 of 16

数字模拟开关

ADG1611/ADG1612/ADG1613

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

15IN116D1

14IN2

IN1D1

IN2D2S2VDDNCS3D3

07981-002

S1VSSGNDS413D2

S1VSSGNDS4D4

12S211VDD10NC9S3

IN4NC = NO CONNECT

IN3

IN37

IN46

D38

D45

Figure 4. 16-Lead TSSOP Pin Configuration

NOTES

1. NC = NO CONNECT.

2. EXPOSED PAD TIED TO SUBSTRATE, VSS.

Figure 5. 16-Lead LFCSP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

16-Lead TSSOP 16-Lead LFCSP 1 15 IN1 Logic Control Input. 2 16 D1 Drain Terminal. This pin can be an input or output. 3 1 S1 Source Terminal. This pin can be an input or output. VSS Most Negative Power Supply Potential. 5 3 GND Ground (0 V) Reference. 6 4 S4 Source Terminal. This pin can be an input or output. 7 5 D4 Drain Terminal. This pin can be an input or output. 8 6 IN4 Logic Control Input. 9 7 IN3 Logic Control Input. 10 8 D3 Drain Terminal. This pin can be an input or output. 11 9 S3 Source Terminal. This pin can be an input or output. No Connection. VDD Most Positive Power Supply Potential. 14 12 S2 Source Terminal. This pin can be an input or output. 15 13 D2 Drain Terminal. This pin can be an input or output. 16 14 IN2 Logic Control Input. N/A 17 (EPAD) EP (EPAD) Exposed Pad. Tied to substrate, VSS.

Table 8. ADG1611/ADG1612 Truth Table

ADG1611 INx 0 1

ADG1612 INx 1 0

Switch Condition On Off

Table 9. ADG1613 Truth Table

Logic (INx) 0 1

Switch 1, Switch 4 Off On

Switch 2, Switch 3 On Off

Rev. A | Page 9 of 16

07981-003

数字模拟开关

ADG1611/ADG1612/ADG1613

1.4

TYPICAL PERFORMANCE CHARACTERISTICS

1.4

1.21.2ON RESISTANCE ( )

ON RESISTANCE ( )

1.0

1.0

0.80.8

0.6

0.6

07981-013

–6–4–202468024681012

VS OR VD VOLTAGE (V)

Figure 6. On Resistance as a Function of VD (VS) for Dual Supply

3.5

Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures,

12 V Single Supply

2.5

VS OR VD VOLTAGE (V)

3.0

ON RESISTANCE ( )

ON RESISTANCE ( )

2.5

2.0

2.0

1.5

1.5

1.0

1.0

00.51.01.52.02.53.03.54.04.55.0

VS OR VD VOLTAGE (V)

VS OR VD VOLTAGE (V)

Figure 7. On Resistance as a Function of VD (VS) for Single Supply

1.4

Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures,

5 V Single Supply

4.0

1.2ON RESISTANCE ( )

ON RESISTANCE ( )

3.5

1.03.0

0.82.5

0.6

07981-011

–4–2024600.51.01.52.02.53.03.5

VS OR VD VOLTAGE (V)

VS OR VD VOLTAGE (V)

Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,

±5 V Dual Supply

Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures,

3.3 V Single Supply

Rev. A | Page 10 of 16

07981-006

0.4–6

2.0

1.5

07981-012

024681012

1416

07981-014

0.5

07981-010

0.4–8

0.4

数字模拟开关

20

15

1816

ADG1611/ADG1612/ADG1613

14

LEAKAGE CURRENT (nA)

LEAKAGE CURRENT (nA)

10

121086420–2

50–5–10–15

20

40

60

80

100

120

07981-030

TEMPERATURE (°C)

07981-032

–4

TEMPERATURE (°C)

Figure 12. Leakage Currents as a Function of Temperature, ±5 V Dual Supply

252015

Figure 15. Leakage Currents as a Function of Temperature,

3.3 V Single Supply

600500400300

LEAKAGE CURRENT (nA

)

1050–5–10–15

IDD (µA)

2001000–100

2

4

6LOGIC (V)

8

10

12

07981-00507981-009

TEMPERATURE (°C)

07981-031

–20

Figure 13. Leakage Currents as a Function of Temperature,

12 V Single Supply

20

300

Figure 16. IDD vs. Logic Level

15LEAKAGE CURRENT (nA)

250

CHARGE INJECTION (pC)

200

10

150

5

100

–4

–2

2

4VS (V)

6

8

10

12

14

20

40

60

80

100

120

07981-019

50

–5

0–6

TEMPERATURE (°C)

Figure 14. Leakage Currents as a Function of Temperature,

5 V Single Supply

Figure 17. Charge Injection vs. Source Voltage (VS)

Rev. A | Page 11 of 16

数字模拟开关

ADG1611/ADG1612/ADG1613

500450400350

–1

INSERTION LOSS (dB)

07981-018

TIME (ns)

300250200150100500–60

–2

–3

–4

–5

–40

–20

20

40

60

TEMPERATURE (°C)

80

100

120

140

10k100k1M10M100M1G

FREQUENCY (Hz)

07981-00407981-016

–61k

Figure 18. tON/tOFF

Times vs. Temperature Figure 21. On Response vs. Frequency

OFF ISOLATION (dB)

–10–15–20–25–30

–5

–20

10k100k

FREQUENCY (Hz)

1M10M

FREQUENCY (Hz)

Figure 19. Off Isolation vs. Frequency

0–20–40

0.200.180.160.14

Figure 22. ACPSRR vs. Frequency

CROSSTALK (dB)

–60–80–100–120–140

THD + N (%)

0.120.100.080.060.040.02

07981-017

05k10k15k20k25k

FREQUENCY (Hz)

FREQUENCY (Hz)

Figure 20. Crosstalk vs. Frequency

Figure 23. THD + N vs. Frequency

Rev. A | Page 12 of 16

07981-008

10k100k1M10M100M1G

07981-007

–35–40–45–50–55–60–65–70–75–80–85

1k

–40

ACPSRR (dB)

–60

–80

–100

–120

1k

数字模拟开关

TEST CIRCUITS

IV0

20-18970

Figure 24. On Resistance

VS

1

20-189

70Figure 25. Off Leakage

2

20-18970

Figure 26. On Leakage

ADG1611/ADG1612/ADG1613

OFF ISOLATION = 20 log

6

2V0S

-1

8970Figure 27. Off Isolation

L

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

V7

2V0S

-

18970Figure 28. Channel-to-Channel Crosstalk

V8

20INSERTION LOSS = 20 log

-1V8OUTWITHOUT SWITCH

970Figure 29. Bandwidth

Rev. A | Page 13 of 16

数字模拟开关

ADG1611/ADG1612/ADG1613

07981-029

Figure 30. THD + Noise

VVIN

VS

VIN

VOUT

07981-023

Figure 31. Switching Times

VIN

0V

50%

50%

VV

OUT1

VOUT1

VOUT2

07981-024

Figure 32. Break-Before-Make Time Delay

VINADG1612

ON

OFF

VINVOUT

07981-025

Figure 33. Charge Injection

Rev. A | Page 14 of 16

数字模拟开关

ADG1611/ADG1612/ADG1613

tON

The delay between applying the digital control input and the output switching on. See Figure 31.

tOFF

The delay between applying the digital control input and the output switching off. See Figure 31.

Charge Injection

A measure of the glitch impulse transferred from the digital input to the analog output during switching. See Figure 33. Off Isolation

A measure of unwanted signal coupling through an off switch. See Figure 27.

Crosstalk

A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. See Figure 28.

Bandwidth

The frequency at which the output is attenuated by 3 dB. See Figure 29.

On Response

The frequency response of the on switch. Insertion Loss

The loss due to the on resistance of the switch.

Total Harmonic Distortion + Noise (THD + N)

The ratio of the harmonic amplitude plus noise of the signal to the fundamental. See Figure 30.

AC Power Supply Rejection Ratio (ACPSRR)

The ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p.

TERMINOLOGY

IDD

The positive supply current. ISS

The negative supply current.

VD (VS)

The analog voltage on Terminal D and Terminal S. RON

The ohmic resistance between Terminal D and Terminal S. RFLAT(ON)

Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range.

IS (Off)

The source leakage current with the switch off. ID (Off)

The drain leakage current with the switch off. ID, IS (On)

The channel leakage current with the switch on. VINL

The maximum input voltage for Logic 0. VINH

The minimum input voltage for Logic 1. IINL (IINH)

The input current of the digital input.

CS (Off)

The off switch source capacitance, which is measured with reference to ground.

CD (Off)

The off switch drain capacitance, which is measured with reference to ground.

CD, CS (On)

The on switch capacitance, which is measured with reference to ground. CIN

The digital input capacitance.

Rev. A | Page 15 of 16

数字模拟开关

ADG1611/ADG1612/ADG1613

OUTLINE DIMENSIONS

0.150.05

COPLANARITY

0.10

1.20COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

0.500.40FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

1.000.850.80COMPLIANTTOJEDEC STANDARDS MO-220-VGGC.

031006-A

0.18

COPLANARITY

0.08

Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad (CP-16-13)

Dimensions shown in millimeters

ORDERING GUIDE

Package Description

1

ADG1611BRUZ 40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP]

1

ADG1611BRUZ-REEL 40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP]

1

ADG1611BRUZ-REEL7 40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP]

1

ADG1611BCPZ-REEL 40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

1

ADG1611BCPZ-REEL7 40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

1

ADG1612BRUZ-REEL 40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] ADG1612BRUZ-REEL71 40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP]

1

ADG1612BCPZ- REEL 40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

1

ADG1612BCPZ-REEL7 40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

1

ADG1613BRUZ-REEL 40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP]

1

ADG1613BRUZ-REEL7 40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] ADG1613BCPZ-REEL1 40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

1

ADG1613BCPZ-REEL7 40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

1

Package Option

RU-16 RU-16 RU-16 CP-16-13CP-16-13RU-16 RU-16 CP-16-13CP-16-13RU-16 RU-16 CP-16-13CP-16-13

Z = RoHS Compliant Part.

©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07981-0-9/09(A)

Rev. A | Page 16 of 16

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