DSP最小系统原理图

在stand alone模式中安装 Master Mode不安装 Slave Mode

芯片复位由DSP控制，MCBSP口时钟稳定后，由DSP程序控制拉高复位电平 VCC3V3

VCC3V3 C1 0.1uF C2 1uF SCL_M0 SDA_M1 VCC3V3 C10 0.1uF C11 1uF R3 10K R4 10K CS4272_SDOUT

1

CS4272_MCLK CS4272_LRCLK CS4272_SCLK R2 33 CS4272_SDIN

MSMODE

CS4272_RESET R5 10K R6 10K

1 2 3 4 5 6 7 8 9 10 11 12 13 14

XTO XTI MCCLK LRCK SCLK SDOUT SDIN DGND VD VL SCL/CCLK SDA/CDIN AD0/CS RST

BMUTEC AOUTBAOUTB+ AOUTA+ AOUTAAMUTEC FILT+ AGND VA AINBAINB+ AINA+ AINAVCOM

28 27 26 25 24 23 22 21 20 19 18 17 16 15

CS_AOUT_RN CS_AOUT_RP CS_AOUT_LP CS_AOUT_LN

VCC5V C3 0.1uF C5 C4 10uF 20uF 1uF C6

3

GND/ADJ TAB

4

R1

47K

U1

U2

VIN

VOUT

2C7

VCC3V3

AMS1117_3V3

20uF

1CS_AIN_RN CS_AIN_RP CS_AIN_LP CS_AIN_LN C12 0.1uF C13 L1 C8 0.1uF C9 1uF

2FB

VCC5V

CS4272该芯片可用局部管脚去耦

VCC3V3

VCC3V3 VCC5V

3C14 20uF C15 0.1uF

GND/ADJ TAB

4

1uF

U3

VIN

VOUT

2R7

VCC1V2

如果由DSP来控制，去掉这几个电阻如果工作在Stand alone方式，用这几个电阻配置主从工作方式

1

AMS1117_ADJ GND1V2 C17 10uF

1K C16 R8 0 20uF

L2 C18 C20 C22 U4 1uF 0.1uF 0.01uF C23 0.01uF VCC12VN VCC3V3 CYVDD REF4_OUT REF2_OUT R11 R12 33 33 VCC12VP DSP_CLKIN MCBSP_CLKIN

2FB

1

VCC5V C19 R9 33 CS4272_MCLK C21 1uF 0.1uF

L3

2FB

1

VCC3V3

VCC5V U5 REF_OUT

J1

VCC12VP C24 47uF C25 47uF

1 7

NC GND

VCC CLK

14 8

osc_power OSC_CLK R10 33 REFIN

1 2 3 4

CLOCK

REF GND REFIN NC

OE VDD REF4 REF2

8 7 6 5

1 2 3 4 5CON4

注意电源完整性问题必须用局部管脚去耦

CY2303

VCC5V C26 47uF J2 U6C C27 47uF

VCC12VN

C28 47uF

C29 47uF

2 4 6 8 10 12 14HEADER 7X2

1 3 5 7 9 11 13

CLKX1 FSX1 DX1 CLKR1 FSR1 DR1_SDA1 CLKS1_SCL1 SCL_M0 SDA_M1 R16 R17 0 0 SCL0 SDA0

L3 L1 L2 M1 M3 M2 E1 N1 N2

CLKX1/AMUTE0 FSX1 DX1/AXR0[5] CLKR1/AXR0[6] FSR1/AXR0[7] DR1/SDA1 CLKS1/SCL1 SCL0 SDA0

CLKX0/ACLKX0 FSX0/AFSX0 DX0/AXR0[1] CLKR0/ACLKR0 FSR0/AFSR0 DR0/AXR0[0] CLKS0/AHCLKR0McBSP_I2C

G3 H1 H2 H3 J3 J1 K3

R13 R14 R15

33 33 33

CS4272_SCLK CS4272_LRCLK CS4272_SDIN CS4272_SCLK CS4272_LRCLK CS4272_SDOUT MCBSP_CLKIN

VCC5V TP1 VCC12VP TP3 TP4 VCC12VN TP5 TP6 TP2

XNET中点引出馈线返回输入端

外部电源滤波

TMS320C6713GDP

如果Codec工作在Stand Alone模式，去掉这两个电阻VCC3V3 VCC3V3 R18 R19 R20 R21 10K SCL0 10K SDA0 TP9 10K DR1_SDA1 10K CLKS1_SCL1 TP7 TP8

VCC1V2

5

4

3

2

1

ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7D

1 R22 8 2 7 3 6 4 5 1 R26 8 2 7 3 6 4 5 1 R25 8 2 7 3 6 4 5 1 R27 8 2 7 3 6 4 5 1 R29 8 2 7 3 6 4 5 1 R32 8 2 7 3 6 4 5 1 R34 8 2 7 3 6 4 5 1 R36 8 2 7 3 6 4 5

R_ED0 R_ED1 R_ED2 R_ED3 R_ED4 R_ED5 R_ED6 R_ED7 R_ED8 R_ED9 R_ED10 R_ED11 R_ED12 R_ED13 R_ED14 R_ED15 R_ED16 R_ED17 R_ED18 R_ED19 R_ED20 R_ED21 R_ED22 R_ED23 R_ED24 R_ED25 R_ED26 R_ED27 R_ED28 R_ED29 R_ED30 R_ED31 EA5 EA4 EA3 EA2 EA9 EA8 EA6 EA7 EA13 EA12 EA11 AWE EA18 EA15 EA16 EA14 EA20 EA19 EA17 ARE AOE ECLKOUT EA10

U6A ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 ED8 ED9 ED10 ED1

1 ED12 ED13 ED14 ED15 ED16 ED17 ED18 ED19 ED20 ED21 ED22 ED23 ED24 ED25 ED26 ED27 ED28 ED29 ED30 ED31 CE0 CE1 CE2 CE3

U8

U7

1 R24 8 2 7 3 6 4 5 1 R23 8 2 7 3 6 4 5 1 R28 8 2 7 3 6 4 5 1 R30 8 2 7 3 6 4 5 1 R33 8 2 7 3 6 4 5 1 R35 8 2 7 3 6 4 5

R_EA5 R_EA4 R_EA3 R_EA2 R_EA9 R_EA8 R_EA6 R_EA7 R_EA13 R_EA12 R_EA11 R_AWE R_EA18 R_EA15 R_EA16 R_EA14 R_EA20 R_EA19 R_EA17 R_ARE R_AOE R_ECLKOUT R_EA10

ED8 ED9 ED10 ED11 ED12 ED13 ED14 ED15 ED16 ED17 ED18 ED19 ED20 ED21 ED22 ED23 ED24 ED25 ED26 ED27 ED28 ED29 ED30 ED31

K18 K19 L18 L19 M19 M20 N18 N19 N20 P18 P20 R19 R20 T18 T20 T19 V4 W4 Y3 V2 V1 U2 U1 U3 T1 T2 R3 R2 P1 P2 P3 N3 V17 W18 W6 V6

ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 ED8 ED9 ED10 ED11 ED12 ED13 ED14 ED15 ED16 ED17 ED18 ED19 ED20 ED21 ED22 ED23 ED24 ED25 ED26 ED27 ED28 ED29 ED30 ED31 CE0 CE1 CE2 CE3

EMIF6713

EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 EA17 EA18 EA19 EA20 EA21

Y6 V7 W7 V8 W8 Y8 V9 Y9 V10 W13 V14 W14 Y14 W15 Y15 V16 Y16 W17 Y18 U18 V11 W10 V12 Y5 Y11 Y10 J19 J17 J18 V5 Y4 U19 V20

EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 EA17 EA18 EA19 EA20 ARE AOE AWE ARDY ECLKOUT BUSRQ HOLD HOLDA BE3 BE2 BE1 BE0

R_ED15 R_ED14 R_ED13 R_ED12 R_ED11 R_ED10 R_ED9 R_ED8 R_ED7 R_ED6 R_ED5 R_ED4 R_ED3 R_ED2 R_ED1 R_ED0 R_AWE R_AOE CE1

45 43 41 39 36 34 32 30 44 42 40 38 35 33 31 29 11 28 26 37

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WE# OE# CE# VDD VSS_27 VSS_46

ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE ARDY ECLKIN ECLKOUT BUSREQ HOLD HOLDA BE3 BE2 BE1 BE0TMS320C6713GDP

VCC3V3 C30 0.1uF

27 46

A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 NC1 NC2 NC3 NC4 NC5 NC6 NC7

16 17 48 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25 9 10 12 13 14 15 47

R_EA20 R_EA19 R_EA18 R_EA17 R_EA16 R_EA15 R_EA14 R_EA13 R_EA12 R_EA11 R_EA10 R_EA9 R_EA8 R_EA7 R_EA6 R_EA5 R_EA4 R_EA3 R_EA2

SST39VF800A

R_ED0 R_ED1 R_ED2 R_ED3 R_ED4 R_ED5 R_ED6 R_ED7 R_ED8 R_ED9 R_ED10 R_ED11 R_ED12 R_ED13 R_ED14 R_ED15 R_ED16 R_ED17 R_ED18 R_ED19 R_ED20 R_ED21 R_ED22 R_ED23 R_ED24 R_ED25 R_ED26 R_ED27 R_ED28 R_ED29 R_ED30 R_ED31 VCC3V3

2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 33 34 36 37 39 40 42 45 47 48 50 51 53 54 56 3 9 35 41 49 55 75 81 6 12 32 38 46 52 78 84

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VDDQ0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 BA0 BA1 DQM0 DQM1 DQM2 DQM3 CLK CKE CS# WE# CAS# RAS# NC0 NC1 NC2 NC3 NC4 NC5 NC6

25 26 27 60 61 62 63 64 65 66 24 22 23 16 71 28 59 68 67 20 17 18 19 14 21 30 57 69 70 73

R_EA2 R_EA3 R_EA4 R_EA5 R_EA6 R_EA7 R_EA8 R_EA9 R_EA10 R_EA11 R_EA12 R_EA13 R_EA14 BE0 BE1 BE2 BE3 R_ECLKOUT CKE R31 CE0 R_AWE R_ARE R_AOE 1K

D

VCC3V3

阻值和板子的层叠结构有关

C

C

VCC3V3

VDD_1 VDD_15 VDD_29 VDD_43 VSS_44 VSS_58 VSS_72 VSS_86

1 15 29 43 44

58 72 86

R37 SW1 DSP-RESET D2 LED R40 1K VCC3V3 R41

1K

D1

LED

VCC3V3

MT48LC2M32B2B5-6 1K D3 LED VCC3V3 C35 C31 0.1uF C32 0.1uF C36 0.1uF C33 0.1uF C34 0.1uF C37 0.1uF C38 0.1uF

U6B NMI GP_INT7 GP_INT6 GP_INT5 GP_INT4 CLKOUT2 CLKOUT3 L4 E1 EMI FILTER

VCC3V3

R39

1K

A13 C13 E3 D2 C1 C2 Y12 D10 C4 A3 C5 B7 A8 A7 A6 B6 D9 B9 D3 B10 C11 B12 F1 F2 G1 G2

RESET NMI GP[7]/(EXT_INT7) GP[6]/(EXT_INT6) GP[5]/(EXT_INT5)/AMUTEIN0 GP[4]/(EXT_INT4)/AMUTEIN1 CLOKOUT2/GP[2] CLKOUT3 CLKMODE0 CLKIN PLLHVHDI_GPIO_INT_JTAG_TIMER_CLOCK

VCC3V3B

GND

1FB

2

DSP_PLL_FB

1

I

O

3C40 10uF

DSP_CLKIN

DSP_CLKIN DSP_PLLHV DSP_TMS DSP_TDO DSP_TDI DSP_TCK DSP_TRST# DSP_EMU0 DSP_EMU1

2

C41 0.1uF

PLL滤波要局部去耦，很重要尽量靠近DSP放置

TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 TOUT1/AXR0[4] TINP1/AHCLKX0 TOUT0/AXR0[2] TINP0/AXR0[3]

HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8] HD7/GP[3] HD6/AHCKR1 HD5/AHCKX1 HD4/GP[0] HD3/AMUTE1 HD2/AFSX1 HD1/AXR1[7] HD0/AXR1[4] HAS/ACLKX1 HRDY/ACLKR1 HDS2/AXR1[5] HDS1/AXR1[6] HCS/AXR1[2]

B14 C14 A15 C15 A16 B16 C16 B17 A18 C17 B18 C19 C20 D18 D20 E20 E18 H19 F18 E19 F20 J20 G19 G18 H20 G20

DSP_GP15 DSP_HD14 DSP_GP13 DSP_HD12 CS4272_RESET DSP_HD8

R38 R42

1K 10K VCC3V3

0.1uF

R43

10K

VCC3V3B

DSP_HD4 DSP_HD3

R44 R45

1K 1K

VCC3V3 C39 C42 1uF 0.1uF

VCC3V3

J3 DSP_TMS DSP_TDI DSP_TDO DSP_TCK DSP_EMU0

TOUT1 TINP1 TOUT0 TINP0 VCC3V3 CE0 CE1 CE2 CE3 ARE AOE AWE BUSRQ HOLD HOLDA ARDY R46 R49 R50 R51 R52 R53 R55 R54 R56 R57 R58 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K

HINT/GP[1] HCNTL1/AXR1[1] HCNTL0/AXR1[3] HHWIL/AFSR1 HR/W/AXR1[0]

1 3 5 7 9 11 13

TMS TDI PD_VCC TDO TCK_RET TCK EMU0JTAG

TRST GND_4 NC GND_8 GND_10 GND_12 EMU1

2 4 6 8 10 12 14

DSP_TRST#

DSP_EMU1

TMS320C6713GDP R47 10K VCC3V3 J5 GP_INT4 GP_INT5 GP_INT6 GP_INT7 NMI J4 R48 10K

A

2 4 6 8 10

1 3 5 7 9HEADER 5X2

CLKOUT2 CLKOUT3 TOUT0 TINP0 TOUT1 TINP1

2 4 6 8 10 12

1 3 5 7 9 11HEADER 6X2

A

5

4

3

2

1

5

4

3

2

1

D

D

VCC1V2

U6D

C

VCC3V3

A4 A9 A10 B2 B19 C3 C7 C18 D5 D6 D11 D14 D15 F4 F17 K1 K4 K17 L4 L17 L20 R4 R17 U6 U10 U11 U14 U15 V3 V18 W2 W19 A17 B3 B8 B13 C10 D1 D16 D19 F3 H18 V13 J2 M18 R1 R18 T3 U5 U7 U12 U16 V15 V19 W3 W9 W12 Y7 Y17

CVDD_32 CVDD_31 CVDD_30 CVDD_29 CVDD_28 CVDD_27 CVDD_26 CVDD_25 CVDD_24 CVDD_23 CVDD_22 CVDD_21 CVDD_20 CVDD_19 CVDD_18 CVDD_17 CVDD_16 CVDD_15 CVDD_14 CVDD_13 CVDD_12 CVDD_11 CVDD_10 CVDD_9 CVDD_8 CVDD_7 CVDD_6 CVDD_5 CVDD_4 CVDD_3 CVDD_2 CVDD_1 DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 DVDD6 DVDD7 DVDD8 DVDD9 DVDD10 DVDD11 DVDD12 DVDD13 DVDD14 DVDD15 DVDD16 DVDD17 DVDD18 DVDD19 DVDD20 DVDD21 DVDD22 DVDD23 DVDD24 DVDD25 DVDD26 DVDD27 RSV7 RSV5 RSV6 RSV4 RSV3 RSV2 RSV1

DSP_POWER

B

VCC1V2

R59

D7 A12 B11 D12 C12 B5 A5

VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35

VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68

A1 A2 A11 A14 A19 A20 B1 B4 B15 B20 C6 C8 C9 D4 D8 D13 D17 E2 E4 E17 F19 G4 G17 H4 H17 J4 J9 J10 J11 J12 K9 K10 K11 K12 K20 L9 L10 L11 L12 M4 M9 M10 M11 M12 M17 N4 N17 P4 P17 P19 T4 T17 U4 U8 U9 U13 U17 U20 W1 W5 W11 W16 W20 Y1 Y2 Y13 Y19 Y20 K2

VCC1V2 C43 2.2uF C44 2.2uF C45 2.2uF C46 2.2uF预留空间

C47 220nF

C48 220nF

C49 220nF

C50 220nF

C51 22nF

C52 22nF

C53 22nF

C54 22nF

C55 22nF

C56 22nF

C57 22nF

C58 22nF

C59 2.2nF

C60 2.2nF

C61 2.2nF

C62 2.2nF

C63 2.2nF

C64 2.2nF

C65 2.2nF

C66 2.2nF

C67 2.2nF

C68 2.2nF

C69 2.2nF

C70 2.2nF

C71 2.2nF

C72 2.2nF

C73 2.2nF

C74 2.2nFC

VCC3V3 C75 2.2uF C76 2.2uF C77 2.2uF C78 2.2uF

预留空间

C79 100nF

C80 100nF

C81 100nF

C82 100nFB

C83 10nF

C84 10nF

C85 10nF

C86 10nF

C87 10nF

C88 10nF

C89 1nF

C90 1nF

C91 1nF

C92 1nF

C93 1nF

C94 1nF

C95 1nF

C96 1nF

C97 1nF

C98 1nF

C99 1nF

C100 1nF

10K TMS320C6713GDP

A

A

5

4

3

2

1

5

4

3

2

1

R60

15K R61 C101 220pF C102 220pF 15K

CS_AOUT_LND

R62

3K

R63 C103 2000pF

12K C104

R64

3K

VCC12VP

R65

10K VCC12VP

8

N1A

2200pF

1NE5532

R66

4.7K6

8

2 3

N1B N2A

D

+

7

R67

3K

R68 C106 1600pF

12K

R69 C107 2200pF

3K

2 3

5+NE5532

+

1

R70

33

C105 1uF

LOUT J6

CS_AOUT_LP

4

R71

3K

R72 C108 2000pF

12K C109 2200pF

R73 R74 15K

3K VCC12VN C110 220pF VCC12VP

4

NE5532 VCC12VP VCC12VN

VCC12VN

VCC12VN

C111 0.1uF

C112 10uF

C113 0.1uF

C114 10uF

C115 0.1uF

C116 10uF

C117 0.1uF

C118 10uF

GND R L NCL NCR GND

1 2 3 4 5 6

ROUT LOUT

AUDIO_RJ

J7 R75 15K R76 C119 220pF VCC12VPC

15K

C120 220pF R80 10K

CS_AOUT_RN

R77

3K

R78 C121 2000pF

12K C122

R79

3K

GND R L NCL NCR GND

1 2 3 4 5 6

RIN LIN

C

AUDIO_RJ

8

N3A

22200pF

N3B R81 4.7K6 N2B -

+

1NE5532

3

7

R82

3K

R83 C124 1600pF

12K

R84 C125 2200pF

3K

6

5+NE5532

-

7

R85

33

C123 1uF

ROUT

5+NE5532

CS_AOUT_RP

R86

3K

R87 C126 2000pF

12K C128 2200pF

R88 R89 15K

3K VCC12VN C127 220pF VCC12VP

4

VCC12VN

C129 0.1uF

C130 10uF

C131 0.1uF

C132 10uF

VCC12VP R90 R91B

VCC12VN

634 C134 0.1uF C135 10uF C136 0.1uF C138 10uF

634 C133 470pF VCC12VPB

C137 470pF VCC12VP

8

2N4A 1 NE5532 R93 91 CS_AIN_LP RIN R96 R95 100K 634 R100 C144 634 470pF N4B C141 2700pF R103 3.3K C139 1uF

8 2LIN R94 VCC5V 100K R98 100K R102 VCC12VN C140 1uF+ N5A 1 NE5532

+

R92

91

3

CS_AIN_RP

3

4

VCC5V R101 100K

4

R97 634 R99 C143 N5B 634 C142 2700pF 470pF

VCC12VN

6

3.3K

6

-

-

7NE5532

R104

91

7NE5532

R105

91

5+C145 10uF C146 C149 0.1uF R106 0.01uF 3.3K C153A

CS_AIN_LN C147 10uF C148 R107 0.1uF 3.3K C154 10uF C155 0.1uF C156 10uF 0.01uF 100uF C150 C152

5+

CS_AIN_RN

C151 100uF

VCC12VP

VCC12VN

0.1uF

A

5

4

3

2

1

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