三星S3C2440A英文数据手册

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S3C2440A 32-BIT RISC MICROPROCESSOR USER'S MANUAL

(Preliminary)

Revision0.12

(March15,2004)

2004.03.15

Preliminary product information describes products that are in development,

for which full characterization data and associated errata are not yet available

Specifications and information herein are subject to change without notice.S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-1

1PRODUCT OVERVIEW

INTRODUCTION

This manual describes SAMSUNG's S3C2440A 16/32-bit RISC microprocessor.SAMSUNG’s S3C2440A is designed to provide hand-held devices and general applications with low-power,and high-performance micro-controller solution in small die size.To reduce total system cost,the S3C2440A includes the following components separate 16KB Instruction and 16KB Data Cache,MMU to handle virtual memory management,LCD Controller (STN &TFT),NAND Flash Boot Loader,System Manager (chip select logic and SDRAM Controller),3-ch UART,4-ch DMA,4-ch Timers with PWM,I/O Ports,RTC,8-ch 10-bit ADC and Touch Screen Interface,Camera interface,IIC-BUS Interface,IIS-BUS Interface,USB Host,USB Device,SD Host &Multi-Media Card Interface,2-ch SPI and PLL for clock generation.

The S3C2440A is developed with ARM920T core,0.13um CMOS standard cells and a memory complier.Its low-power,simple,elegant and fully static design is particularly suitable for cost-and power-sensitive applications.It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).

The S3C2440A offers outstanding features with its CPU core,a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines,Ltd.The ARM920T implements MMU,AMBA BUS,and Harvard cache architecture with separate 16KB instruction and 16KB data caches,each with an 8-word line length.

By providing a complete set of common system peripherals,the S3C2440A minimizes overall system costs and eliminates the need to configure additional components.The integrated on-chip functions that are described in this document include:

Around 1.2V internal,1.8V/2.5V/3.3V memory,3.3V external I/O microprocessor with 16KB I-Cache/16KB D-Cache/MMU ?

External memory controller (SDRAM Control and Chip Select logic)?

LCD controller (up to 4K color STN and 256K color TFT)with 1-ch LCD-dedicated DMA ?

4-ch DMAs with external request pins ?

3-ch UART (IrDA1.0,64-Byte Tx FIFO,and 64-Byte Rx FIFO)/2-ch SPI ?

1-ch multi-master IIC-BUS/1-ch IIS-BUS controller ?

SD Host interface version 1.0&Multi-Media Card Protocol version 2.11compatible ?

2-port USB Host /1-port USB Device (ver 1.1)?

4-ch PWM timers &1-ch internal timer ?

Watch Dog Timer ?

130-bit general purpose I/O ports /24-ch external interrupt source ?

Power control:Normal,Slow,Idle and Sleep mode ?

8-ch 10-bit ADC and Touch screen interface ?

RTC with calendar function ? On-chip clock generator with PLL

2004.03.15

Preliminary product information describes products that are in development,for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice.

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

1-2

FEATURES

Architecture

? Integrated system for hand-held devices and general embedded applications.

? 16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core.? Enhanced ARM architecture MMU to support WinCE,EPOC 32and Linux.

Instruction cache,data cache,write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance.

? ARM920T CPU core supports the ARM debug architecture.

Internal Advanced Microcontroller Bus

Architecture (AMBA)(AMBA2.0,AHB/APB).

System Manager

? Little/Big Endian support.

? Address space:128M bytes for each bank (total 1G bytes).

? Supports programmable 8/16/32-bit data bus width for each bank.

? Fixed bank start address from bank 0to bank 6.? Programmable bank start address and bank size for bank 7.

Eight memory banks:

–Six memory banks for ROM,SRAM,and others.–Two memory banks for ROM/SRAM/Synchronous DRAM.

? Complete Programmable access cycles for all memory banks.

? Supports external wait signals to expand the bus cycle.

? Supports self-refresh mode in SDRAM for power-down.

Supports various types of ROM for booting (NOR/NAND Flash,EEPROM,and others).

NAND Flash Boot Loader

? Supports booting from NAND flash memory.? 4KB internal buffer for booting.

? Supports storage memory for NAND flash memory after booting.

Supports Advanced NAND flash

Cache Memory

? 64-way set-associative cache with I-Cache (16KB)and D-Cache (16KB).

? 8words length per line with one valid bit and two dirty bits per line.

? Pseudo random or round robin replacement algorithm.

Write-through or write-back cache operation to update the main memory.

The write buffer can hold 16words of data and four addresses.

Clock &Power Manager

On-chip MPLL and UPLL:

UPLL generates the clock to operate USB Host/Device.

MPLL generates the clock to operate MCU at maximum 533Mhz @1.35V.

? Clock can be fed selectively to each function block by software.

Power mode :Normal,Slow,Idle,and Sleep mode

Normal mode :Normal operating mode

Slow mode :Low frequency clock without PLL Idle mode :The clock for only CPU is stopped.Sleep mode :The Core power including all peripherals is shut down.

Woken up by EINT[15:0]or RTC alarm interrupt from Sleep mode

2004.03.15

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

1-3

FEATURES (Continued)

Interrupt Controller

60Interrupt sources

(One Watch dog timer,5timers,9UARTs,24external interrupts,4DMA,2RTC,2ADC,1IIC,2SPI,1SDI,2USB,1LCD,1Battery Fault,1NAND and 2Camera),1AC97

? Level/Edge mode on external interrupt source ? Programmable polarity of edge and level ?

Supports Fast Interrupt request (FIQ)for very urgent interrupt request

Timer with Pulse Width Modulation (PWM)

4-ch 16-bit Timer with PWM /1-ch 16-bit internal timer with DMA-based or interrupt-based operation

? Programmable duty cycle,frequency,and polarity ? Dead-zone generation

Supports external clock sources

RTC (Real Time Clock)

? Full clock feature:msec,second,minute,hour,date,day,month,and year ? 32.768KHz operation ? Alarm interrupt ?

Time tick interrupt

General Purpose Input/Output Ports

? 24external interrupt ports ?

Multiplexed input/output ports

DMA Controller

? 4-ch DMA controller

? Supports memory to memory,IO to memory,memory to IO,and IO to IO transfers

Burst transfer mode to enhance the transfer rate

LCD Controller STN LCD Displays Feature

Supports 3types of STN LCD panels:4-bit dual scan,4-bit single scan,8-bit single scan display type

Supports monochrome mode,4gray levels,16

gray levels,256colors and 4096colors for STN LCD

Supports multiple screen size

–Typical actual screen size:640x480,320x240,

160x160,and others.–Maximum frame buffer size is 4Mbytes.–Maximum virtual screen size in 256color mode:

4096x1024,2048x2048,1024x4096and others TFT(Thin Film Transistor)Color Displays Feature

? Supports 1,2,4or 8bpp (bit-per-pixel)palette color displays for color TFT

? Supports 16,24bpp non-palette true-color displays for color TFT

? Supports maximum 16M color TFT at 24bpp mode

LPC3600Timing controller embedded for LTS350Q1-PD1/2(SAMSUNG 3.5”Portrait /256K-color/Reflective a-Si TFT LCD)?

LCC3600Timing controller embedded for LTS350Q1-PE1/2(SAMSUNG 3.5”Portrait /256K-color/Transflective a-Si TFT LCD)?

Supports multiple screen size

–Typical actual screen size:640x480,320x240,

160x160,and others.–Maximum frame buffer size is 4Mbytes.

–Maximum virtual screen size in 64K color mode :

2048x1024,and others UART

? 3-channel UART with DMA-based or interrupt-based operation

? Supports 5-bit,6-bit,7-bit,or 8-bit serial data transmit/receive (Tx/Rx)

? Supports external clocks for the UART operation (UEXTCLK)

Programmable baud rate ? Supports IrDA 1.0? Loopback mode for testing

Each channel has internal 64-byte Tx FIFO and 64-byte Rx FIFO.

2004.03.15

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

1-4

FEATURES (Continued)

A/D Converter &Touch Screen Interface

? 8-ch multiplexed ADC

? Max.500KSPS and 10-bit Resolution ?

Internal FET for direct Touch screen interface

Watchdog Timer

? 16-bit Watchdog Timer

Interrupt request or system reset at time-out IIC-Bus Interface

? 1-ch Multi-Master IIC-Bus

Serial,8-bit oriented and bi-directional data transfers can be made at up to 100Kbit/s in

Standard mode or up to 400Kbit/s in Fast mode.

IIS-Bus Interface

1-ch IIS-bus for audio interface with DMA-based operation

? Serial,8-/16-bit per channel data transfers ? 128Bytes (64-Byte +64-Byte)FIFO for Tx/Rx ?

Supports IIS format and MSB-justified data format AC97Audio-CODEC Interface

? Support 16-bit samples

1-ch stereo PCM inputs/1-ch stereo PCM outputs 1-ch MIC input

USB Host

? 2-port USB Host

? Complies with OHCI Rev.1.0

Compatible with USB Specification version 1.1USB Device

? 1-port USB Device

? 5Endpoints for USB Device

Compatible with USB Specification version 1.1SD Host Interface

? Support SD/MMC Controller reset register.?

Normal,Interrupt and DMA data transfer

mode(byte,halfword,word transfer)

? DMA burst4access support(only word transfer)?

Compatible with SD Memory Card Protocol version 1.0

? Compatible with SDIO Card Protocol version 1.0? Bytes FIFO for Tx/Rx

Compatible with Multimedia Card Protocol version 2.11

SPI Interface

Compatible with 2-ch Serial Peripheral Interface Protocol version 2.11

? 2x8bits Shift register for Tx/Rx

DMA-based or interrupt-based operation Camera Interface

? ITU-R BT 601/6568-bit mode support ? DZI (Digital Zoom In)capability

? Programmable polarity of video sync signals ?

Max.4096x 4096pixels input support (2048x 2048pixel input support for scaling)

Image mirror and rotation (X-axis mirror,Y-axis mirror,and 180°rotation)

Camera output format (RGB 16/24-bit and YCbCr 4:2:0/4:2:2format)

Operating Voltage Range

Core :1.20V for 300MHz

1.30V for 400MHz 1.35V for 533MHz ? Memory:1.8V/

2.5V/

3.0V/3.3V ?

I/O :3.3V

Operating Frequency

? Fclk Up to 533MHz ? Hclk Up to 136MHz ?

Pclk Up to 68MHz Package

289-FBGA

2004.03.15

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

1-5

BLOCK DIAGRAM

ARM920T

ARM9TDMI Processor core

(Internal Embedded ICE)DD[31:0]WriteBack PA Tag RAM

Data MMU

C13

DVA[31:0]

Instruction CACHE (16KB)

Instruction MMU External Coproc Interface

C13

ID[31:0]

IPA[31:0]

IVA[31:0]

CP15

Write Buffer AMBA Bus I/F

JTAG

Data CACHE (16KB)

WBPA[31:0]

DPA[31:0]Bridge &DMA (4Ch)

Clock Generator

(MPLL)

A H

B B U S

Memory CONT.SRAM/NOR/SDRAM

BUS CONT.Arbitor/Decode Power Management Interrupt ed47f644336c1eb91a375d3fB Host CONT.

ExtMaster LCD DMA

LCD CONT.

P B B U S

I2C GPIO I2S

RTC SPI ADC SDI/MMC USB Device

Watchdog Timer BUS CONT.Arbitor/Decode Timer/PWM 0~3,4(Internal)

SPI 0,1

UART 0,1,2

NAND Ctrl.NAND Flash Boot

Loader

Camera Interface

AC97

Figure 1-1.S3C2440A Block Diagram

2004.03.15

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR PIN ASSIGNMENTS

1234567891011121314151617

BOTTOM VIEW

Figure1-2.S3C2440A Pin Assignments(289-FBGA)

1-6

Preliminary product information describes products that are in development,

for which full characterization data and associated errata are not yet available

Specifications and information herein are subject to change without notice.

2004.03.15

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

1-7

Table 1-1.289-Pin FBGA Pin Assignments –Pin Number Order (Sheet 1of 3)

Pin Number Pin Name

A1VDDi C1VDDMOP E1nFRE/GPA20A2SCKE C2nGCS5/GPA16E2VSSMOP A3VSSi C3nGCS2/GPA13E3nGCS7A4VSSi C4nGCS3/GPA14E4nWAIT A5VSSMOP C5nOE E5nBE3A6VDDi C6nSRAS E6nWE A7VSSMOP C7ADDR4E7ADDR1A8ADDR10C8ADDR11E8ADDR6A9VDDMOP C9ADDR15E9ADDR14A10VDDi C10ADDR21/GPA6E10ADDR23/GPA8A11VSSMOP C11ADDR24/GPA9E11DATA2A12VSSi C12DATA1E12DATA20A13DATA3C13DATA6E13DATA19A14DATA7C14DATA11E14DATA18A15VSSMOP C15DATA13E15DATA17A16VDDi C16DATA16E16DATA21A17DATA10C17VSSi E17DATA24B1VSSMOP D1ALE/GPA18F1VDDi B2nGCS1/GPA12D2nGCS6F2VSSi

B3SCLK1D3nGCS4/GPA15F3nFWE/GPA19B4SCLK0D4nBE0F4nFCE/GPA22B5nBE1D5nBE2F5CLE/GPA17B6VDDMOP D6nSCAS F6nGCS0B7ADDR2D7ADDR7F7ADDR0/GPA0B8ADDR9D8ADDR5F8ADDR3B9ADDR12D9ADDR16/GPA1F9ADDR18/GPA3B10VSSi D10ADDR20/GPA5F10DATA4B11VDDi D11ADDR26/GPA11F11DATA5B12VDDMOP D12DATA0F12DATA27B13VSSMOP D13DATA8F13DATA31B14VDDMOP D14DATA14F14DATA26B15DATA9D15DATA12F15DATA22B16VDDMOP D16VSSMOP F16VDDi B17

DATA15

D17

VSSMOP

F17

VDDMOP

2004.03.15

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

1-8

Table 1-1.289-Pin FBGA Pin Assignments –Pin Number Order (Sheet 2of 3)

Pin Number Pin Name

G1VSSOP

J1VDDOP L1LEND/GPC0G2CAMHREF/GPJ10J2VDDiarm

L2VDDiarm G3CAMDATA1/GPJ1J3CAMCLKOUT/GPJ11L3nXDACK0/GPB9G4VDDalive J4CAMRESET/GPJ12L4VCLK/GPC1G5CAMPCLK/GPJ8J5TOUT1/GPB1L5nXBREQ/GPB6G6FRnB

J6TOUT0/GPB0L6VD1/GPC9G7CAMVSYNC/GPJ9J7TOUT2/GPB2L7VFRAME/GPC3G8ADDR8J8CAMDATA6/GPJ6L8I2SSDI/AC_SDATA_IN G9ADDR17/GPA2J9SDDAT3/GPE10L9SPICLK0/GPE13G10ADDR25/GPA10J10EINT10/nSS0/GPG2L10EINT15/SPICLK1/GPG7G11DATA28J11TXD2/nRTS1/GPH6L11EINT22/GPG14G12DATA25J12PWREN L12Xtortc G13DATA23J13TCK L13EINT2/GPF2G14XTIpll J14TMS

L14EINT5/GPF5G15XTOpll J15RXD2/nCTS1/GPH7L15EINT6/GPF6G16DATA29J16TDO L16EINT7/GPF7G17VSSi J17VDDalive L17nRTS0/GPH1H1VSSiarm

K1VSSiarm M1VLINE/GPC2H2CAMDATA7/GPJ7K2nXBACK/GPB5M2LCD_LPCREV/GPC6H3CAMDATA4/GPJ4K3TOUT3/GPB3M3LCD_LPCOE/GPC5H4CAMDATA3/GPJ3K4TCLK0/GPB4M4VM/GPC4H5CAMDATA2/GPJ2K5nXDREQ1/GPB8M5VD9/GPD1H6CAMDATA0/GPJ0K6nXDREQ0/GPB10M6VD6/GPC14

H7CAMDATA5/GPJ5K7nXDACK1/GPB7M7VD16/SPIMISO1/GPD8H8ADDR13K8SDCMD/GPE6M8SDDAT1/GPE8H9ADDR19/GPA4K9SPIMISO0/GPE11

M9IICSDA/GPE15H10ADDR22/GPA7K10EINT13/SPIMISO1/GPG5

M10EINT20/GPG12H11VSSOP K11nCTS0/GPH0M11EINT17/nRTS1/GPG9H12EXTCLK K12VDDOP M12VSSA_UPLL H13DATA30K13TXD0/GPH2M13VDDA_UPLL H14nBATT_FLT K14RXD0/GPH3M14Xtirtc H15nTRST K15UEXTCLK/GPH8M15EINT3/GPF3H16nRESET K16TXD1/GPH4M16EINT1/GPF1H17

TDI

K17

RXD1/GPH5

M17

EINT4/GPF4

2004.03.15

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

1-9

Table 1-1.289-Pin FBGA Pin Assignments –Pin Number Order (Sheet 3of 3)

Pin Number Pin Name

N1VSSOP R1VD3/GPC11U1VDDiarm N2VD0/GPC8R2VD8/GPD0U2VDDiarm N3VD4/GPC12R3VD11/GPD3U3VSSOP N4VD2/GPC10R4VD13/GPD5

U4VSSiarm

N5VD10/GPD2R5VD18/SPICLK1/GPD10U5VD23/nSS0/GPD15

N6VD15/GPD7R6VD21/GPD13

U6I2SSDO/AC_SDATA_OUT

N7VD22/nSS1/GPD14R7I2SSCLK/AC_BIT_CLK U7VSSiarm N8SDCLK/GPE5R8SDDAT0/GPE7U8IICSCL/GPE14N9EINT8/GPG0

R9CLKOUT0/GPH9U9VSSOP N10EINT18/nCTS1/GPG10R10EINT11/nSS1/GPG3

U10VSSiarm N11DP0R11EINT14/SPIMOSI1/GPG6

U11VDDi

N12DN1/PDN0R12NCON U12EINT19/TCLK1/GPG11N13nRSTOUT/GPA21R13OM1U13EINT23/GPG15N14MPLLCAP R14AIN0U14DP1/PDP0N15VDD_RTC R15AIN2U15VSSOP N16VDDA_MPLL R16XM/AIN6U16Vref N17EINT0/GPF0

R17VSSA_MPLL U17

AIN1

P1LCD_LPCREVB/GPC7T1VSSiarm P2VD5/GPC13T2VSSiarm P3VD7/GPC15T3VDDOP

P4VD12/GPD4T4VD17/SPIMOSI1/GPD9P5VD14/GPD6

T5VD19/GPD11P6VD20/GPD12

T6VDDiarm

P7I2SLRCK/AC_SYNC T7CDCLK/AC_nRESET P8SDDAT2/GPE9T8VDDiarm P9SPIMOSI0/GPE12T9EINT9/GPG1P10CLKOUT1/GPH10

T10EINT16/GPG8P11EINT12/LCD_PWREN/GPG4

T11EINT21/GPG13P12DN0T12VDDOP P13OM2T13OM3P14VDDA_ADC T14VSSA_ADC P15AIN3T15OM0P16XP/AIN7T16YM/AIN4P17

UPLLCAP

T17

YP/AIN5

2004.03.15

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

1-10

Table 1-2.S3C2440A 289-Pin FBGA Pin Assignments (Sheet 1of 9)

Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O State @nRESET I/O Type F7ADDR0/GPA0ADDR0Hi-z/–O(L)/–O(L)t10s E7ADDR1ADDR1Hi-z O(L)O(L)t10s B7ADDR2ADDR2Hi-z O(L)O(L)t10s F8ADDR3ADDR3Hi-z O(L)O(L)t10s C7ADDR4ADDR4Hi-z O(L)O(L)t10s D8ADDR5ADDR5Hi-z O(L)O(L)t10s E8ADDR6ADDR6Hi-z O(L)O(L)t10s D7ADDR7ADDR7Hi-z O(L)O(L)t10s G8ADDR8ADDR8Hi-z O(L)O(L)t10s B8ADDR9ADDR9Hi-z O(L)O(L)t10s A8ADDR10ADDR10Hi-z O(L)O(L)t10s C8ADDR11ADDR11Hi-z O(L)O(L)t10s B9ADDR12ADDR12Hi-z O(L)O(L)t10s H8ADDR13ADDR13Hi-z O(L)O(L)t10s E9ADDR14ADDR14Hi-z O(L)O(L)t10s C9ADDR15ADDR15Hi-z O(L)O(L)t10s D9ADDR16/GPA1ADDR16Hi-z/–O(L)/–O(L)t10s G9ADDR17/GPA2ADDR17Hi-z/–O(L)/–O(L)t10s F9ADDR18/GPA3ADDR18Hi-z/–O(L)/–O(L)t10s H9ADDR19/GPA4ADDR19Hi-z/–O(L)/–O(L)t10s D10ADDR20/GPA5ADDR20Hi-z/–O(L)/–O(L)t10s C10ADDR21/GPA6ADDR21Hi-z/–O(L)/–O(L)t10s H10ADDR22/GPA7ADDR22Hi-z/–O(L)/–O(L)t10s E10ADDR23/GPA8ADDR23Hi-z/–O(L)/–O(L)t10s C11ADDR24/GPA9ADDR24Hi-z/–O(L)/–O(L)t10s G10ADDR25/GPA10ADDR25Hi-z/–O(L)/–O(L)t10s D11ADDR26/GPA11

ADDR26Hi-z/–O(L)/–O(L)t10s R14AIN0AIN0––AI r10U17AIN1AIN1––AI r10R15AIN2AIN2––AI r10P15AIN3AIN3––AI r10T16YM/AIN4AIN4–/––/–AI r10T17YP/AIN5YP –/––/–AI r10R16

XM/AIN6

AIN6

–/–

r10

2004.03.15

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

1-11

Table 1-2.S3C2440A 289-Pin FBGA Pin Assignments (Sheet 2of 9)

Pin Number Pin Name Default Function I/O State @BUS REQ

I/O State @Sleep I/O State @nRESET

I/O Type P16XP/AIN7XP –/––/–AI r10H6CAMDATA0/GPJ0GPJ0–/–Hi-z/–I t8G3CAMDATA1/GPJ1GPJ1–/–Hi-z/–I t8H5CAMDATA2/GPJ2GPJ2–/–Hi-z/–I t8H4CAMDATA3/GPJ3GPJ3–/–Hi-z/–I t8H3CAMDATA4/GPJ4GPJ4–/–Hi-z/–I t8H7CAMDATA5/GPJ5GPJ5–/–Hi-z/–I t8J8CAMDATA6/GPJ6GPJ6–/–Hi-z/–I t8H2CAMDATA7/GPJ7GPJ7–/–Hi-z/–I t8G5CAMPCLK/GPJ8GPJ8–/–Hi-z/–I t8G7CAMVSYNC/GPJ9GPJ9–/–Hi-z/–I t8G2CAMHREF/GPJ10GPJ10–/–Hi-z/–I t8J3CAMCLKOUT/GPJ11GPJ11–/–O(L)/–I t8J4CAMRESET/GPJ12

GPJ12–/–O(L)/–I t8D12DATA0DATA0Hi-z Hi-z,O(L)I b12s C12DATA1DATA1Hi-z Hi-z,O(L)I b12s E11DATA2DATA2Hi-z Hi-z,O(L)I b12s A13DATA3DATA3Hi-z Hi-z,O(L)I b12s F10DATA4DATA4Hi-z Hi-z,O(L)I b12s F11DATA5DATA5Hi-z Hi-z,O(L)I b12s C13DATA6DATA6Hi-z Hi-z,O(L)I b12s A14DATA7DATA7Hi-z Hi-z,O(L)I b12s D13DATA8DATA8Hi-z Hi-z,O(L)I b12s B15DATA9DATA9Hi-z Hi-z,O(L)I b12s A17DATA10DATA10Hi-z Hi-z,O(L)I b12s C14DATA11DATA11Hi-z Hi-z,O(L)I b12s D15DATA12DATA12Hi-z Hi-z,O(L)I b12s C15DATA13DATA13Hi-z Hi-z,O(L)I b12s D14DATA14DATA14Hi-z Hi-z,O(L)I b12s B17DATA15DATA15Hi-z Hi-z,O(L)I b12s C16DATA16DATA16Hi-z Hi-z,O(L)I b12s E15DATA17DATA17Hi-z Hi-z,O(L)I b12s E14

DATA18

Hi-z

Hi-z,O(L)

b12s

2004.03.15

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

1-12

Table 1-2.S3C2440A 289-Pin FBGA Pin Assignments (Sheet 3of 9)

Pin Number Pin Name Default Function I/O State @BUS REQ

I/O State @Sleep I/O State @nRESET

I/O Type E13DATA19DATA19Hi-z Hi-z,O(L)I b12s E12DATA20DATA20Hi-z Hi-z,O(L)I b12s E16DATA21DATA21Hi-z Hi-z,O(L)I b12s F15DATA22DATA22Hi-z Hi-z,O(L)I b12s G13DATA23DATA23Hi-z Hi-z,O(L)I b12s E17DATA24DATA24Hi-z Hi-z,O(L)I b12s G12DATA25DATA25Hi-z Hi-z,O(L)I b12s F14DATA26DATA26Hi-z Hi-z,O(L)I b12s F12DATA27DATA27Hi-z Hi-z,O(L)I b12s G11DATA28DATA28Hi-z Hi-z,O(L)I b12s G16DATA29DATA29Hi-z Hi-z,O(L)I b12s H13DATA30DATA30Hi-z Hi-z,O(L)I b12s F13DATA31DATA31Hi-z Hi-z,O(L)

I b12s P12DN0DN0––AI us N11DP0DP0––AI us N12DN1/PDN0DN1–/––AI us U14DP1/PDP0DP1–/––AI us N17EINT0/GPF0GPF0–/–Hi-z/–I t8M16EINT1/GPF1GPF1–/–Hi-z/–I t8L13EINT2/GPF2GPF2–/–Hi-z/–I t8M15EINT3/GPF3GPF3–/–Hi-z/–I t8M17EINT4/GPF4GPF4–/–Hi-z/–I t8L14EINT5/GPF5GPF5–/–Hi-z/–I t8L15EINT6/GPF6GPF6–/–Hi-z/–I t8L16EINT7/GPF7GPF7–/–Hi-z/–I t8N9EINT8/GPG0GPG0–/–Hi-z/–I t8T9EINT9/GPG1GPG1–/–Hi-z/–I t8J10EINT10/nSS0/GPG2GPG2–/–/–Hi-z/Hi-z/–I t8R10EINT11/nSS1/GPG3GPG3–/–/–Hi-z/Hi-z/–I t8P11EINT12/LCD_PWREN/GPG4GPG4–/–/–Hi-z/O(L)/–I t8K10EINT13/SPIMISO1/GPG5GPG5–/–/–Hi-z/Hi-z/–I tt8R11EINT14/SPIMOSI1/GPG6GPG6–/–/–Hi-z/Hi-z/–I tt8L10

EINT15/SPICLK1/GPG7

GPG7

–/–/–

Hi-z/Hi-z/–

tt8

2004.03.15

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

1-13

Table 1-2.S3C2440A 289-Pin FBGA Pin Assignments (Sheet 4of 9)

Pin Number Pin Name Default Function I/O State @BUS REQ

I/O State @Sleep I/O State @nRESET

I/O Type

T10EINT16/GPG8GPG8–/–Hi-z/–I t8M11EINT17/nRTS1/GPG9GPG9–/–/–Hi-z/O(H)/–I t8N10EINT18/nCTS1/GPG10GPG10–/–/–Hi-z/Hi-z/–I t8U12EINT19/TCLK1/GPG11

GPG11–/–/–Hi-z/Hi-z/–I t12M10EINT20/GPG12GPG12–/–Hi-z/–I t12T11EINT21/GPG13GPG13–/–Hi-z/–I t12L11EINT22/GPG14GPG14–/–Hi-z/–I t12U13EINT23/GPG15

GPG15–/–Hi-z/–I t12H12EXTCLK EXTCLK ––AI is P17UPLLCAP UPLLCAP ––AI r50N14MPLLCAP MPLLCAP ––AI r50H14nBATT_FLT

nBATT_FLT

––I is D4nBE0nBE0Hi-z Hi-z,O(H)O(H)t10s B5nBE1nBE1Hi-z Hi-z,O(H)O(H)t10s D5nBE2nBE2Hi-z Hi-z,O(H)O(H)t10s E5nBE3nBE3Hi-z Hi-z,O(H)

O(H)t10s R12NCON NCON ––I is G6FRnB FRnB –Hi-z,O(L)I d2s F3nFWE/GPA19GPA19O(H)/–Hi-z,O(H)/–O(H)t10s E1nFRE/GPA20GPA20O(H)/–Hi-z,O(H)/–O(H)t10s F4nFCE/GPA22GPA21O(H)/–Hi-z,O(H)/–O(H)t10s F5CLE/GPA17GPA17O(L)/–Hi-z,O(L)/–O(L)t10s D1ALE/GPA18GPA18O(L)/–Hi-z,O(L)/–O(L)t10s N13nRSTOUT/GPA21

GPA21–/–O(L)/–O(L)b8C5nOE nOE Hi-z Hi-z,O(H)

O(H)t10s H16nRESET nRESET ––I is F6nGCS0nGCS0Hi-z Hi-z,O(H)O(H)t10s B2nGCS1/GPA12GPA12Hi-z/–Hi-z,O(H)/–O(H)t10s C3nGCS2/GPA13GPA13Hi-z/–Hi-z,O(H)/–O(H)t10s C4nGCS3/GPA14GPA14Hi-z/–Hi-z,O(H)/–O(H)t10s D3nGCS4/GPA15GPA15Hi-z/–Hi-z,O(H)/–O(H)t10s C2nGCS5/GPA16

GPA16Hi-z/–Hi-z,O(H)/–O(H)t10s D2

nGCS6

Hi-z

Hi-z,O(H)

O(H)

t10s

2004.03.15

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

1-14

Table 1-2.S3C2440A 289-Pin FBGA Pin Assignments (Sheet 5of 9)

Pin Number Pin Name Default Function I/O State @BUS REQ

I/O State @Sleep I/O State @nRESET I/O Type E3nGCS7nGCS7Hi-z Hi-z,O(H)O(H)t10s D6nSCAS nSCAS Hi-z Hi-z,O(H)O(H)t10s C6nSRAS nSRAS Hi-z Hi-z,O(H)

O(H)t10s H15nTRST nTRST I –I is E4nWAIT nWAIT –Hi-z,O(L)I d2s E6nWE nWE Hi-z Hi-z,O(H)O(H)t10s J6TOUT0/GPB0GPB0–/–O(L)/–I t8J5TOUT1/GPB1GPB1–/–O(L)/–I t8J7TOUT2/GPB2GPB2–/–O(L)/–I t8K3TOUT3/GPB3GPB3–/–O(L)/–I t8K4TCLK0/GPB4GPB4–/––/–I t8K2nXBACK/GPB5GPB5–/–O(H)/–I t8L5nXBREQ/GPB6GPB6–/––/–I t8K7nXDACK1/GPB7GPB7–/–O(H)/–I t8K5nXDREQ1/GPB8GPB8–/––/–I t8L3nXDACK0/GPB9GPB9–/–O(H)/–I t8K6nXDREQ0/GPB10

GPB10–/––/–I t8T15OM0OM0––I is R13OM1OM1––I is P13OM2OM2––I is T13OM3OM3––I is J12PWREN PWREN O(H)O(L)O(H)b8K11nCTS0/GPH0GPH0–/––/–I t8L17nRTS0/GPH1GPH1–/–O(H)/–I t8K13TXD0/GPH2GPH2–/–O(H)/–I t8K14RXD0/GPH3GPH3–/––/–I t8K16TXD1/GPH4GPH4–/–O(H)/–I t8K17RXD1/GPH5GPH5–/––/–I t8J11TXD2/nRTS1/GPH6GPH6–/–/–O(H)/O(H)/–I t8J15RXD2/nCTS1/GPH7GPH7–/–/–Hi-z/Hi-z/–I t8K15UEXTCLK/GPH8GPH8–/–Hi-z/–I t8R9CLKOUT0/GPH9GPH9–/–O(L)/–I t12P10

CLKOUT1/GPH10

GPH10

–/–

O(L)/–

t12

2004.03.15

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

1-15

Table 1-2.S3C2440A 289-Pin FBGA Pin Assignments (Sheet 6of 9)

Pin Number Pin Name Default Function I/O State @BUS REQ

I/O State @Sleep I/O State @nRESET I/O Type A2SCKE SCKE Hi-z O(L)O(H)t10s B4SCLK0SCLK0Hi-z O(L)O(SCLK)t12s B3SCLK1

SCLK1Hi-z O(L)O(SCLK)

t12s P7I2SLRCK/AC_SYNC GPE0–/–Hi-z/–I t8R7I2SSCLK/AC_BIT_CLK GPE1–/–Hi-z/–I t8T7CDCLK/AC_nRESET GPE2–/–Hi-z/–I t8L8I2SSDI/AC_SDATA_IN GPE3–/–/–Hi-z/Hi-z/–I t8U6I2SSDO/AC_SDATA_OUT

GPE4–/–/–O(L)/Hi-z/–I t8N8SDCLK/GPE5GPE5–/–O(L)/–I t8K8SDCMD/GPE6GPE6–/–Hi-z/–I t8R8SDDAT0/GPE7GPE7–/–Hi-z/–I t8M8SDDAT1/GPE8GPE8–/–Hi-z/–I t8P8SDDAT2/GPE9GPE9–/–Hi-z/–I t8J9SDDAT3/GPE10GPE10–/–Hi-z/–I t8K9SPIMISO0/GPE11GPE11–/–Hi-z/–I tt8P9SPIMOSI0/GPE12GPE12–/–Hi-z/–I tt8L9SPICLK0/GPE13GPE13–/–Hi-z/–I tt8U8IICSCL/GPE14GPE14–/–Hi-z/–I d8M9IICSDA/GPE15

GPE15–/–Hi-z/–I d8J13TCK TCK I –I is H17TDI TDI I –I is J16TDO TDO O O O ot J14TMS TMS I –I is L1LEND/GPC0GPC0–/–O(L)/–I t8L4VCLK/GPC1GPC1–/–O(L)/–I t8M1VLINE/GPC2GPC2–/–O(L)/–I t8L7VFRAME/GPC3GPC3–/–O(L)/–I t8M4VM/GPC4GPC4–/–O(L)/–I t8M3LCD_LPCOE/GPC5GPC5–/–O(L)/–I t8M2LCD_LPCREV/GPC6GPC6–/–O(L)/–I t8P1LCD_LPCREVB/GPC7

GPC7–/–O(L)/–I t8N2VD0/GPC8GPC8–/–O(L)/–I t8L6

VD1/GPC9

GPC9

–/–

O(L)/–

2004.03.15

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

1-16

Table 1-2.S3C2440A 289-Pin FBGA Pin Assignments (Sheet 7of 9)

Pin Number Pin Name Default Function I/O State @BUS REQ

I/O State @Sleep I/O State @nRESET

I/O Type

N4VD2/GPC10GPC10–/–O(L)/–I t8R1VD3/GPC11GPC11–/–O(L)/–I t8N3VD4/GPC12GPC12–/–O(L)/–I t8P2VD5/GPC13GPC13–/–O(L)/–I t8M6VD6/GPC14GPC14–/–O(L)/–I t8P3VD7/GPC15GPC15–/–O(L)/–I t8R2VD8/GPD0GPD0–/–O(L)/–I t8M5VD9/GPD1GPD1–/–O(L)/–I t8N5VD10/GPD2GPD2–/–O(L)/–I t8R3VD11/GPD3GPD3–/–O(L)/–I t8P4VD12/GPD4GPD4–/–O(L)/–I t8R4VD13/GPD5GPD5–/–/–O(L)/O/–I t8P5VD14/GPD6GPD6–/–/–O(L)/O/–I t8N6VD15/GPD7GPD7–/–/–O(L)/O/–I t8M7VD16/SPIMISO1/GPD8GPD8–/–/–O(L)/Hi-z/–I tt8T4VD17/SPIMOSI1/GPD9GPD9–/–/–O(L)/Hi-z/–I tt8R5VD18/SPICLK1/GPD10

GPD10–/–/–O(L)/Hi-z/–I tt8T5VD19//GPD11GPD11–/–/–O(L)/Hi-z/–I t8P6VD20/GPD12GPD12–/–/–O(L)/Hi-z/–I t8R6VD21/GPD13GPD13–/–/–O(L)/Hi-z/–I t8N7VD22/nSS1/GPD14GPD14–/–/–O(L)/Hi-z/–I t8U5VD23/nSS0/GPD15

GPD15–/–/–O(L)/Hi-z/–

I t8U16Vref Vref ––AI ia G14XTIpll XTIpll ––AI m26M14Xtirtc Xtirtc ––AI nc G15XTOpll XTOpll ––AO m26L12Xtortc Xtortc ––AO nc N15VDD_RTC VDD_RTC P P P drtc P14VDDA_ADC VDDA_ADC P P P d33th N16VDDA_MPLL VDDA_MPLL P P P d12t M13VDDA_UPLL VDDA_UPLL P P P d12t G4VDDalive VDDalive P P P d12i J17

VDDalive

d12i

2004.03.15

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

1-17

Table 1-2.S3C2440A 289-Pin FBGA Pin Assignments (Sheet 8of 9)

Pin Number Pin Name Default Function I/O State @BUS REQ

I/O State @Sleep

I/O State @nRESET

I/O Type A1VDDi VDDi P P P d12c A10VDDi VDDi P P P d12c A16VDDi VDDi P P P d12c A6VDDi VDDi P P P d12c B11VDDi VDDi P P P d12c F1VDDi VDDi P P P d12c F16VDDi VDDi P P P d12c U11VDDi VDDi P P P d12c L2VDDiarm VDDiarm P P P d12c T6VDDiarm VDDiarm P P P d12c T8VDDiarm VDDiarm P P P d12c U1VDDiarm VDDiarm P P P d12c J2VDDiarm VDDiarm P P P d12c U2VDDiarm VDDiarm P P P d12c A9VDDMOP VDDMOP P P P d33o B12VDDMOP VDDMOP P P P d33o B14VDDMOP VDDMOP P P P d33o B16VDDMOP VDDMOP P P P d33o B6VDDMOP VDDMOP P P P d33o C1VDDMOP VDDMOP P P P d33o F17VDDMOP VDDMOP P P P d33o J1VDDOP VDDOP P P P d33o T12VDDOP VDDOP P P P d33o T3VDDOP VDDOP P P P d33o K12VDDOP VDDOP P P P d33o T14VSSA_ADC VSSA_ADC P P P sth R17VSSA_MPLL VSSA_MPLL P P P st M12VSSA_UPLL

VSSA_UPLL

P P P st A12VSSi VSSi P P P si A3VSSi VSSi P P P si A4VSSi VSSi P P P si B10VSSi VSSi P P P si C17

VSSi

2004.03.15

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

1-18

Table 1-2.S3C2440A 289-Pin FBGA Pin Assignments (Sheet 9of 9)

Pin Number Pin Name Default Function I/O State @BUS REQ

I/O State @Sleep

I/O State @nRESET

I/O Type

F2VSSi VSSi P P P si G17VSSi VSSi P P P si H1VSSiarm VSSiarm P P P si K1VSSiarm VSSiarm P P P si T1VSSiarm VSSiarm P P P si T2VSSiarm VSSiarm P P P si U10VSSiarm VSSiarm P P P si U4VSSiarm VSSiarm P P P si U7VSSiarm VSSiarm P P P si A11VSSMOP VSSMOP P P P so A15VSSMOP VSSMOP P P P so A5VSSMOP VSSMOP P P P so A7VSSMOP VSSMOP P P P so B1VSSMOP VSSMOP P P P so B13VSSMOP VSSMOP P P P so D16VSSMOP VSSMOP P P P so D17VSSMOP VSSMOP P P P so E2VSSMOP VSSMOP P P P so G1VSSOP VSSOP P P P so N1VSSOP VSSOP P P P so U15VSSOP VSSOP P P P so U3VSSOP VSSOP P P P so U9VSSOP VSSOP P P P so H11

VSSOP

2004.03.15

Preliminary product information describes products that are in development,

for which full characterization data and associated errata are not yet available

Specifications and information herein are subject to change without notice.S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-19

NOTE:

1.The @BUS REQ.shows the pin state at the external bus,which is used by the other bus master.

2.'–‘mark indicates the unchanged pin state at Bus Request mode.

3.Hi-z or Pre means Hi-z or early state and it is determined by the setting of MISCCR register.

4.AI/AO means analog input/analog output.

5.P,I,and O mean power,input and output respectively.

6.The I/O state @nRESET shows the pin status in the @nRESET duration below.nRESET FCLK

@nRESET

4FCLK

2004.03.15

Preliminary product information describes products that are in development,

for which full characterization data and associated errata are not yet available

Specifications and information herein are subject to change without notice.PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-20

THE TABLE BELOW SHOWS I/O TYPES AND DESCRIPTIONS.Input (I)/Output (O)Type

Descriptions

d12i(vdd12ih)

1.2V Vdd for alive power d12c(vdd12ih_core),si(vssih)

1.2V Vdd/Vss for internal logic d33o(vdd33oph),so(vssoph)

3.3V Vdd/Vss for external logic d33th(vdd33th_abb)

,sth(vssbbh_abb)

3.3V Vdd/Vss for analog circuitry d12t(vdd12t_abb),st(vssbb_abb)

1.2V Vdd/Vss for analog circuitry drtc(vdd30th_rtc)

3.0V Vdd for RTC power t8(phbsu100ct8sm)

Bi-directional pad,LVCMOS schmitt-trigger,100Kohm pull-up resistor with control,tri-state,Io=8mA is(phis)

Input pad,LVCMOS schmitt-trigger level us(pbusb0)

USB pad t10(phtot10cd)

5V tolerant Output pad,Tri-state .ot(phot8)

Output pad,tri-state,Io=8mA b8(phob8)

Output pad,Io=8mA t16(phot16sm)

Output pad,tri-state,medium slew rate,Io=16mA r10(phiar10_abb)

Analog input pad with 10-ohm resistor ia(phia_abb)

Analog input pad gp(phgpad_option)

Pad for analog pin m26(phsoscm26_2440a)

Oscillator cell with enable and feedback resistor tt8(phtbsu100ct8sm_esd)

5V Tolerant Bi-directional pad,LVCMOS schmitt-trigger,100Kohm pull-up resistor with control,tri -state,medium slew rate,Io=8mA t12(phbsu100ct12sm)

Bi-directional pad,LVCMOS schmitt-trigger,100Kohm pull-up resistor with control,tri-state,Io=12mA d8(phbsd8sm)

Bi-directional pad,LVCMOS schmitt-trigger,Open Drain,Io=8mA t10s(phtot10cd_10_2440a)

output pad,LVCMOS ,tri -state,output drive strenth control,Io=4,6,8,10mA b12s(phtbsu100ct12cd_12_2440a)

Bi-directional pad,LVCMOS schmitt-trigger,100Kohm pull-up resistor with control,tri -state,output drive strenth control,Io=6,8,10,12mA d2s(phtbsd2_2440a)

Bi-directional pad,LVCMOS schmitt-trigger,open-drain,output drive strenth ignore,r50(phoar50_abb)

Analog Output pad,50Kohm resistor,Separated bulk-bias t12s(phtot12cd_12_2440a)

output pad,LVCMOS ,tri -state,output drive strenth control,Io=6,8,10,12mA nc(phnc)No connection pad

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