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www.altera.com101InnovationDrive,SanJose,CA951342014.08.18AlteraLVDSSERDESIPCoreUserGuide

SubscribeSendFeedbackug_altera_lvdsTheAlteraLVDSSERDESIPCoreconfigurestheserializer/deserializer(SERDES)anddynamicphasealignment(DPA)blocks.TheIPcorealsosupportsLVDSchannelsplacement,legalitychecks,andLVDSchannel-relatedrulechecks.

TheAlteraLVDSSERDESIPcoreisonlyavailableforArria10devices.ForArriaV,CycloneV,and

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StratixVdevices,followthestepsinMigratingYourALTLVDS_TXandALTLVDS_RXIPCoresonpage25tomigrateyourIP.

RelatedInformation

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?LVDSSERDESTransmitter/Receiver(ALTLVDS_TXandALTLVDS_RX)MegafunctionsUserGuide

Features

YoucanconfigurethefeaturesofAlteraLVDSSERDESIPcorethroughtheIPParameterEditorinthe

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QuartusIIsoftware.TheAlteraLVDSSERDESIPcorefeatureincludestheALTLVDS_RXandALTLVDS_TXIPcoresfeaturessupportedinStratixVdevices,suchas:??????

Parameterizabledatachannelwidths

Parameterizableserializer/deserializer(SERDES)factorsRegisteredinputandoutputportsPLLcontrolsignals

Dynamicphasealignment(DPA)modeSoftclockdatarecovery(CDR)mode

FunctionalModes

ThistableliststhefunctionalmodesfortheAlteraLVDSSERDESIPcore.

Table1:FunctionalModesfortheAlteraLVDSSERDESIPCore

FunctionalMode

Description

TX

Inthismode,theIPcoreconfigurestheSERDESblockasaserializer.APLLgeneratesthefastclock(fclk)andloadenable(loaden)signals.

?2014AlteraCorporation.Allrightsreserved.ALTERA,ARRIA,CYCLONE,ENPIRION,MAX,MEGACORE,NIOS,QUARTUSandSTRATIXwords

andlogosaretrademarksofAlteraCorporationandregisteredintheU.S.PatentandTrademarkOfficeandinothercountries.Allotherwordsandlogosidentifiedastrademarksorservicemarksarethepropertyoftheirrespectiveholdersasdescribedatwww.altera.com/common/legal.html.AlterawarrantsperformanceofitssemiconductorproductstocurrentspecificationsinaccordancewithAltera'sstandardwarranty,butreservestherighttomakechangestoanyproductsandservicesatanytimewithoutnotice.Alteraassumesnoresponsibilityorliabilityarisingoutoftheapplicationoruseofanyinformation,product,orservicedescribedhereinexceptasexpresslyagreedtoinwritingbyAltera.Alteracustomersareadvisedtoobtainthelatestversionofdevicespecificationsbeforerelyingonanypublishedinformationandbeforeplacingordersforproductsorservices.

ISO9001:2008Registered

2FunctionalDescription

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FunctionalModeDescription

RXNon-DPAMode

Inthismode,youmustensurethecorrectclock-dataalignment,astheincomingdataiscapturedatthebitslipwiththefclksignal.TheDPAandDPA-FIFOarebypassed.Asinthetransmittermode,thefclksignalisprovidedbyaPLL.

Inthismode,theDPAblockselectsanoptimalphasetosampleincomingdatafromasetofeightDPAclocksrunningatthefclkfrequency,each45°outofphase.TheDPA-FIFO,acircularbuffer,samplestheincomingdatawiththeselectedDPAclockandforwardsthedatatoLVDSclockdomain.ThedatareleasedfromtheDPA-FIFOisthensampledatthebitslipcircuitry,whereitislagged,andthus,realignedtomatchthedesiredwordboundarywhenitisdeserialized.

Toavoidclockmetastabilityissues,afterFIFOresets,waitfortwocoreclockcyclesbeforeresettingthebitslip.

Note:AllRXchannelsmustbeplacedinoneI/Obank,whichsupports

upto24channelsonly.

RXDPA-FIFO

RXSoft-CDRMode

Inthismode,theoptimalDPAclock(DPACLK)isforwardedintotheLVDSclockdomain,whereitisusedasthefclksignal.Thelocalclockgeneratorproducesrx_divfwdclkwhichwillbeforwardedtothecorethroughaPCLKnetwork.Note,thereisalimitationofthenumberofsoft-CDRchannelsduetoPCLKusage.

Note:RXinterfacesmustbeplacedinoneI/Obank,andeachbank

onlyhas12PCLKresources,hence12soft-CDRchannels.Note:Foractualsoft-CDRsupportedchannel,refertotherespective

devicepinoutlist.Under\Tx/RxChannel\therewillbeavalueofformLVDS__.Thepinpairsupportssoft-CDRmodeonlywhenisanevennumber.

FunctionalDescription

AsingleAlteraLVDSSERDESchannelcontainsaSERDES,abitslipblock,DPAcircuitryforallmodes,ahigh-speedclocktree(LVDSclocktree)andforwardedclocksignalforsoft-CDRmode.YoucanconfiguretheAlteraLVDSSERDESchannelasareceiveroratransmitterforasingledifferentialI/O.Therefore,ann-channelLVDSinterfacecontainsn-serdes_dpablocks.TheI/OPLLsdrivetheLVDSclocktree,providingclockingsignalstotheAlteraLVDSSERDESchannelintheI/Obank.

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FPGAFabricug_altera_lvds2014.08.18Serializer+-tx_inDOUTFigure1:DINAlteraLVDSSERDESChannelDiagram10FunctionalDescriptiontx_out3tx_coreclock3lvds_loadenlvds_fclktx_coreclockLVDSTransmitterLVDSReceiverrx_out10DeserializerDOUTDINBitslipDOUTDINDPAFIFODOUTDINDPACircuitryRetimedDataDIN+-rx_inDPAClock2loadenfclkrx_divfwdclkrx_coreclock3lvds_loadenlvds_fclkrx_coreclockfclklvds_fclkdpa_fclk3dpa_loadendpa_fclkrx_divfwdclkClockMultiplexer8SerialLVDSClockPhasesrx_inclock/tx_inclockLVDSClockDomainDPAClockDomainIOPLL(LocalClockGenerator)EachAlteraLVDSSERDESchannelcanbebrokendownintothefollowingpaths,withsevenfunctionalunits:

Path

Block

Modes

ClockDomain

TXDataPathSerializerTXmodeLVDS

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TXDAT[7:0]FCLKLOADENLVDSOUT476543210SerializerabcdefghABCDEFGHXXXXXXXXug_altera_lvds2014.08.18PathBlockModesClockDomainDPAXXXXXXXXXX765432DPA10aCircuitrybcdefghABCDFIFOEFandSoft-DPACDRmodesDPAFIFOBitslipandDeserializerLocalClockGeneratorSERDESClockMultiplexersDPA-FIFOmodeLVDS-DPAdomaincrossingNon-DPAandDPA-LVDSFIFOmodesSoftCDRmodesSoft-CDRmodeAllmodesDPAclockdomainGeneratesPCLKandLOADENinthesemodesSelectsLVDSclocksourcesforallmodesThiswaveformisspecifictoserializationfactor=8.RXDataPathClockGenerationandMultiplexersSerializer

Theserializerconsistsoftwosetsofregisters.ThefirstsetofregisterscapturestheparalleldatafromthecoreusingtheLVDSfastclock.TheloadenclockisprovidedalongsidetheLVDSfastclock,toenablethesecaptureregistersoncepercoreclockperiod.Afterthedataiscaptured,thedataisthenloadedintoashiftregister,whichshiftstheLSBtowardstheMSB,onebitperfastclockcycle.TheMSBoftheshiftregisterfeedstheLVDSoutputbuffer;hence,higherorderbitsprecedelowerorderbitsintheoutputbitstream.Thefollowingfigureshowstheserializerwaveform.Figure2:LVDSx8SerializerWaveform

Signal

txdat[7:0]fclkloadenlvdsout

Description

Datatobeserialized(supportedserializationfactorsare3-10).Clockusedfortransmitter.Enablesignalforserialization.

LVDSdatastream,outputfromtheAlteraLVDSSERDESchannel.

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RX_IN76543210abcdefghABCDEFGHXXXXXXXXFCLKug_altera_lvds2014.08.18DPAFIFO5

LOADENDPARX_OUT[7:0]FIFOInDPA-FIFOmode,theDPAFIFOsynchronizestheretimeddatatothehigh-speedLVDSclockdomain.XXXXXXXX76543210abcdefghABCDEFGHBecausetheDPAclockmayshiftphaseduringtheinitiallockperiod,theFIFOmustbeheldinresetstateuntiltheDPAlocks;otherwise,theremaybeadatarun-throughconditionduetotheFIFOwritepointercreepinguptothereadpointer.Bitslip

Usebitslipcircuitrytoinsertlatenciesinincrementsofonefclkcyclefordatawordalignment.Thedataslipsonebitforeverypulseoftherx_bitslip_ctrlsignal.Youmustwaitatleastfivecoreclockcyclesbeforecheckingifthedataisalignedbecauseitwilltakeatleasttwocoreclockcyclestopurgetheundefineddata.

Whenenoughbitslipsignalsaresenttorolloverthebitslipcounter,therx_bitslip_maxstatussignalisassertedafterfivecoreclockcyclestoindicatethatithasreacheditsmaximumcountervalueofthebitslipcounterrolloverpoint.

Deserializer

Thedeserializerconsistsofshiftregisters.Thedeserializationfactordeterminesthedepthoftheshiftregisters.Theloadensignalisapulsewithafrequencyofthefclkdividedbythedeserializationfactor.The

deserializerconvertsa1-bitserialdatastreamintoaparalleldatastreambasedonthedeserializationfactor.Figure3:LVDSx8DeserializerWaveform

Signal

rx_infclkloadenrx_out[7:0]

Description

LVDSdatastream,inputtotheAlteraLVDSSERDESchannel.Clockusedforreceiver.Enablesignalfordeserialization.Deserializeddata.

InitializationandReset

Thissectiondescribestheinitializationandresetaspects,usingcontrolcharacters.ThissectionalsoprovidesarecommendedinitializationandresetflowfortheAlteraLVDSSERDESIPcore.

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6InitializingtheAlteraLVDSSERDESIPCore

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InitializingtheAlteraLVDSSERDESIPCore

WiththeAlteraLVDSSERDESIPcore,thePLLmustbelockedtothereferenceclockpriortousingtheSERDESblocksfordatatransfer.ThePLLstartstolocktothereferenceclockduringdeviceinitialization.ThePLLisoperationalwhenthePLLachieveslockduringusermode.Iftheclockreferenceisnotstableduringdeviceinitialization,thePLLoutputclockphaseshiftsbecomescorrupted.

WhenthePLLoutputclockphaseshiftsarenotsetcorrectly,thedatatransferbetweenthehigh-speedLVDSdomainandthelow-speedparalleldomainmightnotbesuccessful,whichleadstodatacorruption.Assertthepll_aresetportforatleast10ns,andthendeassertthepll_aresetportandwaituntilthePLLlockbecomesstable.AfterthePLLlockportassertsandisstable,theSERDESblocksarereadyforoperation.WhenusingDPA,furtherstepsarerequiredforinitializationandresetrecovery.TheDPAcircuitsamplestheincomingdataandfindstheoptimalphasetapfromthePLLtocapturedataonareceiverchannel-by-channelbasis.IfthePLLhasnotlockedtoastableclocksource,theDPAcircuitmightlockprematurelytoanon-idealphasetap.Usetherx_dpa_resetporttokeeptheDPAinresetuntilthePLLlocksignalisassertedandstable.

Therx_dpa_lockedsignalassertswhentheDPAhasfoundtheoptimalphasetap.

Note:Alterarecommendsassertingtherx_fifo_resetportaftertherx_dpa_lockedsignalasserts,and

thendeasserttherx_fifo_resetporttobeginreceivingdata.EachtimetheDPAshiftsthephasetapsduringnormaloperationtotrackvariationsbetweentherelationshipofthereferenceclocksourceandthedata,thetimingmarginforthedatatransferbetweenclockdomainsisreduced.

TheAlteraLVDSSERDESIPcoreassertstherx_dpa_lockedportuponinitialDPAlock.WhenyouenabletheEnableDPAlossoflockononechangeoption,therx_dpa_lockedportdeassertsafteronechangeinphase.Ifthisoptionisdisabled,therx_dpa_lockedsignalwilldeassertaftertwophasechangesinthesamedirection.

Note:Alterarecommendsusingthedatacheckerstoensuredataaccuracy.

ResettingtheDPA

Whenthedatabecomescorrupted,youmustresettheDPAcircuitryusingtherx_dpa_resetportandrx_fifo_resetport.

Asserttherx_dpa_resetporttoresettheentireDPAblock.ThisrequirestheDPAtobetrainedbeforeitisreadyfordatacapture.

Note:Alterarecommendstogglingtherx_fifo_resetportafterrx_dpa_lockedisasserted.Thisensures

thesynchronizationFIFOissetwiththeoptimaltimingtotransferdatabetweentheDPAandhigh-speedLVDSclockdomains.Asserttherx_fifo_resetporttoresetonlythesynchronizationFIFO.Thisallowsyoutocontinuesystemoperationwithouthavingtore-traintheDPA.UsingthisportcanfixdatacorruptionbecauseitresetstheFIFO;however,itdoesnotresettheDPAcircuit.

WhentheDPAislocked,theAlteraLVDSSERDESblockisreadytocapturedata.TheDPAfindstheoptimalsamplelocationtocaptureeachbit.Thenextstepistosetupthewordboundaryusingcustomlogictocontroltherx_bitslip_ctrlportonachannel-by-channelbasis.

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AligningtheWordBoundaries7

Thebitslipcircuitcanberesetusingtherx_bitslip_resetport.ThiscircuitcanberesetanytimeandisnotdependentonthePLLorDPAcircuitoperation.

AligningtheWordBoundaries

Toalignthewordboundaries,itisusefultohavecontrolcharactersinthedatastreamsothatyourlogiccanhaveaknownpatterntosearchfor.Youcancomparethedatareceivedforeachchannel,comparetothecontrolcharacteryouarelookingfor,thenpulsetherx_bitslip_ctrlportasrequireduntilyousuccessfullyreceivethecontrolcharacter.

Note:Alterarecommendssettingthebitsliprollovercounttothedeserializationfactororhigher,which

allowsenoughdepthinthebitslipcircuittorollthroughanentirewordifrequired.Ifyoudonothavecontrolcharactersinthereceiveddata,youneedadeterministicrelationshipbetweenthereferenceclockanddatatopredictthewordboundaryusingtimingsimulationorlaboratorymeasure-ments.Thisappliesonlyfornon-DPAmode.TheonlywaytoensureadeterministicrelationshiponthedefaultwordpositionintheSERDESwhenthedevicepowersup,oranytimethePLLisreset,istohaveareferenceclockequaltothedataratedividedbythedeserializationfactor.Forexample,ifthedatarateis800Mbps,andthedeserializationfactoris8,thePLLrequiresa100-MHzreferenceclock.ThisisimportantbecausethePLLlockstotherisingedgeofthereferenceclock.Ifyouhaveonerisingedgeonthereferenceclockperserialwordreceived,thedeserializeralwaysstartsatthesameposition.Usingtimingsimulation,orlabmeasurements,monitortheparallelwordsreceivedanddeterminehowmanypulsesarerequiredontherx_bitslip_ctrlporttosetyourwordboundaries.Youcancreateasimplestatemachinetoapplytherequirednumberofpulseswhenyouenterusermode,oranytimeyouresetthePLL.

Note:WhenusingDPAorsoft-CDRmodes,thewordboundaryisnotdeterministic.Theinitialtraining

oftheDPAallowsittomoveforwardorbackwardinphaserelativetotheincomingserialdata.Thus,therecanbea±1-bitofvarianceintheserialbitwheretheDPAinitiallylocks.Iftherearenotrainingpatternsorcontrolcharactersavailableintheserialbitstreamtouseforwordalignment,Alterarecommendsusingnon-DPAmode.

RecommendedInitializationandResetFlow

AlterarecommendsthatyoufollowthesestepstoinitializeandresettheAlteraLVDSSERDESIPcore:1.Duringentryintousermode,oranytimeinusermodeoperationwhentheinterfacerequiresareset,assertthepll_aresetandrx_dpa_resetports.

2.Deassertthepll_aresetportandmonitorthepll_lockedport.Fornon-DPAmode,skiptostep7.3.Deasserttherx_dpa_resetportafterthepll_lockedportbecomesassertedandstable.

4.ApplytheDPAtrainingpatternandallowtheDPAcircuittolock.(Ifatrainingpatternisnotavailable,anydatawithtransitionsisrequiredtoallowtheDPAtolock.)RefertotherespectivedevicedatasheetforDPAlocktimespecifications.

5.Waitfortherx_dpa_lockedporttoassert.

6.Assertrx_fifo_resetforatleastoneparallelclockcycle,andthende-assertrx_fifo_reset.7.Asserttherx_bitslip_resetportforatleastoneparallelclockcycle,andthendeasserttherx_bitslip_resetport.

8.Beginwordalignmentbyapplyingpulsesasrequiredtotherx_bitslip_ctrlport.

9.Whenthewordboundariesareestablishedoneachchannel,theinterfaceisreadyforoperation.

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8Signals

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Signals

ThefollowingtableslisttheinputandoutputsignalsfortheAlteraLVDSSERDESIPcore.

Note:NrepresentstheLVDSinterfacewidthandthenumberofserialchannelswhileJrepresentsthe

SERDESfactoroftheinterface.

Table2:CommonTXandRXSignals

SignalName

inclockpll_areset

WidthDirectionTypeDescription

111

InputInputOutput

ClockResetControl

PLLreferenceclock.

Active-highasynchronousresettoallblocksinAlteraLVDSSERDESandPLL.AssertedwheninternalPLLislocked.

pll_locked

Table3:RXSignals

SignalName

rx_in

rx_bitslip_reset

WidthDirectionTypeDescription

NNN

InputInputInput

DataResetControl

LVDSserialinputdata.

Asynchronous,active-highresettotheclock-dataalignmentcircuitry(bitslip).

Positive-edgetriggeredincrementforbitslipcircuitry.Eachassertionaddsonebitoflatencytothereceivedbitstream.

Asynchronous,active-highsignalpreventstheDPAcircuitryfromswitchingtoanewclockphaseonthetargetchannel.Whenheldhigh,theselectedchannel(s)holdtheircurrentphasesetting.Whenheldlow,theDPAblockonselectedchannel(s)monitorsthephaseoftheincomingdatastreamcontinuouslyandselectsanewclockphasewhenneeded.ApplicableinDPA-FIFOandsoft-CDRmodesonly.

Asynchronous,active-highresettoDPAblocks.Minimumpulsewidthisoneparallelclockperiod.ApplicableinDPA-FIFOandsoft-CDRmodesonly.

Asynchronous,active-highresettoFIFOblock.Minimumpulsewidthisoneparallelclockperiod.ApplicableinDPA-FIFOmodeonly.

rx_bitslip_ctrl

rx_dpa_hold

NInputControl

rx_dpa_reset

NInputReset

rx_fifo_reset

NInputReset

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Signals9

SignalName

rx_out

WidthDirectionTypeDescription

N*JOutputData

Receiverparalleldataoutput.Synchronoustorx_coreclockin(DPA-FIFOandnon-DPAmodes).Insoft-CDRmode,each

channelhasparalleldatasynchronoustoitsrx_divfwdclk.

Bitsliprolloversignal.Highwhenthenextassertionofrx_bitslip_ctrlresetstheserialbitlatencyto0.

CoreclockforRXinterfacesprovidedbythePLL.NotavailablewhenusinganexternalPLL.

Theperchannel,dividedclockwiththeidealDPAphase.Therecoveredslowclockforagivenchannel.Applicableinsoft-CDRmodeonly.Becauseeachchannelmayhaveadifferentidealsamplingphase,therx_divfwdclksmaynotbeedge-alignedwitheachother.Eachrx_divfwdclkmustdrivethecorelogicwithdatafromthesamechannel.

AssertedwhentheDPAblockselectstheidealphase.TheAlteraLVDSSERDESIPcoredrivestherx_dpa_lockedport.TheDPAlogicassertstherx_dpa_lockedsignalwhenthesignalsettlesonanidealphaseforthatgivenchannel.Therx_dpa_lockedportwillde-assertiftheDPAmovestwophasesinthesamedirectionoriftheDPAmovesonephase.Therx_dpa_lockedsignalwillstilltogglewhentherx_dpa_holdsignalis

asserted,andshouldbeignoredbyuserlogicwhentherx_dpa_holdsignalisasserted.ApplicableinDPA-FIFOandsoft-CDRmodesonly.

rx_bitslip_max

NOutputControl

rx_coreclock

1OutputClock

rx_divfwdclk

NOutputClock

rx_dpa_locked

NOutputControl

Table4:TXSignals

SignalName

tx_intx_outtx_outclock

WidthDirectionTypeDescription

N*JN1

InputOutputOutput

DataDataClock

Paralleldatafromthecore.LVDSserialoutputdata.

Externalreferenceclock(sentoffchipviatheTXdatapath).Source-synchronouswithtx_out.

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SignalName

tx_coreclock

WidthDirectionTypeDescription

1OutputClock

Theclockthatdrivesthecorelogicfeedingtheserializer.NotavailableintheexternalPLLmode.

Table5:ExternalPLLSignals

Forinstructionsonsettingthefrequencies,dutycycles,andphaseshiftsoftherequiredPLLclocksforexternalPLLmode,refertotheClockResourceSummarytabintheIPParameterEditor.

SignalName

ext_fclk

WidthDirectionTypeDescription

1InputClock

LVDSfastclock.Usedforserialdatatransfer.Requiredinallmodes.Youmustconnectthissignaltothelvds_clk[0]portofthePLL.Thissignalisconfiguredasoutclock[0]fromthePLL.UseEnableaccesstoPLLLVDS_CLK/LOADENoutputportintheIOPLLgeneration.

LVDSloadenable.Usedforparallelload.NotrequiredinRXSoft-CDRmode.Youmustconnectthissignaltotheloaden[0]portofthePLL.Thissignalisconfiguredas

outclock[1]fromthePLL.UseEnableaccesstoPLLLVDS_CLK/LOADENoutputportintheIOPLLgeneration.

Theclockthatdrivesthecorelogicfeedingtheserializer(TX)/receivingfromthedeserializer(RX).ThissignalisstillpresentinRXsoft-CDRmode,eventhoughtheRXcoreregistersareclockedusingtherx_divfwdclk.RequiredforRXDPA-FIFOandRXSoft-CDRmodesonly.ProvidestheVCOclockstotheDPAcircuitryforoptimalphaseselection.Youmustconnectthissignaltothephout[7:0]signalfromthePLL.UseEnableaccesstoPLLDPAoutputportinIOPLLgeneration.PLLlocksignal.RequiredforRXDPA-FIFOandRXSoft-CDRmodesonly.

Phase-shiftedversionoffastclockrequiredforTXoutclockphaseshiftsthatarenotmultiplesof180degrees.

Phase-shiftedversionofloadenrequiredforTXoutclockphaseshiftsthatarenotmultiplesof180degrees.

ext_loaden

1InputClock

ext_coreclock

1InputClock

ext_vcoph[7:0]

InputClock

ext_pll_locked

11

InputInput

DataClock

ext_tx_outclock_fclk

ext_tx_outclock_loaden

1InputClock

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ParameterSettings11

ParameterSettings

YoucanparameterizetheAlteraLVDSSERDESIPcoreusingtheIPParameterEditor.

GeneralSettingsTab

Parameter

Value

Description

Functionalmode

????TX

RXNon-DPARXDPA-FIFORXSoft-CDR

Specifiesthefunctionalmodeoftheinterface.

Numberofchannels

?1to72forTXSpecifiesthenumberofserialchannelsinthe?1to24forRXNon-interface.DPA?Decrementonechannelforthededicated?1to24forRXDPA-referenceclockpin(refclk)forTX,RX

FIFONon-DPA,andRXDPA.Notusingthe?1to12forRXSoft-dedicatedreferenceclockpinmay

CDRcontributetohigherjitter.

?DecreasebyonechannelfortheTXoutclockpin(tx_outclock)ifused.

150.0to1600.0

Specifiesthedatarate(inMbps)ofasingleserialchannel.ThevalueisdependentontheFunctionalmodeparametersettings.

Datarate

SERDESfactorUseclock-pindrive

3,4,5,6,7,8,9,and10Specifiestheserializationrateordeserializa-tionratefortheLVDSinterface.

Whenenabled,theIPcorebypassesthePLLandtheinterfaceisdrivenwithaclockpin.

—

Note:Thisfeatureisnotsupportedin

thecurrentversionoftheQuartusIIsoftware.Whenenabled,theIPcoreuseslegacytop-levelnamesthatarecompatiblewith

ALTLVDS_TXandALTLVDS_RXIPcores.

Usebackwards-compatibleportnames

—

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PLLSettingsTab

Parameter

Value

Description

UseexternalPLL

—

Whenenabled,theIPcoredoesnotinstantiateaPLLlocally.Instead,aseriesofclockconnectionsareelaboratedwiththeprefix\thatshouldbeconnectedtoanexternallygeneratedPLL.ThisoptionallowsyoutoaccessalloftheavailableclocksfromthePLL,aswellasuseadvancedPLLfeaturessuchasclockswitchover,bandwidthpresets,dynamicphasestepping,anddynamicreconfiguration.

TheClockResourceSummarytabguidesyoutoconfigureyourexternalPLL.

DesiredinclockfrequencyActualinclockfrequencyFPGA/PLLspeedgradeEnablepll_aresetport

————

SpecifiestheinclockfrequencyinMHzSpecifiestheclosestinclockfrequencytothedesiredfrequencythatcansourcetheinterface.SpecifiestheFPGA/PLLspeedgradewhichdeterminestheoperationrangeofthePLL.Whenenabled,thisparameterexposesthepll_aresetport,whichyoucanusetoresettheentireLVDSinterface.

SpecifieswhichclocknetworktheAlteraLVDSSERDESIPcoreshouldexportaninternallygeneratedcoreclockonto.

Note:Thisfeatureisnotsupportedinthe

currentversionoftheQuartusIIsoftware.However,thiscanbemanuallyaddedusingQSFassignments.

Coreclockresourcetype—

ReceiverSettingsTab

Parameter

Value

Description

BitslipSettingsEnablebitslipmode

—

Whenenabled,thisparameteraddsabitslipblocktothedatapathofthereceiverandexposestherx_bitslip_ctrlport(oneinputperchannel).Everyassertionoftherx_bitslip_ctrlsignaladdsonebitofseriallatencytothedatapathofthespecifiedchannel.

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ReceiverSettingsTab13

ParameterValueDescription

Enablerx_bitslip_resetport—

Whenenabled,thisparameterexposestherx_bitslip_resetport(oneinputperchannel),whichyoucanusetoresetthebitslip.

Whenenabled,thisparameterexposestherx_bitslip_maxport(oneoutputperchannel).Whenasserted,thenextrisingedgeofrx_bitslip_ctrlresetsthelatencyofthebitsliptozero.

Enablerx_bitslip_maxport—

Bitsliprollovervalue

3,4,5,6,7,8,9,Setsthemaximumlatencythatcanbeinjectedusing

10,11bitslip.Whenitreachesthatvalue,itrollsoverand

therx_bitslip_maxsignalisasserted.Thedefaultvalueis10.

Note:Alterarecommendssettingthis

parametertoavalueequaltoorgreaterthanthedeserializationfactor.

DPASettings

Enablerx_dpa_resetport

—

Whenenabled,theIPcoreexposestherx_dpa_reset port,whichyoucanusetoresettheDPAlogicofeachchannelindependently.Formerlyknownasrx_reset.

Whenenabled,userlogicdrivestherx_fifo_resetportwhichyoucanusetoresettheDPA-FIFOblock.

Whenenabled,theIPcoreexposestherx_dpa_holdinputport(oneinputperchannel).Whensethigh,theDPAlogicinthecorrespondingchanneldoesnotswitchsamplingphases.Therx_dpa_holdportisformerlyknownasrx_dpll_holdport.

Enablerx_fifo_resetport—

Enablerx_dpa_holdport—

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ParameterValueDescription

EnableDPAlossoflockononechange

—

Whenenabled,theAlteraLVDSSERDESIPcoredrivestherx_dpa_lockedsignallowwhentheDPAchangesphaseselectionfromtheinitiallylockedposition.TheAlteraLVDSSERDESIPcoredrivestherx_dpa_lockedsignalhighiftheDPAchangesthephaseselectionbacktotheinitiallockedposition.

Whendisabled,theAlteraLVDSSERDESIPcoredrivestherx_dpa_lockedsignallowwhentheDPAmovestwophasesinthesamedirectionawayfromtheinitiallockedposition.TheAlteraLVDS

SERDESIPcoredrivestherx_dpa_locked signalhighiftheDPAchangesthephaseselectiontobewithinonephaseorsamephaseastheinitiallockedposition.

Ade-assertionofrx_dpa_lockeddoesnotindicatethedataisinvalid,itindicatestheDPAhaschangedphasetapstotrackvariationsbetweentheinclockandrx_indata.Alterarecommendsusingdatacheckerstoverifydataaccuracy.

EnableDPAalignmentonlytorisingedgesofdata

—

Whenenabled,DPAlogiccountstherisingedgesontheincomingserialdataonly.Whendisabled,DPAlogiccountstherisingandfallingedges.Note:Thisportisonlyrecommendedforuse

inhighjittersystems,andAlterarecommendsdisablingthisportintypicalapplications.

(Simulationonly)SpecifyPPMdriftontherecoveredclock(s)

—

SpecifiestheamountofphasedrifttheALTERA_LVDSsimulationmodelshouldaddtotherecoveredrx_divfwdclks.

Note:Thisfeatureisnotsupportedinthe

currentversionoftheQuartusIIsoftware.

Non-DPASettings

Desiredreceiverinclockphaseshift(degrees):

—

SpecifiestheidealphasedelayoftheinclockwithrespecttotransitionsintheincomingserialdataindegreesoftheLVDSfastclock.Forexample,

specifying180degreesimpliestheinclockiscenteralignedwiththeincomingdata.

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TransmitterSettingsTab15

ParameterValueDescription

ActualreceiverinclockphaseshiftLegalvaluesareSpecifiestheclosestachievablereceiverinclock(degrees)dependentonthephaseshifttothedesiredreceiverinclockphase

fclkandinclockshift.frequencies.RefertoSettingtheReceiverInputClockParametersonpage16.

TransmitterSettingsTab

Parameter

Value

Description

TXcoreregistersclock

Allowsyoutoeitherclockthecoreregisterswiththetx_coreclockorthePLLrefclk.Ifyouselect

tx_coreclockorinclock,therefclkfrequencymustbeequaltothe

dataratedividedbytheserializationfactor.inclock

ThisparameterisavailableinTXfunctionalmodeonly.

—

Whenenabled,theIPcoreexposesthetx_

coreclockportwhichyoucanusetodrivethecorelogicfeedingthetransmitter.

Whenenabled,theIPcoreexposesthetx_

outclockport.Thefrequencyofthetx_outclockportisdependentonthesettingforthetx_outclockdivisionfactorparameter.Thephaseofthetx_outclockportisdependentontheDesiredtx_outclockphaseshiftparameter.Thisparametertakesupanadditionalchannel,whichreducesthemaxnumberofchannelsperTXinterfaceby1AllowsyoutospecifythephaserelationshipbetweentheoutclockandoutgoingserialdataindegreesoftheLVDSfastclock.

Enabletx_coreclockport

Enabletx_outclockport

—

Desiredtx_outclockphaseshift(degrees)

RefertotheSettingtheTransmitterOutputClockParametersonpage17.

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ParameterValueDescriptionActualtx_outclockphaseshift(degrees)

LegalvaluesareSpecifiestheclosestachievabletx_outclockphasedependentontheshifttothedesiredtx_outclockphaseshift.fclkandtx_outclock

frequencies.RefertoSettingtheTransmitterOutputClockParametersonpage17.Legalvaluesaredependentontheserializationfactor.

Allowsyoutospecifytheratioofthefastclockfrequencytotheoutclockfrequency(forexample,themaximumnumberofserialtransitionsperoutclockcycle).

Tx_outclockdivisionfactor

ClockResourceSummaryTab

Thistabintheparametereditorlistsoutalltherequiredfrequencies,phaseshifts,anddutycyclesoftherequiredclocks,includinginstructionsontherequiredconnections.ThistabalsoshowshowtoconfigureandconnectanexternalPLL.

SettingtheReceiverInputClockParameters

Whenusingnon-DPAmode,ifyouwanttheSERDESreceivertosamplethesourcesynchronousdata,youmustspecifytheinclockrelationshiptotherx_indata.Todoso,typeavalueintheDesiredreceiverinclockphaseshift(degrees)parameter.Legalvaluesareevenlydivisibleby45.Ifyouenteranillegalvalue,theactualphaseshiftwillappearinActualreceiverinclockphaseshift(degrees).

Forrisinginclockedgealignedinterfacestotherx_indata(Figure4),select0°asthedesiredreceiverclockphaseshift.ThePLLwillbesetwiththerequiredphaseshiftonfclktocenteritattheSERDESreceiver.Figure4:0°EdgeAlignedinclockx8DeserializerWaveformWithSingleRateClock

Thephaseshiftyouspecifywillberelativetothefclkwhichoperatesattheserialdatarate.Phaseshiftvaluesbetween0°and360°areusedtospecifytherisingedgeoftheinclockwithinasinglebitperiod.Themaximumphaseshiftvalueisdeterminedbythefollowingequation:(Numberoffclkperiodsperinclockperiodx360)-1

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SettingtheTransmitterOutputClockParameters17

Specifyingphaseshiftvaluesgreaterthan360°willchangetheMSBlocationwithintheparalleldata.Note:Bydefault,theMSBfromtheserialdatawillnotbetheMSBontheparalleldata.Youcanusebitslip

tosettheproperwordboundaryontheparalleldata.RefertoAligningtheWordBoundariesformoredetails.Tospecifyacenteralignedinclocktorx_inrelationship(Figure5),enteraphaseshiftvalueof180°fortheDesiredreceiverinclockphaseshift(degrees)parameter.

Figure5:180°CenterAlignedinclockx8DeserializerWaveformWithSingleRateClock

Thephaseshiftvalueyouentertospecifytheinclocktorx_inrelationshipisindependentoftheinclockfrequency.TospecifyacenteralignedDDRinclocktorx_inrelationship(Figure6),enteraphaseshiftvalueof180°fortheDesiredreceiverinclockphaseshift(degrees)parameter.Figure6:180°CenterAlignedinclockx8DeserializerWaveformWithDDRClock

SettingtheTransmitterOutputClockParameters

Thetx_outclockrelationshiptothetx_outdataisspecifiedwithtwoparameters:?Desiredtx_outclockphaseshift(degrees)?Tx_outclockdivisionfactor

Theseparameterssetthephaseandfrequencyofthetx_outclockbasedonthefclkwhichoperatesattheserialdatarate.Youcanspecifythedesiredtx_outclockphaseshiftrelativetothetx_outdataat45°incrementsofthefclk.Youcansetthetx_outclockfrequencyusingtheavailabledivisionfactorsfromthedrop-downlist.

Use0°tospecifythetx_outclockphasetoberisingedgealignedtotheMSBoftheserialdataontx_out(Figure7).

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Figure7:0°EdgeAlignedtx_outclockx8SerializerWaveformwithDivisionFactorof8

Use180°tospecifythetx_outclockphasetocenteralignedtotheMSBoftheserialdataontx_out (Figure8).

Figure8:180°CenterAlignedtx_outclockx8SerializerWaveformwithDivisionFactorof8

Phaseshiftvaluesof0°through315°willpositiontherisingedgeofthetx_outclockwithintheMSBofthetx_outdata.Phaseshiftvaluesbeginningwith360°willpositiontherisingedgeofthetx_outclockinserialbitsaftertheMSB.Forexample,aphaseshiftof540°willpositiontherisingedgeinthecenterofthebitaftertheMSB(Figure9).

Figure9:540°CenterAlignedtx_outclockx8SerializerWaveformwithDivisionFactorof8

UsetheTx_outclockdivisionfactordrop-downlisttosetthetx_outclockfrequency.Figure10showsax8serializationfactorusinga180°phaseshiftwithatx_outclockdivisionfactorof2(DDRclockanddatarelationship).

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Timing19

Figure10:180°CenterAlignedtx_outclockx8SerializerWaveformwithDivisionFactorof2

Timing

ToproperlyperformtiminganalysisontheAlteraLVDSSERDESIPcoreonArria10devices,theQuartusIIsoftwareversion14.0a10generatestherequiredtimingconstraints.

TimingComponents

Table6:TimingComponents

ThistableliststhetimingcomponentsfortheAlteraLVDSSERDESIPcore.

TimingComponent

Description

SourceSynchronousPaths

Thesourcesynchronouspathsarepathswhereclockanddatasignalsarepassedfromthetransmittingdevicestothereceivingdevices.Forexample:

?FPGA/LVDS/TXtoexternalreceivingdevicetransmittingpath?ExternaltransmittingdevicetoFPGA/non-DPAmode/LVDS/RXreceivingpath

DynamicPhaseAlignmentPaths

TheI/Ocapturepathsinsoft-CDRandDPA-FIFOmodesareregisteredbyaDPAblock,whichdynamicallychoosesthebestphasefromthePLLVCOclockstolatchtheinputdata.

TheinternalFPGApathsarethepathsinsidetheFPGAfabric.ThisincludestheLVDSRXhardwaretocoreregisterspaths,coreregisterstoLVDSTXhardwarepathsandotherscoreregisterstocoreregisterspath.TheTimeQuestTimingAnalyzerreportsthecorrespondingtimingmargins.

InternalFPGAPaths

TimingConstraintsandFiles

ToenableyoutoperformtiminganalysisontheAlteraLVDSSERDESIPcoresuccessfully,theIPcoregeneratesthefollowingtimingfiles,whichyoucanlocateinthedirectory.

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Table7:TimingFiles

File

Description

_altera_lvds_core20_140_This.sdcallowstheFittertooptimizetiming.sdcmarginswithtimingdrivencompilation.Also

allowstheTimeQuesttiminganalyzertoanalyzethetimingofyourdesign.

TheIPcoreusesthe.sdcforthefollowingoperations:????

CreatingclocksonPLLinputsCreatinggeneratedclocks

Callingderive_clock_uncertaintyCreatingpropermulti-cycleconstraints

Youcanlocatethisfileinthe.qipgeneratedduringtheIPgeneration.

sdc_util.tcl

This.tclfileisalibraryoffunctionsandproceduresthatthe.sdcuses.

TimingAnalysis

TimingAnalysisatI/O

ThissectiondescribesthetiminganalysisattheI/Ointerfacingexternaldevices.SoftCDRModeandDPA-FIFOModeRX

InsoftCDRandDPA-FIFOmode,thereceivingdataiscaptureddynamicallybytheDPAhardware.Asaresult,theTimeQuestTimingAnalyzerdoesnotperformstatictiminganalysisattheI/O.Non-DPAModeRXandReceiverSkewMargin(RSKM)

Changesinthesystemenvironment,suchastemperature,media(cable,connector,orPCB),andloading,affectthereceiver'ssetupandholdtimes;internalskewaffectsthesamplingabilityofthereceiver.Innon-DPAmode,usereceiverskewmargin(RSKM),receiverchannel-to-channelskew(RCCS),andsamplingwindow(SW)specificationstoanalyzethetimingforhigh-speedsource-synchronousdifferentialsignalsinthereceiverdatapath.ThefollowingequationshowstherelationshipbetweenRSKM,RCCS,andSW.Figure11:RSKM

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