FPGA可编程逻辑器件芯片EP2SGX125GF1508C5N中文规格书

I/O Structure

Figure2–54.Stratix II IOE in DDR Output I/O Configuration Notes(1), (2)

Notes to Figure2–54:

(1)All input signals to the IOE can be inverted at the IOE.

(2)The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an

inverter at the OE register data port. Similarly, the aclr and apreset signals are also active-high at the input ports of the DDIO megafunction.

(3)The optional PCI clamp is only available on column I/O pins.

Stratix II Device Handbook, Volume 1

Stratix II Architecture Figure2–55.Output TIming Diagram in DDR Mode

The Stratix II IOE operates in bidirectional DDR mode by combining the

DDR input and DDR output configurations. The negative-edge-clocked

OE register holds the OE signal inactive until the falling edge of the clock.

This is done to meet DDR SDRAM timing requirements.

External RAM Interfacing

In addition to the six I/O registers in each IOE, Stratix II devices also have

dedicated phase-shift circuitry for interfacing with external memory

interfaces. Stratix II devices support DDR and DDR2 SDRAM, QDR II

SRAM, RLDRAM II, and SDR SDRAM memory interfaces. In every

Stratix II device, the I/O banks at the top (banks 3 and 4) and bottom

(banks 7 and 8) of the device support DQ and DQS signals with DQ bus

modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table2–14 shows the number

of DQ and DQS buses that are supported per device.

Table2–14.DQS & DQ Bus Mode Support(Part 1 of2)Note(1)

Device Package Number of

×4Groups

Number of

×8/×9 Groups

Number of

×16/×18 Groups

Number of

×32/×36 Groups

EP2S15484-pin FineLine BGA8400 672-pin FineLine BGA18840

EP2S30484-pin FineLine BGA8400 672-pin FineLine BGA18840

EP2S60484-pin FineLine BGA8400 672-pin FineLine BGA18840

1,020-pin FineLine BGA361884

Stratix II Device Handbook, Volume 1

Stratix II Architecture f For more information on tolerance specifications for on-chip termination

with calibration, refer to the DC & Switching Characteristics chapter in

volume 1 of the Stratix II Device Handbook.

On-Chip Parallel Termination with Calibration

Stratix II devices support on-chip parallel termination with calibration for

column I/O pins only. There is one calibration circuit for the top I/O

banks and one circuit for the bottom I/O banks. Each on-chip parallel

termination calibration circuit compares the total impedance of each I/O

buffer to the external 50-Ω resistors connected to the RUP and RDN pins

and dynamically enables or disables the transistors until they match.

Calibration occurs at the end of device configuration. Once the calibration

circuit finds the correct impedance, it powers down and stops changing

the characteristics of the drivers.

1On-chip parallel termination with calibration is only supported for input pins.

f For more information on on-chip termination supported by Stratix II

devices, refer to the Selectable I/O Standards in Stratix II & Stratix II GX

Devices chapter in volume 2 of the Stratix II Device Handbook or the

Stratix II GX Device Handbook.

f For more information on tolerance specifications for on-chip termination

with calibration, refer to the DC & Switching Characteristics chapter in

volume 1 of the Stratix II Device Handbook.

MultiVolt I/O Interface

The Stratix II architecture supports the MultiVolt I/O interface feature

that allows Stratix II devices in all packages to interface with systems of

different supply voltages.

The Stratix II VCCINT pins must always be connected to a 1.2-V power

supply. With a 1.2-V V CCINT level, input pins are 1.5-, 1.8-, 2.5-, and3.3-V

tolerant. The VCCIO pins can be connected to either a 1.5-, 1.8-, 2.5-, or

3.3-V power supply, depending on the output requirements. The output

levels are compatible with systems of the same voltage as the power

supply (for example, when VCCIO pins are connected to a 1.5-V power

supply, the output levels are compatible with 1.5-V systems).

The Stratix II VCCPD power pins must be connected to a 3.3-V power

supply. These power pins are used to supply the pre-driver power to the

output buffers, which increases the performance of the output pins. The

VCCPD pins also power configuration input pins and JTAG input pins.

Stratix II Device Handbook, Volume 1

Document Revision History

Stratix II Device Handbook, Volume 1

Document Revision History

Stratix II Device Handbook, Volume 1

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