AT24C164-10PU-2.7中文资料

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Features

Low Voltage and Standard Voltage Operation–2.7 (V–1.8 (VCC = 2.7V to 5.5V) = 1.8V to 5.5V)

Internally Organized 2048 x 8 (16K)CC Two-Wire Serial Interface

Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol

100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility Write Protect Pin for Hardware Data Protection Cascadable Feature Allows for Extended Densities 16-Byte Page Write Mode

Partial Page Writes Are Allowed Self-Timed Write Cycle (10 ms max) High Reliability

–Endurance: 1 Million Write Cycles–Data Retention: 100 Years

Automotive Grade, Extended Temperature and Lead-free/Halogen-free Devices Available

8-lead PDIP and 8-lead JEDEC SOIC Packages

Die Sales: Wafer Form, Waffle Pack and Bumped Wafers

Description

The AT24C164 provides 16,384 bits of serial electrically erasable and programmableread only memory (EEPROM) organized as 2048 words of 8 bits each. The device’scascadable feature allows up to eight devices to share a common two-wire bus. Thedevice is optimized for use in many industrial and commercial applications where lowpower and low voltage operation are essential. The AT24C164 is available in spacesaving 8-lead PDIP and 8-lead JEDEC SOIC packages and is accessed via a two-wire serial interface. In addition, this device is available in 2.7V (2.7V to 5.5V) and1.8V (1.8V to 5.5V) versions.Table 1. Pin Configurations

8-lead SOIC

Pin NameFunctionA0 - A2Address InputsSDASerial DataSCLSerial Clock InputWP

Write Protect

8-lead PDIP1

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Absolute Maximum Ratings*

Operating Temperature..................................–55°C to +125°CStorage Temperature.....................................–65°C to +150°CVoltage on Any Pin

with Respect to Ground....................................–1.0V to +7.0VMaximum Operating Voltage..........................................6.25VDC Output Current........................................................

5.0 mA

*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 1. Block Diagram

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Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into eachEEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin isopen-drain driven and may be wire-ORed with any number of other open-drain or opencollector devices.

DEVICE SELECT (A2, A1, A0): The A2, A1 and A0 pins are device address inputs thatmay be hardwired or actively driven to VDD or VSS. These inputs allow the selection forone of eight possible devices sharing a common bus. The AT24C164 can be madecompatible with the AT24C16 by tying A2, A1 and A0 to VSS. Device addressing is dis-cussed in detail in the device addressing section.

WRITE PROTECT (WP): The write protect input, when tied low to GND, allows normalwrite operations. When WP is tied to VCC, all write operations are inhibited.

Memory Organization

The AT24C164 is internally organized with 256 pages of 8 bytes each. Random wordaddressing requires an 11 bit data word address.

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Table 2. Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.

SymbolCI/OCINNote:

Test Condition

Input/Output Capacitance (SDA)Input Capacitance (A0, A1, A2, SCL)

1.This parameter is characterized and is not 100% tested.

Max86

UnitspFpF

ConditionsVI/O = 0VVIN = 0V

Table 3. DC Characteristics

Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,VCC = +1.8V to +5.5V (unless otherwise noted).

SymbolVCC1VCC2VCC3VCC4ICCICCISB1ISB2ISB3ISB4ILIILOVIL(1)VIH(1)VOL2VOL1Note:

ParameterSupply VoltageSupply VoltageSupply VoltageSupply Voltage

Standby Current VCC = 5.0VStandby Current VCC = 5.0VStandby Current VCC = 1.8VStandby Current VCC = 2.5VStandby Current VCC = 2.7VStandby Current VCC = 5.0VInput Leakage CurrentOutput Leakage CurrentInput Low LevelInput High Level

Output Low Level VCC = 3.0VOutput Low Level VCC = 1.8V

IOL = 2.1 mAIOL = 0.15 mAREAD at 100 kHzWRITE at 100 kHzVIN = VCC or VSSVIN = VCC or VSSVIN = VCC or VSSVIN = VCC or VSSVIN = VCC or VSSVOUT = VCC or VSS

–0.6VCC x 0.7

Test Condition

Min1.82.52.74.5

0.42.00.61.41.68.00.100.05Typ

Max5.55.55.55.51.03.03.04.04.018.03.03.0VCC x 0.3VCC + 0.50.40.2

UnitsVVVVmAmAµAµAµAµAµAµAVVVV

1.VIL min and VIH max are reference only and are not tested.

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AT24C164

Table 4. AC Characteristics

Applicable over recommended operating range from TA = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and100pF (unless otherwise noted).

2.7-, 2.5-, 1.8-volt

SymbolfSCLtLOWtHIGHtItAAtBUFtHD.STAtSU.STAtHD.DATtSU.DATtRtFtSU.STOtDHtWR

Endurance(1)Note:

Parameter

Clock Frequency, SCLClock Pulse Width LowClock Pulse Width HighNoise Suppression Time(1)Clock Low to Data Out Valid

Time the bus must be free before a new transmission can start(1)

Start Hold TimeStart Set-up TimeData In Hold TimeData In Set-up TimeInputs Rise Time(1)Inputs Fall Time(1)Stop Set-up TimeData Out Hold TimeWrite Cycle Time 5.0V, 25°C, Page Mode

1M4.7100

10

1M

0.14.74.04.70200

1.0300

0.650

10

4.74.0

1004.5

0.11.20.60.60100

0.3300

Min

Max100

1.20.6

500.9

5.0-voltMin

Max400

UnitskHzµsµsnsµsµsµsµsµsnsµsnsµsnsmsWrite cycles

1.These parameters are characterized and is not 100% tested.

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Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (refer toData Validity timing diagram). Data changes during SCL high periods will indicate a startor stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start conditionwhich must precede any other command (see Figure 5 on page 8).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby powermode (see Figure 5 on page 8).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and fromthe EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it hasreceived each word. This happens during the ninth clock cycle.

STANDBY MODE: The AT24C164 features a low power standby mode which isenabled: a) upon power-up and b) after the receipt of the STOP bit and the completionof any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, theAT24C164 can be reset by following these steps:

(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then(c) create a start condition as SDA is high.

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Figure 2. Bus Timing

SCL: Serial Clock, SDA: Serial Data I/O

Figure 3. Write Cycle Timing

SCL: Serial Clock, SDA: Serial Data I/O

Note:

1.The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

Figure 4.

Data Validity

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Figure 5. Start and Stop Definition

Figure 6.

Output Acknowledge

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AT24C164

Device Addressing

The AT24C164 requires an 8-bit device address word following a start condition toenable the chip for read or write operations (see Figure 7 on page 10). The most signifi-cant bit must be a one followed by the A2, A1 and A0 device select bits (the A1 bit mustbe the compliment of the A1 input pin signal). The next 3 bits are used for memory blockaddressing and select one of the eight 256 x 8 memory blocks. These bits should beconsidered the three most significant bits of the data word address. The eighth bit of thedevice address is the read/write select bit. A read operation is selected if this bit is highor a write operation is selected if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare isnot made, the chip will return to a standby state.

Write Operations

BYTE WRITE: A write operation requires an 8-bit data word address following thedevice address word and acknowledgment. Upon receipt of this address, the EEPROMwill again respond with a zero and then clock in the first 8-bit data word. Followingreceipt of the 8-bit data word, the EEPROM will output a zero and the addressingdevice, such as a microcontroller, must terminate the write sequence with a stop condi-tion. At this time the EEPROM enters an internally-timed write cycle, tWR, to thenonvolatile memory. All inputs are disabled during this write cycle and the EEPROM willnot respond until the write is complete (see Figure 8 on page 11).

PAGE WRITE: The AT24C164 is capable of a 16-byte page write. A page write is initi-ated the same as a byte write, but the microcontroller does not send a stop conditionafter the first data word is clocked in. Instead, after the EEPROM acknowledges receiptof the first data word, the microcontroller can transmit up to fifteen more data words. TheEEPROM will respond with a zero after each data word received. The microcontrollermust terminate the page write sequence with a stop condition (see Figure 9 on page11).

The data word address lower 4 bits are internally incremented following the receipt ofeach data word. The higher data word address bits are not incremented retaining thememory page row location. When the word address, internally generated, reaches thepage boundary, the following byte is placed at the beginning of the same page. If morethan sixteen data words are transmitted to the EEPROM, the data word address will “rollover” and previous data will be overwritten.

ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and theEEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-ing a start condition followed by the device address word. The read/write bit isrepresentative of the operation desired. Only if the internal write cycle has completedwill the EEPROM respond with a zero allowing the read or write sequence to continue.

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Read Operations

Read operations are initiated the same way as write operations with the exception thatthe read/write select bit in the device address word is set to one. There are three readoperations: current address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains thelast address accessed during the last read or write operation, incremented by one. Thisaddress stays valid between operations as long as the chip power is maintained. Theaddress “roll over” during read is from the last byte of the last memory page to the firstbyte of the first page. The address “roll over” during write is from the last byte of the cur-rent page to first byte of the same page.

Once the device address with the read/write select bit set to one is clocked in andacknowledged by the EEPROM, the current address data word is serially clocked out.The microcontroller does not respond with an input zero but does generate a followingstop condition (see Figure 10 on page 11).

RANDOM READ: A random read requires a “dummy” byte write sequence to load in thedata word address. Once the device address word and data word address are clockedin and acknowledged by the EEPROM, the microcontroller must generate another startcondition. The microcontroller now initiates a current address read by sending a deviceaddress with the read/write select bit high. The EEPROM acknowledges the deviceaddress and serially clocks out the data word. The microcontroller does not respondwith a zero but does generate a following stop condition (see Figure 11 on page 11).SEQUENTIAL READ: Sequential reads are initiated by either a current address read ora random address read. After the microcontroller receives a data word, it responds withan acknowledge. As long as the EEPROM receives an acknowledge, it will continue toincrement the data word address and serially clock out sequential data words. When thememory address limit is reached, the data word address will “roll over” and the sequen-tial read will continue. The sequential read operation is terminated when themicrocontroller does not respond with a zero but does generate a following stop condi-tion (see Figure 12 on page 12).Figure 7.

Device Address

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Figure 8. Byte Write

Figure 9. Page Write

Figure 10. Current Address Read

Figure 11.

Random Read

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Figure 12.

Sequential Read

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AT24C164

Ordering Information(1)

Ordering CodeAT24C164-10PU-2.7(2)AT24C164-10PU-1.8(2)AT24C164-10SU-2.7(2)AT24C164-10SU-1.8(2)AT24C164-W2.7-11(3)AT24C164-W1.8-11(3)Notes:

Package8P38P38S18S1Die SaleDie Sale

Operation RangeLead-free/Halogen-freeIndustrial Temperature(–40°C to 85°C)Industrial Temperature(–40°C to 85°C)

1.Not recommended for new design; Please refer to AT24C16B datasheet. For 2.7V devices used in the 4.5V to 5.5V range,

please refer to performance values in the AC and DC characteristics tables.2.“U” designates Green package + RoHS compliant.

3.Available in waffle pack and wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing.

Package Type

8P38S1

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)

Options

–2.7–1.8

Low-Voltage (2.7V to 5.5V)Low-Voltage (1.8V to 5.5V)

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Packaging Information

8P3 – PDIP

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AT24C164

8S1 – JEDEC SOIC

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Revision History

Doc. Rev.0105J

Comments

Added note to 1st page; ‘Not recommended for new design; please refer to AT24C16B datasheet. For cascadability features of the AT24C164 (A0-A2), please move to the AT24C32C device which allows up to eight devices that may be addressed on a single bus system.’

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