实验四、在 Verilog HDL 中使用函数

实验四、在 Verilog HDL 中使用函数

一：函数源代码：

module tryfunct(clk, n, result, reset);

output[31:0] result;

input[3:0] n;

input reset, clk;

reg[31:0] result;

always @(posedge clk)

begin

if(!reset)

result=0;

else

begin

result=n*factorial(n)/((n*2)+1);

end

end

function[31:0] factorial;

input[3:0] operand;

reg[3:0] index;

begin

factorial=operand?1:0;

for(index=2; index<=operand; index=index+1)

factorial=index*factorial;

end

endfunction

endmodule

二：函数的测试代码：

`timescale 1ns/100ps

`include "tryfunct.v"

`define clk_cycle 5

module tryfunct_test;

reg[3:0] n,i;

reg reset, clk;

wire[31:0] result;

initial

begin

clk=0;

n=0;

reset=1;

#10 reset=0;

#10 reset=1;

for(i=0; i<=15; i=i+1)

begin

#20 n=i;

end

#10 $stop;

end

always #`clk_cycle clk=~clk;

tryfunct mod1( .clk(clk), .n(n),.result(result), .reset(reset) );

initial $monitor($time,,,"n=%d, reset=%b, result=%d", n, reset, result);

endmodule

三：Transcript显示结果：

Loading work.tryfunct_test

# Loading work.tryfunct

# ** Warning: (vsim-3009) [TSCALE] - Module 'tryfunct' does not have a `timescale directive in effect, but previous modules do.

# Region: /tryfunct_test/mod1

# WARNING: No extended dataflow License exists

add wave sim:/tryfunct_test/*

run

# 0 n= 0, reset=1, result= x

run

run

run

run -continue

run

run -continue

run

run -continue

add wave -r /*

run

run -continue

run -all

# 5 n= 0, reset=1, result= 0

# 10 n= 0, reset=0, result= 0

# 20 n= 0, reset=1, result= 0

# 60 n= 1, reset=1, result= 0

# 80 n= 2, reset=1, result= 0

# 100 n= 3, reset=1, result= 0

# 105 n= 3, reset=1, result= 2

# 120 n= 4, reset=1, result= 2

# 125 n= 4, reset=1, result= 10

# 140 n= 5, reset=1, result= 10

# 145 n= 5, reset=1, result= 54

# 160 n= 6, reset=1, result= 54

# 165 n= 6, reset=1, result= 332

# 180 n= 7, reset=1, result= 332

# 185 n= 7, reset=1, result= 2352 # 200 n= 8, reset=1, result= 2352 # 205 n= 8, reset=1, result= 18974 # 220 n= 9, reset=1, result= 18974 # 225 n= 9, reset=1, result= 171890 # 240 n=10, reset=1, result= 171890 # 245 n=10, reset=1, result= 1728000 # 260 n=11, reset=1, result= 1728000 # 265 n=11, reset=1, result= 19090643 # 280 n=12, reset=1, result= 19090643 # 285 n=12, reset=1, result= 58122076 # 300 n=13, reset=1, result= 58122076 # 305 n=13, reset=1, result= 134883669 # 320 n=14, reset=1, result= 134883669 # 325 n=14, reset=1, result= 25012577 # 340 n=15, reset=1, result= 25012577 add wave sim:/tryfunct_test/*

add wave sim:/tryfunct_test/*

# Compile of tryfunct_test.v was successful.

# Compile of tryfunct.v was successful.

# 2 compiles, 0 failed with no errors.

add wave sim:/tryfunct_test/*

四：测试波形如下图所示：

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