Tektronix_Fundamentals_of_Signal_Integrity泰克信号完整性基础

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Table of Content s

Signal Integrity Described . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Digital Technology and the Information Age . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Rising Bandwidth Challenges Digital Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 - 4Review of Signal Integrity Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 8Problem s Created by Digital Timing I ss ue s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5I s olating Analog Deviation s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Eye Diagram s : A S hortcut for Quic k ly Detecting S ignal Integrity Problem s . . . . . . . . . . . . . . . . . . . .8Signal Integrity Measurement Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 25Di s covering Digital Fault s U s ing Logic Analy z er s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Logic Analy z er Probing S olution s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Uncovering Analog Diviation s with Digital O s cillo s cope s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12O s cillo s cope Probing S olution s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Revealing the Frequency Domain with Real-Time S pectrum Analy z er s . . . . . . . . . . . . . . . . . . . . . .17Identify S ignal Integrity Problem s with Integrated Mea s urement Tool s . . . . . . . . . . . . . . . . . . . . . . .19S implifying Complex Mea s urement s with Jitter Analy s i s Tool s . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Providing Critical Impedance Mea s urement s with Time Domain Reflectometry S olution s . . . . . . . . .22S ignal Generator s Complete the Mea s urement S y s tem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Fundamental s of S ignal Integrity e31a51f52af90242a895e5e8/signal_integrity S ignal Integrity De s cribed

By definition, “integrityó mean s “complete and unimpaired.”Li k ewi s e, a digital s ignal with good integrity ha s clean, fa s t tran s ition s ; s table and valid logic level s ; accurate placement in time and it would be free of any tran s ient s .

Evolving technology ma k e s it increa s ingly difficult for s y s tem developer s to produce and maintain complete, unimpaired s ignal s in digital s y s tem s . The purpo s e of thi s primer i s to provide s ome in s ight into s ignal integrity-related problem s in digital s y s tem s , and to de s cribe their cau s e s , characteri s tic s , effect s , and s olution s .Digital Technology and the

Information Age

It ’s been over twenty year s s ince the per s onal computer emerged and almo s t a s long s ince cellular telephony went from being a novelty to a con s umer nece ss ity. For both, one trend ha s remained con s tant: the demand for more feature s and s ervice s , and the need for more bandwidth to deliver them. Fir s t-generation PC u s er s were excited about the power of creating a s imple s pread s heet. Now they demand detailed graphic s , high-quality audio, and fa s t-s treaming video. And, cell phone s are hardly a tool anymore for ju s t conver s ation.

Our much-s maller world now depend s on increa s ingly more content and it s rapid, reliable delivery. The term “Information Age ” wa s coined to de s cribe thi s new interwoven, interde-pendent, data-ba s ed culture.

With the Information Age ha s come a s teady s tream of technology brea k through s in the field s of s emiconductor s , PC bu s architecture s , networ k infra s tructure s , and digital wirele ss communication s . In PC s — and e s pecially in s erver s — proce ss or s peed s have e s calated into the multi-GH z range, and memory throughput and internal bu s s peed s have ri s en right along with them.The s e dramatically increa s ed rate s s upport computer application s s uch a s 3D game s and computer-aided de s ign program s . S ophi s ticated 3D imagery require s a huge amount of bandwidth at the circuit board level, where the CPU, the graphic s s ub s y s tem, and the memory ha s to move data,con s tantly, a s the image move s .Computer s are ju s t one facet of the bandwidth-hungry Information Age. Digital communication equipment de s igner s (and particularly tho s e developing the electrical and optical infra s tructure element s for both mobile and fixed networ ks )are moving toward 40 Gb/s data rate s . And digital video product development team s are de s igning a new generation of tran s mi ss ion equipment for high-definition, interactive video.Numerou s technologie s are pu s hing the s e data rate advancement s . S erial bu s e s are emerging to brea k the s peed barrier s inherent in older, parallel bu s architecture s . In s ome ca s e s , s y s tem cloc ks are intentionally dithered to reduce unintended radiated emi ss ion s . And s maller, den s er circuit board s u s ing ball grid array IC s and buried via s have become common a s developer s loo k for way s to maximi z e den s ity and minimi z e path length s .Ri s ing Bandwidth Challenge s Digital De s ign Today ’s digital bandwidth race require s innovative thin k ing.Bu s cycle time s are now up to a thou s and time s fa s ter than they were twenty year s ago. Tran s action s that once too k micro s econd s are now mea s ured in nano s econd s . To achieve thi s improvement, edge s peed s today are now a hundred time s fa s ter than before.Circuit board technology, however, ha s not k ept pace becau s e of certain phy s ical realitie s . The propagation time of inter-chip bu s e s ha s remained virtually unchanged. Although geometrie s have s hrun k , circuit board s s till need s ufficient s pace for IC device s , connector s , pa ss ive component s , and

of cour s e, the bu s trace s them s elve s . Thi s s pace equate s to di s tance, and di s tance mean s delay— the enemy of s

peed.

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It ’s important to remember that the edge s peed – or ri s e time – of a digital s ignal can carry much higher frequency component s than it s repetition rate might imply. It ’s actually the higher frequency component s that create the de s ired fa s t tran s ition s in a digital s ignal. With today ’s high-s peed s erial bu s e s , there i s often s ignificant energy at the 5th harmonic of the cloc k rate.

A s a re s ult, circuit board trace s ju s t s ix inche s long become tran s mi ss ion line s when driven with s ignal s exhibiting edge rate s below four to s ix nano s econd s . Circuit board trace s are no longer s imple conductor s . At lower frequencie s , a trace exhibit s mo s tly re s i s tive characteri s tic s . A s frequencie s increa s e, a trace begin s to act li k e a capacitor. At the highe s t frequencie s , a trace ’s inductance play s a larger role.S ignal integrity problem s increa s e at higher frequencie s .Tran s mi ss ion line effect s are critical. Impedance di s continu-itie s along the s ignal path create reflection s , which degrade s ignal edge s . Cro ss tal k increa s e s . Power s upply decoupling become s far le ss effective, a s ground plane s and power plane s become inductive and act li k e tran s mi ss ion line s .EMI (electromagnetic interference) goe s up a s fa s ter edge s peed s produce s horter wavelength s relative to the bu s length, which create s unintended radiated emi ss ion s .

The s e emi ss ion s increa s e cro ss tal k and can cau s e a digital device to fail EMC (electromagnetic compliance) te s ting.Fa s ter edge s peed s generally al s o require higher current s to produce them. Higher current s tend to cau s e ground bounce, e s pecially on wide bu s e s in which many s ignal s s witch at once. Al s o, higher current increa s e s the amount of radiated magnetic energy and, with it, cro ss tal k .

A s data rate s increa s e to the gigabit range and beyond, digital de s igner s face all the fru s tration s that come with high frequency de s ign. An ideal digital pul s e i s cohe s ive in time and amplitude, i s free from deviation s and jitter, and ha s fa s t,clean tran s ition s . A s s y s tem s peed s increa s e it become s increa s ingly more difficult to maintain ideal s ignal characteri s -tic s , requiring careful con s ideration of s ignal integrity i ss ue s .

Review of S ignal Integrity Concept s

At frequencie s in the gigahert z range, a ho s t of variable s can affect s ignal integrity: s ignal path de s ign, impedance s and loading, tran s mi ss ion line effect s , and even power di s tribution on or off the circuit board.

The de s ign engineer ’s mi ss ion i s to minimi z e the s e problem s from the s tart, and to correct them when they do appear.

To do that, they mu s t inve s tigate both of the fundamental s ource s of s ignal degradation: digital i ss ue s and analog i ss ue s .

Problems Created by Digital Timing Issues

An engineer wor k ing with an evolving digital s y s tem de s ign i s li k ely to encounter s ignal integrity problem s in their digital form. Binary s ignal s on the bu s or device output s produce incorrect value s . The error s may appear in the waveform (timing mea s urement) view on a logic analy z er, and they may al s o s how up at the s tate or even the protocol level. It only ta k e s one bad bit to dramatically affect the outcome of an in s truction or tran s action.

Digital s ignal aberration s s tem from many root cau s e s .Timing-related i ss ue s are e s pecially common:

Bus Contention -Bu s contention occur s when two driver device s try to u s e the s ame bu s line at the s ame time.Normally, one of the driver s s hould go to a high imped-ance s tate and not hinder the other while it s end s data. If the high impedance device doe s n ’t change in time, the two driver s then contend for the bu s . Neither driver prevail s , forcing the bu s to an indeterminate amplitude that may fail to reach the thre s hold voltage. Thi s create s ,for example, a “0” logic level where there s hould be a “1.”With a high-s peed bu s , thi s s ituation i s complicated further by the time of flight between the contending s ource s and the receiver.

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Fundamental s of S ignal Integrity

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e31a51f52af90242a895e5e8/signal_integrity Setup and Hold Violations -S etup and hold violation s are increa s ing a s digital s y s tem s pu s h to fa s ter s peed s . A cloc k ed device, s uch a s a D flip flop, require s the data to be s table at it s input for a s pecified time before the cloc k arrive s . Thi s i s k nown a s “s etup ” time. S imilarly, the input data mu s t remain valid for a s pecified time after the leading edge of the cloc k . Thi s i s k nown a s “hold ”time. Violating s etup and/or hold requirement s can cau s e unpredictable glitche s on the output, or can cau s e there to be no output tran s ition at all. S etup and hold time s are decrea s ing a s device s peed s increa s e, ma k ing the timing relation s hip s harder to trouble s hoot.

Metastability - Meta s tability i s an indeterminate or un s ta-ble data s tate that re s ult s from a timing violation, s uch a s a s etup and hold problem. A s a re s ult, the output s ignal might be late or achieve an illegal output level, s uch a s a runt, a glitch, or even the wrong logic level.

Undefined Conditions -Undefined condition s can occur when the s witching s tate s on multiple input s of a logic device are not correctly aligned in time. Thi s may be

cau s ed by variation s or error s in the delay on the s e input s ignal s .

Inter-Symbol Interference (ISI) -I S I i s when one s ymbol interfere s with s ub s equent s ymbol s , creating di s tortion of the s ignal. It i s cau s ed by jitter and noi s e due to high frequency lo ss e s and reflection s .

Logic analy z er s have powerful tool s to help u s er s acquire and analy z e digital s ignal s in many format s . Today ’s advanced logic analy z er s can capture data from thou s and s of te s t point s s imultaneou s ly, then di s play s tream s of digital pul s e s and their placement in time relative to each another.With thi s type of conventional logic analy z er acqui s ition,amplitude error s and glitche s can appear to be valid logic level s even though they contain incorrect data. It may be po ss ible to s ee an error value in the hexadecimal code, for example, but the di s play won ’t s how why the error i s occurring.It can be very difficult to find the cau s e of a logic error if there i s no mean s to probe further into the s ignal ’s

behavior.

Every Design Detail is Important

At cloc k frequencie s in the hundred s of megahert z and above, every de s ign detail i s important to minimi z e s ignal integrity problem s :Cloc k di s tribution S ignal path de s ign S tub s Noi s e margin

Impedance s and loading Tran s mi ss ion line effect s S ignal path return current s Termination Decoupling Power di s tribution

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Isolating Analog Deviations

Many digital problem s are much ea s ier to pinpoint if you can probe deeply into the s ignal ’s behavior and s ee the analog repre s entation of the flawed digital s ignal. Although the problem may appear a s a mi s placed digital pul s e, the cau s e of the problem s ignal often i s due to it s analog characteri s tic s . Analog characteri s tic s can become digital fault s when low-amplitude s ignal s turn into incorrect logic s tate s , or when s low ri s e time s cau s e pul s e s to s hift in time.S eeing a digital pul s e s tream with a s imultaneou s analog view of the s ame pul s e s i s the fir s t s tep in trac k ing down the s e k ind s of problem s .

O s cillo s cope s are commonly u s ed to identify the root cau s e of s ignal integrity problem s by analy z ing a s ignal ’s analog characteri s tic s . They can di s play waveform detail s ,edge s and noi s e, and they can al s o detect and di s play tran s ient s . With powerful triggering and analy s i s feature s , an o s cillo s cope can trac k down analog aberration s and help the de s ign engineer find device problem s cau s ing fault s .

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Common causes of analog deviations:

Amplitude Problems –Amplitude problem s include ringing (o s cillation), “droop ” (decrea s ed amplitude at the s tart of a pul s e), and “runt ” pul s e s (tho s e which don ’t reach full amplitude).

Edge Aberrations –Edge aberration s can re s ult

from board layout problem s or from improper termination or even quality problem s in the s emiconductor device s .Aberration s can include pre s hoot, rounding, over s hoot,ringing, and s low ri s

e time.

Figure 1. Amplitude problem s

.

Figure 2. Edge aberration s .

Fundamental s of S ignal Integrity

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e31a51f52af90242a895e5e8/signal_integrity Reflections –Reflection s can be cau s ed by termination

and board layout problem s , where the outgoing s ignal

bounce s bac k toward it s s ource and interfere s with

s ub s equent pul s e s . Crosstalk – Cro ss tal k can occur when long trace s

running next to each other couple their s ignal s together

through mutual capacitance and inductance. In addition,

the higher current embodied in fa s t edge s increa s e s the

amount of radiated magnetic energy, and with it,

cro ss tal k

. Figure 3. Reflection s

.Figure 4. Cro ss tal k

.Figure 5. Ground bounce.Ground Bounce –Ground bounce, cau s ed by exce ss ive current draw (and/or re s i s tance in the power s upply and ground return path s ), can cau s e a circuit ’s ground reference level to s hift when current demand s are high. Jitter – Jitter i s defined a s edge placement variation s from cycle to cycle. S ome important cau s e s of jitter are noi s e, cro ss tal k and timing in s tability. Thi s can affect timing accuracy and s ynchroni z ation throughout a digital s y s

tem.

Figure 6. Jitter.

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Eye Diagrams: A Shortcut For Quickly Detecting Signal Integrity Problems

The eye diagram i s a vi s ual tool to ob s erve the

general s ignal integrity on a cloc k ed bu s . It i s a required compliance te s ting tool for many of today ’s bu s e s , particularly s erial type s , but any s ignal line can be viewed a s an eye diagram.

The eye diagram (s ee Figure 7) i s built up by overlaying the waveform trace s from many s ucce ss ive unit interval s (UI). Eye diagram s di s play s erial data with re s pect to a cloc k recovered from the data s ignal u s ing either hardware or s oftware tool s . The diagram di s play s all

po ss ible po s itive-going and negative-going tran s ition s (edge s ) and both data s tate s in a s ingle window. The re s ulting image re s emble s an eye.

Ideally, each new trace would align perfectly on top of the one s coming before it. In reality, however, s ignal integrity factor s cau s e the compo s ite trace to “blur ” a s it accumulate s , with jitter cau s ing a hori z ontal ‘blur ’ and noi s e cau s ing a vertical one.

Becau s e an eye diagram pre s ent s all po ss ible logic tran s ition s in a s ingle view, it can al s o provide a fa s t a ss e ss ment of a s ignal ’s condition. It can reveal s uch analog problem s a s s low ri s e time s , inter-s ymbol interfer-ence and attenuation level s . S ome engineer s s tart their evaluation s by loo k ing fir s t at eye diagram s , then trac k ing down any deviation s .

Many modern digiti z ing o s cillo s cope s offer tool s that can expedite complex cloc k recovery, triggering and s caling, then perform quantitative mea s urement s on the data. The s e new s oftware and hardware tool s have now incorporated the eye diagram mea s urement a s a s

tandard, one-button operation.

Figure 7. Example of an eye diagram.

Fundamental s of S ignal Integrity e31a51f52af90242a895e5e8/signal_integrity S ignal Integrity Mea s urement Requirement s

Direct s ignal ob s ervation s and mea s urement s are the only way s to di s cover many cau s e s of s ignal integrity-related problem s . A s alway s , u s ing the right tool will s implify any ta sk . Mo s t s ignal integrity mea s urement s are made with the familiar combination of in s trument s found in mo s t electronic s engineering lab s : the logic analy z er, the o s cillo s cope and, in s ome ca s e s , the s pectrum analy z er.Probe s and application s oftware – to perform ta sks li k e jitter analy s i s – round out the ba s ic tool k it. S ignal s ource s can be u s ed to provide di s torted s ignal s for s tre ss te s ting and evaluation of new device s and s y s tem s . They can al s o provide mi ss ing s y s tem input s , or they can replicate s en s or s ignal s to the device during te s t. A time-domain reflectometry s olution i s helpful for trac k ing s ignal path impedance problem s , s uch a s impedance mi s match and other s ignal integrity problem s that cau s e reflection s or amplitude lo ss .

Discovering Digital Faults Using Logic Analyzers

A s mentioned earlier, the logic analy z er i s the fir s t line of defen s e for digital trouble s hooting, e s pecially for complex s y s tem s with numerou s bu s e s , input s and output s . A logic analy z er ha s the high channel count to acquire digital information from many te s t point s , and then di s play that information coherently to identify problem s .

Becau s e it ’s a digital in s trument, the logic analy z er detect s thre s hold cro ss ing s on the s ignal s it ’s monitoring, then di s play s the logic s ignal s . Figure 8 s how s a typical timing diagram from a logic analy z er. The re s ulting digital waveform s are clear and under s tandable, and can ea s ily be compared with expected data to confirm that the device i s wor k ing correctly. The s e waveform s are u s ually the s tarting point in the s earch for problem s that compromi s e s ignal integrity.Logic analy z er s offer two different data acqui s ition mode s :"s tate" and “timing ”. S tate (or s ynchronou s ) acqui s ition i s u s ed to acquire the “s tate ” of the device under te s t (DUT).A s ignal from the DUT define s when and how often data will be acquired. The s ignal u s ed to cloc k the acqui s ition may be the device ’s cloc k , a control s ignal on the bu s or a s ignal that cau s e s the DUT to change s tate s . Data i s s ampled on the active edge and repre s ent s the condition of the DUT when the logic s ignal s are s table.Timing (or a s ynchronou s ) acqui s ition capture s s ignal timing information to create timing diagram s . In thi s mode, a cloc k internal to the logic analy z er i s u s ed to s ample data. There i s no fixed-timing relation s hip between the target device and the data acquired by the logic analy z er. Thi s mode i s u s ed when a long, contiguou s record of timing detail s i s

needed.

Figure 8. Logic analy z er di s play s howing a timing diagram.

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Timing Resolution

Timing diagram s are u s eful in detecting intermittent glitche s .The s e erratic pul s e s are unpredictable and often irregular in amplitude and duration, which ma k e s them difficult to detect and capture. The logic analy z er ’s timing re s olution will determine it s ability to detect and di s play glitche s , a s s hown in Figure 9. The higher the timing re s olution, the more li k ely an event will be s een and triggered on, enabling further analy s i s of the problem.

Memory Depth

Memory depth will impact a logic analy z er ’s ability to detect elu s ive problem s . Memory depth, along with timing re s olu-tion, determine s how much “time ” and detail can be captured in a s ingle acqui s ition. The total acqui s ition time at a given s ample rate (or timing re s olution) will increa s e a s memory depth increa s e s . Li k ewi s e, deeper memory allow s for a higher s ample rate, enabling more s ignal detail to be

captured.Acquiring more s ample s increa s e s the chance of capturing an error a s well a s the fault that cau s ed it.

Triggering Flexibility

Triggering flexibility i s the k ey to fa s t, efficient detection of un s een problem s . In a logic analy z er, triggering i s u s ed to s et condition s that, when met, will tell the logic analy z er to acquire data and di s play the re s ult. When a logic analy z er trigger s on an error, it i s proof that the error ha s occurred,which enable s fa s t detection. Mo s t logic analy z er s today include trigger s to detect event s that compromi s e s ignal integrity, li k e glitche s and s etup and hold time violation s . A unique s trength of a logic analy z er i s that the s e trigger condition s can be applied acro ss hundred s of channel s at once.

With it s ability to analy z e hundred s to thou s and s of digital line s at a time, the logic analy z er i s a powerful tool for di s covering device fault s for further analy s i s . For fa s t and efficient debugging, it ’s important to carefully loo k at u s ability feature s li k e triggering, a s well a s performance attribute s ,when choo s ing a logic analy z er s olution.

Logic Analyzer Probing Solutions

A logic analy z er ’s probing s cheme play s a critical role in high-s peed digital acqui s ition. It's critical that the probe deliver the s ignal to the logic analy z er with the highe s t po ss ible fidelity. Mo s t logic analy z er probe s fulfill thi s fundamental requirement, but s ome ta k e the concept even further.

S ome logic analy z er s require s eparate probing connection s for timing and s tate acqui s ition s . Thi s i s k nown a s “double probing ”, which i s a technique that can compromi s e the s ignal environment, affecting the actual mea s urement s them s elve s . For example, connecting two probe s at once to the te s t point can create unacceptable level s of s ignal loading. Connecting them inpidually expo s e s the te s t point to double the ri sk of damage or mi s connection. Moreover, it i s time-con s uming to connect two probe s .

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Figure 9. A logic analy z er ’s timing re s olution determine s it s ability to detect and di s play s ignal deviation s .

Fundamental s of S ignal Integrity e31a51f52af90242a895e5e8/signal_integrity S ome logic analy z er s have the ability to mea s ure both timing and s tate acqui s ition s through one probe. Thi s s imultaneou s timing/s tate acqui s ition s peed s trouble s hooting and s upport s s ignal integrity analy s i s ta sks by minimi z ing the impact of probe s on the DUT.

Recent advancement s have ta k en logic analy z er probing technology to a new level. The late s t generation of probe s can carry both digital information to the logic analy z er while al s o delivering the s ame information to an o s cillo s cope a s analog s ignal s . Any pin of the probe can be u s ed for both digital and analog acqui s ition. The analog s ignal route s

through the logic analy z er to an external o s cillo s cope, ma k ing it po ss ible to determine, almo s t in s tantly, if a digital error i s a ss ociated with an analog fault.

In high performance digital s y s tem s , a dedicated te s t point i s u s ually the mo s t practical way to mea s ure s ignal s . S ome dedicated te s t point s are fitted with pin s to s implify their connection with clip-on probe s and lead s et s . The s e type s of te s t connector s have an effect on the target device ’s s ignal environment, even when they aren ’t connected to a logic analy z er.

A logic analy z er ’s probe s can al s o mount to dedicated

connector s on the DUT. The matched impedance connector,MICTOR, i s a compact, high-den s ity connector joined to a matching connector on the logic analy z er probe. Board-mounted connector s add co s t to the target device, and they can affect high-s peed s ignal operation, but they do provide fa s t, po s itive connection s .

High-den s ity (HD) compre ss ion logic analy z er probe s and D-Max ?probing technology have emerged to provide an alternative to conventional MICTOR probe connector s .

The s e probe s don't require connector s on the DUT. In s tead,they mate directly to land pad s on the circuit board. Figure 10 s how s a D-Max ?connectorle ss probe in s talled on a circuit board, which i s held in place by threaded in s ert s .Connectorle ss probe s addre ss lead inductance and al s o offer very low capacitive loading. They al s o provide both s ingle-ended and differential mea s urement s with no tradeoff s in channel count. A D-Max ?connectorle ss logic analy z er probe ha s much le ss of an impact on the circuit board than a MICTOR-s tyle connection, but land pad s s till mu s t be de s igned into the board layout. The location at which a bu s i s probed can ma k e a difference in the appearance of the s ignal s . Becau s e of that, it ’s preferable to place te s t connection point s clo s e to the receiving device s , where s ignal s exhibit the

characteri s tic s that will be “s een ” by the logic IC s . The D-Max ?connectorle ss probe ’s s mall footprint offer s flexibility in thi s

placement.

Figure 10. D-Max TM connectorle ss analy z er probe.

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Uncovering Analog Deviations with Digitizing Oscilloscopes

Another major s ignal integrity mea s urement s olution i s the digiti z ing o s cillo s cope. The o s cillo s cope i s u s ed to i s olate analog problem s once they have been captured, in their digital form, by the logic analy z er. The o s cillo s cope can di s play waveform detail s , edge s and noi s e; it can detect and di s play tran s ient s and it can preci s ely mea s ure timing relation s hip s li k e s etup and hold time s . S ince digital error s are often related to analog s ignal integrity problem s , the o s cillo s cope i s a valuable tool in determining the cau s e of a digital fault.

Digiti z ing o s cillo s cope s come in different form s , s uch a s the digital s torage o s cillo s cope (D S O), the digital pho s phor o s cillo s cope (DPO), and the s ampling o s cillo s cope. The D S O i s ideal for low-repetition rate s ignal s with fa s t edge s or narrow pul s e width s . The D S O al s o excel s at capturing one-time event s and tran s ient s , and i s the be s t s olution for high-s peed, multi-channel de s ign application s .

The DPO i s the right tool for digital trouble s hooting, for finding intermittent s ignal s , and for many type s of eye diagram and ma sk te s ting. The DPO ’s extraordinary waveform capture rate overlay s s weep after s weep of information more quic k ly than any other o s cillo s cope, providing frequency-of-occurrence detail s , in color and inten s ity, with unmatched clarity. Figure 11 s how s a DPO di s play with inten s ity-grading.

A digital s ampling o s cillo s cope i s a better-s uited tool when the bandwidth (or the accuracy at high bandwidth) of a real-time o s cillo s cope i s n't enough. The s ampling o s cillo s cope i s an ideal tool for accurately capturing repetitive s ignal s with frequency component s that are much higher than the o s cillo-s cope ’s s ample rate. The digital s ampling o s cillo s cope i s

capable of mea s uring s ignal s of nearly an order of magnitude fa s ter than any other o s cillo s cope. By u s ing s equential equivalent-time s ampling of repetitive s ignal s , it can achieve bandwidth s of up to 100 GH z .

When choo s ing an o s cillo s cope, there are s everal k ey

performance con s ideration s that impact the quality of s ignal integrity mea s urement s . The s e include bandwidth, ri s e time,s ample rate, waveform capture rate, record length, and triggering flexibility.

12

Figure 11. A digital pho s phor o s cillo s cope with an inten s ity-graded di s play offer s fa s t in s ight into elu s ive problem s .

Fundamental s of S ignal Integrity e31a51f52af90242a895e5e8/signal_integrity Bandwidth

When trouble s hooting de s ign s with high data rate s or fa s t ri s e time s ignal s , o s cillo s cope bandwidth i s critical. The edge s peed (ri s e time) of a digital s ignal can carry much higher frequency component s than it s repetition rate might imply.An o s cillo s cope mu s t have s ufficient bandwidth to capture the higher frequency component s , and therefore s how s ignal tran s ition s accurately.

All o s cillo s cope s have a low-pa ss frequency re s pon s e that roll s off at higher frequencie s . Traditionally, o s cillo s cope bandwidth ha s been s pecified a s being the frequency at which a s inu s oidal input s ignal i s attenuated to 70.7% of the s ignal ’s true amplitude. Thi s i s k nown a s the “-3 dB point ”,which i s a term ba s ed on a logarithmic s cale. It mean s that a s ine wave mea s ured at the o s cillo s cope ’s bandwidth rating will have an amplitude error of -3 dB, or almo s t 30%. Figure 12 s how s a typical frequency re s pon s e plot for a 1 GH z o s cillo s cope, including the characteri s tic roll-off and s pecified -3 dB point.Without adequate bandwidth, an o s cillo s cope will not be able to re s olve high-frequency change s . Amplitude will be di s torted, edge s will di s appear and detail s will be lo s t.Without adequate bandwidth, all the s trength s and s pecial feature s of the o s cillo s cope will mean nothing. To determine the o s cillo s cope bandwidth needed to accu-rately characteri z e s ignal amplitude for a s pecific application,the “5 Time s Rule ” i s u s eful:An o s cillo s cope s elected u s ing the 5 Time s Rule will have le ss than a +/- 2% mea s urement error. In general, a higher bandwidth will provide a more accurate reproduction of the s ignal of intere s t.For debug of today ’s high-s peed s erial bu s e s , achieving the 5 Time s Rule can be challenging given the fa s t data rate s .For de s ign debug, it ’s common to choo s e an o s cillo s cope bandwidth that's three time s higher than the fa s te s t digital cloc k rate in the DUT – and therefore able to capture the 3rd harmonic of the cloc k rate. For characteri z ation and compliance te s ting of high-s peed bu s e s , the o s cillo s cope often need s to capture the 5th harmonic, requiring a band-width that i s five time s higher than the DUT ’s cloc k

rate.

Figure 12. Typical frequency re s pon s e plot for a 1 GH z o s cillo s cope.

The 5 Times Rule: ≥x 5Oscilloscope Bandwidth Highest Frequency Component of Signal

Primer

Chart 1 s how s common s erial bu s data rate s and the re s ulting o s cillo s cope bandwidth s to capture the 3rd and 5th harmonic s . It illu s trate s how today ’s high-s peed bu s e s require s ub s tantial o s cillo s cope bandwidth s .

Rise Time

In the digital world, ri s e time mea s urement s are critical. Ri s e time may actually be a more appropriate performance con-s ideration than bandwidth when choo s ing an o s cillo s cope to mea s ure digital s ignal s li k e pul s e s and s tep s . S ince s emicon-ductor device technology advance s have brought fa s ter edge performance to virtually every logic family, it ’s important to remember that many digital s y s tem s that are de s igned with s lower cloc k rate s may s till have very fa s t edge s (Chart 2).

To calculate the o s cillo s cope ri s e time required for a s pecific s ignal type, the following equation i s u s eful:

The ba s i s for the o s cillo s cope ri s e time s election i s s imilar to that for bandwidth. In general, an o s cillo s cope with fa s ter ri s e time will more accurately capture the critical detail s of fa s t tran s ition s . Ju s t a s with bandwidth, achieving thi s rule of thumb can be difficult when dealing with the extreme s peed s of today ’s high-s peed s erial bu s e s .

The ri s e time mea s ured by the o s cillo s cope will depend on both the actual s ignal ri s e time and the o s cillo s cope ri s e time.The fa s ter the o s cillo s cope ri s e time, the more accurate the mea s ured ri s e time will be. A general formula for the net mea s ured ri s e time i s :

14

2

=

+(

)Measured Rise Time Oscilloscope Rise Time

2

(

)

Signal Rise Time

≤x

Oscilloscope Rise Time Fastest Rise Time of Signal 51

Chart 2. S ome logic familie s produce inherently fa s ter ri s e time s than other s .

Chart 1. Common s erial bu s data rate s and the required o s cillo s cope bandwidth s to capture the 3rd and 5th harmonic s .

Fundamental s of S ignal Integrity

e31a51f52af90242a895e5e8/signal_integrity If the ri s e time of the o s cillo s cope i s un k nown, it can be calculated from the s pecified bandwidth by u s ing the follow-ing equation:Where k i s a value between 0.35 and 0.45, depending on the s hape of the o s cillo s cope ’s frequency re s pon s e curve and pul s e ri s e time re s pon s e.

Mo s t o s cillo s cope s with a bandwidth s pecification of le ss than 1 GH z have a s low frequency re s pon s e roll-off, s imilar to a Gau ss ian re s pon s e, and they can be modeled with a k value of 0.35. Higher bandwidth o s cillo s cope s typically have a maximally flat frequency re s pon s e with a s harp roll-off, clo s er to a bric k wall filter, and can be modeled with a k value of 0.42.Sample Rate S ample rate – s pecified in s ample s per s econd (S /s ) – refer s to how frequently a digital o s cillo s cope ta k e s a s ample,or a vi s ual s nap s hot, of the s ignal. A fa s ter s ample rate provide s greater re s olution and detail of the di s played

waveform, ma k ing it le ss li k ely that critical information or event s will be lo s t.

In order to accurately recon s truct a s ignal and avoid alia s ing,the Nyqui s t theorem s tate s that the s ignal mu s t be s ampled at a rate of at lea s t twice a s fa s t a s it s highe s t frequency component. But, the theorem a ss ume s an infinite record length and a continuou s s ignal. S ince no o s cillo s cope i s capable of infinite record length, and becau s e, by definition,glitche s aren't continuou s , s ampling at only twice the rate of the highe s t frequency component i s u s ually in s ufficient.In reality, accurate recon s truction of a s ignal depend s on both the s ample rate and the interpolation method u s ed to fill in the s pace s between the s ample s . S ome o s cillo s cope s offer s in(x)/x interpolation for mea s uring s inu s oidal s ignal s , or linear interpolation for s quare wave s , pul s e s , and other s ignal type s .

Waveform Capture Rate The waveform capture rate, expre ss ed a s waveform s per s econd (wfm s /s ), determine s how frequently the o s cillo s cope capture s a s ignal. While the s ample rate indicate s how frequently the o s cillo s cope s ample s the input s ignal within one waveform, or cycle, the waveform capture rate refer s to how quic k ly an o s cillo s cope acquire s the whole waveform.O s cillo s cope s with high waveform capture rate s provide s ignificantly more vi s ual in s ight into s ignal behavior. They can dramatically increa s e the probability that the o s cillo s cope will quic k ly capture tran s ient anomalie s li k e jitter, runt pul s e s ,glitche s , and tran s ition error s .Record Length Record length i s the number of s ample s the o s cillo s cope

can digiti z e and s tore in a s ingle acqui s ition. S ince an o s cillo-s cope can s tore only a limited number of s ample s , the waveform duration – or length of “time ” captured – will be inver s ely proportional to the o s cillo s cope ’s s ample rate.

Today ’s o s cillo s cope s allow the u s er to s elect the record length for an acqui s ition to optimi z e the level of detail needed for the application. If a very s table s inu s oidal s ignal i s being analy z ed, a 500-point record length may be s ufficient.However, if a complex digital data s tream i s being analy z ed for the cau s e s of timing anomalie s , a record length of over a million point s may be required. A longer record length enable s a longer time window to be captured with high re s olution (high s

ample rate).

=k Bandwidth Rise Time

x >2.5Oscilloscope Sample Rate highest frequency component of signal

highest frequency component of signal x >10Oscilloscope Sample Rate (For linear interpolation)(For sin(x)/x interpolation)

=Record Length

Time Interval Sample Rate

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Trigger Flexibility

The triggering function s in an o s cillo s cope are ju s t a s critical a s tho s e in the logic analy z er. Li k e a logic analy z er, the o s cillo s cope ’s trigger i s proof that a s pecified type of event occurred. Modern o s cillo s cope s offer trigger s for a ho s t of analog event s :

Edge level s and s lew rate condition s

Pul s e characteri s tic s , including glitche s ,

low-amplitude event s and even width condition s S etup and hold time violation s S erial digital pattern s

All of the s e trigger type s can a ss i s t engineer s in detecting and i s olating s ignal integrity problem s . There are al s o

variou s combination s of voltage, timing, and logic trigger s , a s well a s s pecialty trigger s , for application s s uch a s s erial data compliance te s ting.

The o s cillo s cope i s a critical piece of the s ignal integrity

mea s urement s olution. Once a digital fault ha s been i s olated,the o s cillo s cope can provide detailed analy s i s of the digital s ignal to identify po ss ible analog problem s . For quality mea s -urement s , and for efficient debug, it ’s important to loo k care-fully at the performance of the o s cillo s cope to en s ure it can meet the challenge s of the s ignal s being analy z ed. The k ey to fa s t and efficient debug i s u s ability feature s li k e triggering flexibility and tool s to efficiently navigate long record length s .

Oscilloscope Probing Solutions

The o s cillo s cope probe i s a critical element in s ignal integrity analy s i s mea s urement s . E ss entially, the probe mu s t bring the s y s tem ’s full bandwidth and s tep re s pon s e performance to the te s t point. Al s o, it mu s t be durable and s mall enough to probe den s ely-pac k ed circuit board s .

During trouble s hooting for s ignal integrity problem s , it ’s u s ually nece ss ary to have one probe “fixed ” on a te s t point at which an error appear s and another probe that can follow the s ignal path to i s olate the s ource of the problem.For high-s peed wor k , two important characteri s tic s of a probe are it s capacitance and it s inductance. Every probe ha s re s i s tance, inductance, and capacitance. The effect s of capacitance and inductance, however, increa s e with frequency. Their combined effect s can change the s ignal and it s mea s urement re s ult s .

Figure 13 demon s trate s the probe loading effect s on a typical high-s peed s ignal (ground-referenced 250 mV s tep with about 200 p s ri s e time). Thi s s creen s how s the s ame s ignal,loaded and unloaded, on a 4 GH z o s cillo s cope. The addition of the probe ha s loaded the original s ignal (the white trace),a s s hown by the green trace, with the front corner of the s tep being s omewhat s lowed. S imply s tated, a s capacitance and inductance increa s e, loading on the s ignal al s o increa s e s .S imilarly, lead length inductance can cau s e s ignificant di s tor-tion in the s ignal being mea s ured. Probe input characteri s tic s and lead length inductance can actually cau s e s ignal integrity problem s .

A new generation of ultra-low-capacitance o s cillo s cope probe s i s the an s wer to s ignal integrity and high-s peed

mea s urement problem s . With wide bandwidth s at the probe tip, very s hort probe tip lead length s and ultra-low input capacitance, the s e probe s better pre s erve the s ignal a s it travel s to the o s cillo s cope input. They bring the s ignal to the acqui s ition s y s tem accurately, with aberration s and all.The probe ’s performance i s critical becau s e it ’s the fir s t lin k ,in a chain of mea s urement s ub s y s tem s , that mu s t pre s erve,capture and di s play the s ignal a s accurately a s po ss ible. A high-bandwidth, low-capacitance probe with both a very s hort probe tip and ground lead length s en s ure s that the bandwidth of the o s cillo s cope i s not wa s ted.

16

Figure 13. Probe loading effect s on a high-s peed s ignal.

Fundamental s of S ignal Integrity

17

e31a51f52af90242a895e5e8/signal_integrity Identifying Signal Integrity Problems with Integrated Measurement Tools

In today ’s digital s y s tem s , with their fa s t edge s and data rate s , the analog characteri s tic s underlying digital s ignal s have an ever-increa s ing impact on s y s tem behavior—reliabili-ty and repeatability in particular. Efficiently trouble s hooting s ignal integrity problem s require s loo k ing at both the analog and digital domain s .

A s mentioned earlier, digital s ignal deviation s can ari s e from problem s in the analog domain li k e impedance mi s matche s ,tran s mi ss ion line effect s , and cro ss tal k . S imilarly, s ignal devia-tion s may be a by-product of digital i ss ue s li k e s etup and hold violation s . There i s a high degree of interaction between digital and analog s ignal effect s .

For device s with ju s t a few digital line s , a mixed s ignal o s cillo-s cope (M S O) provide s both analog and digital mea s urement capabilitie s . That enable s s imultaneou s analy s i s of both domain s with one in s trument.

For more complex device s , with many digital s ignal s , a full-featured logic analy z er integratedwith an o s cillo s cope i s the right choice.

Efficient trouble s hooting call s for tool s and method s that can addre ss both the analog and digital domain s . Capturing the interaction between multiple domain s , and di s playing time-correlated s ignal s in both analog and digital form s , i s the k ey to efficient trouble s hooting a s s hown in Figure 14.

Revealing the Frequency Domain with Real-Time S pectrum Analy z er s For s ome elu s ive event s , a mea s urement tool with improved

frequency re s olution may be required to s ee s ubtle frequency event s s uch a s cloc k pha s e-s lip, microphonic s , and p ha s e loc k loop (PLL) s ettling. S ince a s pectrum analy z er provide s much greater frequency re s olution than an o s cillo s cope, it can be an invaluable tool for trac k ing down the s e event s . It i s al s o a good tool for mea s uring the frequency tolerance of dither generation, which i s becoming more common a s today ’s high-s peed cloc ks are being intentionally dithered for EMI s uppre ss ion.S ince the s pectrum analy z er i s inherently bandwidth-limited a s it i s tuned over it s frequency range, it al s o provide s excel-lent dynamic range for mea

s uring low-level s ignal s that may be otherwi s e ma sk ed by noi s e. Example

s include impul s e noi s e, cloc k glitche s from meta s table event s , and cro ss tal k s ignal s in the pre s ence of higher amplitude s ignal s .

To help detect s ignal integrity problem s , a s pectrum analy z er i s typically u s ed to determine how frequency and amplitude parameter s behave over s hort and long interval s of e31a51f52af90242a895e5e8mon mea s urement ta sks include:

Ob s erving s ignal s ma sk ed by noi s e

S eeing tonal cloc k s ignal s ma sk ed within s pread s pectrum s ignal s Finding and analy z ing tran s ient and dynamic s ignal s Capturing bur s t tran s mi ss ion s , glitche s and s witching tran s ient s Characteri z ing PLL s ettling time s , frequency drift and microphonic s Frequency-s tepped cloc k s ignal s Te s ting and diagno s ing tran s ient EMI effect s Characteri z ing time-variant modulation s cheme s

Mixed S ignal O s cillo s cope s : Vi s uali z e Analog and Digital Domain s on One In s trument With a mixed s ignal o s cillo s cope (M S O), time-correlated digital and analog s ignal s can be vi s uali z ed on one di s play. The digital channel s of the M S O acquire and di s play a s ignal in it s digital form while the analog chan-nel s capture the s ame s ignal in it s analog form. S eeing the s e two s eparate view s together ma k e s it ea s y to vi s u-ali z e, for example, how a digital timing problem can re s ult from an analog glitch.With the M S O's digital and analog channel s , many point s of a de s ign can be s imultaneou s ly monitored. Thi s allow s the de s ign engineer to s ee a s y s tem-level view of hi s de s ign while trouble s hooting. Doe s the glitch on one s ignal happen at the s ame time a s a ri s ing edge on another s ignal, indicating a cro ss -tal k problem?Under s tanding the context in which an event occurred can be valuable while debugging digital s y s tem s . S ome performance M S O s offer advanced triggering in which the M S O's digital channel s can be u s ed to qualify analog trigger s . The M S O loo ks for a digital pattern fir s t before applying the analog trigger, capturing only the important s ignal change s .To view both domain s , both the analog and digital

channel s of the M S O mu s t be connected to the s ignal.Depending on the M S O, thi s may require attaching two probe s to the s ignal - one analog probe and one logic probe. To minimi z e the effect of probe loading on the s ignal under te s t, the capacitance of both probe s mu s t be minimi z ed, a s di s cu ss ed earlier. For high-s peed s ignal s , even low capacitance probe s may s ignificantly load the s ignal, impacting mea s urement s . Performance M S O s offer a unique feature to addre ss thi s problem - analog multiplexing. Thi s allow s the de s ign engineer to view a s ignal connected to any of the logic probe connection s in s imultaneou s analog and digital view s . Thi s minimi z e s probe loading s ince only one probe i s connected, an important feature for high-s peed s ignal s .

With an M S O, logic analy z er functionality i s combined with an o s cillo s cope, providing a powerful tool for trouble s hooting s ignal integrity problem s .

Primer

Revealing the Frequency Domain with

Real-Time Spectrum Analyzers

For s ome elu s ive event s, a mea s urement tool with improved

frequency re s olution may be required to s ee s ubtle frequency

event s s uch a s cloc k pha s e-s lip, microphonic s, and pha s e

loc k loop (PLL) s ettling. S ince a s pectrum analy z er provide s

much greater frequency re s olution than an o s cillo s cope, it

can be an invaluable tool for trac k ing down the s e event s. It i s

al s o a good tool for mea s uring the frequency tolerance of

dither generation, which i s becoming more common a s

today’s high-s peed cloc ks are being intentionally dithered for

EMI s uppre ss ion.

S ince the s pectrum analy z er i s inherently bandwidth-limited

a s it i s tuned over it s frequency range, it al s o provide s excel-

lent dynamic range for mea s uring low-level s ignal s that may

be otherwi s e ma sk ed by noi s e. Example s include impul s e

noi s e, cloc k glitche s from meta s table event s, and cro ss tal k

s ignal s in the pre s ence of higher amplitude s ignal s.

To help detect s ignal integrity problem s, a s pectrum analy z er

i s typically u s ed to determine how frequency and amplitude

parameter s behave over s hort and long interval s of time.

Common mea s urement ta sks include:

Ob s erving s ignal s ma sk ed by noi s e

S eeing tonal cloc k s ignal s ma sk ed within s pread

s pectrum s ignal s

Finding and analy z ing tran s ient and dynamic s ignal s

Capturing bur s t tran s mi ss ion s, glitche s and s witching

tran s ient s

Characteri z ing PLL s ettling time s, frequency drift and

microphonic s

Frequency-s tepped cloc k s ignal s

Te s ting and diagno s ing tran s ient EMI effect s

Characteri z ing time-variant modulation s cheme s

I s olating s oftware and hardware interaction s

Traditional s wept s pectrum analy z er s (S A) and vector s ignal

analy z er s (V S A) provide s nap s hot s of the s ignal in the fre-

quency domain or in the modulation domain. But often that's

not enough information to confidently de s cribe the dynamic

nature of modern s ignal s. S pectrum analy z er s are not all

equal in their capabilitie s to s ee tran s ient event s.

Each of the mea s urement ta sks li s ted above involve s

high-frequency (RF) s ignal s that change over time, often

unpredictably. To effectively characteri z e the s e s ignal s,

engineer s need a tool that can di s cover elu s ive event s,

effectively trigger on tho s e event s and i s olate them into

memory s o that s ignal behavior can be analy z ed in the

frequency, time, modulation, s tati s tical and code domain s.

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Figure 14. Cro ss tal k error s are quic k ly identified with time-correlated digital and

analog mea s urement s on the s ame di s play.

Fundamental s of S ignal Integrity e31a51f52af90242a895e5e8/signal_integrity The Real-Time S pectrum Analy z er (RT S A) i s de s igned to overcome the mea s urement limitation s of the S A and V S A to better addre ss the challenge s a ss ociated with tran s ient and dynamic RF s ignal s . The RT S A perform s s ignal analy s i s u s ing real-time digital s ignal proce ss ing (D S P) that occur s prior to memory s torage unli k e the po s t-acqui s ition proce ss ing common in the V S A architecture s . Real-time proce ss ing allow s the u s er to di s cover and trigger on event s with 100%certainty, given the minimum event duration of the s ignal and the bandwidth of the s pectrum analy z er. Once captured, the data can then be exten s ively analy z ed in multiple domain s –time, frequency and modulation - u s ing batch proce ss ing.With the RT S A ’s unique architecture, it i s po ss ible to trigger on an event in the frequency domain, capture a continuou s time record of changing RF event s and perform time-correlat-ed analy s i s in all domain s , s peeding trouble s hooting of RF s ignal integrity i ss ue s .S ince an RT S A mu s t ta k e all of the information contained in a time domain waveform and tran s form it into frequency domain s ignal s , there are s everal important s ignal proce ss ing requirement s to con s ider when choo s ing an RT S A for s ignal integrity analy s i s : frequency range, capture bandwidth, s ample rate, analy s i s interval and minimum event duration.Capture Bandwidth and Frequency Range The RT S A ’s frequency range and capture bandwidth are critical parameter s . It ’s important to choo s e the right RT S A for the s ignal of intere s t, with con s ideration s for thing s li k e the s ignal's fundamental frequency, modulation type, frequency s pread, and PLL tuning s tep s .Sample Rate The RT S A ’s analog-to-digital converter (ADC) cloc k rate mu s t be high enough to exceed the Nyqui s t criteria for the capture bandwidth that's nece ss ary for a particular mea s urement.Analysis Interval The analy s i s interval mu s t be long enough to s upport the narrowe s t re s olution bandwidth of intere s t when repetitive Fourier tran s form s are being u s ed to di s cover, capture and analy z e infrequent tran s ient event s in the frequency domain.Minimum Event Duration A minimum event i s defined a s the narrowe s t, non-repetitive rectangular pul s e that can be captured with 100% certainty at the s pecified accuracy. Narrower event s can be detected,but the accuracy and probability may degrade. Minimum event duration will depend largely on the RT S A ’s DFT tran s -form rate. For example, an RT S A with a 48,000 s pectrum s per s econd DFT tran s form rate can detect RF pul s e s a s s hort a s 24 micro s econd s with 100% probability and with full s pecified accuracy. By compari s on, a s wept s pectrum

analy z er with 50 s weep s per s econd require s pul s e s longer than 20 milli s econd s for 100% probability of detection at

full accuracy.

DPX Technology: a Revolutionary Tool for Signal Discovery

Te k tronix ’ patented Digital Pho s phor technology, or DPX, reveal s s ignal detail s that are completely mi ss ed by conventional s pectrum analy z er s and vector s ignal analy z er s . The s pectrum di s play i s an intuitive live color view of s ignal tran s ient s changing over time in the frequency domain, giving immediate confidence in the s tability of a de s ign or in s tantly di s playing a fault when it occur s . For example, Figure 14 i s a s pectrum ta k en for s y s tem level EMI diagno s tic s . It s how s the emi ss ion s and abundance of cloc k s ource s that are increa s ing the overall energy at a given frequency. At up to 48,000 s pectrum update s per s econd, only the DPX s pectrum can give the in s ight needed that energy from multiple s ignal s exi s t s within the s pread-s pectrum cloc k

frequency.

Figure 14. DPX S pectrum di s play s how s tonal cloc k s ignal s within a s pread s pectrum cloc k . The tonal s ignal s are temperature colored “hot ” to demon s trate the proportionality of occurrence in the time domain. The s pread s pectrum cloc k i s “cool ” to demon s trate the time-varying nature of the s ignal over time.

Primer

Multi-Domain Analysis

An RT S A may be integrated in with a logic analy z er and o s cil-lo s cope, allowing the u s er to trigger in the frequency domain and capture time-correlated frequency (RT S A), time (o s cillo-s cope) and digital (logic analy z er) s ignal s , for in-depth analy-s i s of s ignal integrity problem s . A RT S A i s an inde s pen s ible tool for detecting and analy z ing s ubtle frequency event s that require a mea s urement tool with tight frequency re s olution.Al s o, it s high dynamic range enable s the mea s urement of low-level s ignal s that may otherwi s e be ma sk ed by noi s e. A s de s ign s drive to high-s peed data rate s , requiring fa s t timing and technique s li k e cloc k dithering, the RT S A will become a critical part of the s ignal integrity mea s urement tool s et.

Simplifying Complex Measurements with Jitter Analysis Tools

S ignal integrity analy s i s i s not alway s a matter of finding a s low edge or a low s ignal amplitude s omewhere in the

s y s tem. A s explained earlier, factor s li k e timing jitter can play a large role in s y s tem s tability. Jitter typically originate s in the cloc k circuitry but can al s o ari s e from power s upply noi s e,cro ss tal k , and PLL circuit s . Jitter can affect data, addre ss e s ,enable line s and, in fact, virtually any s ignal in the s y s tem.In today ’s high-s peed de s ign s , a s s ignaling rate s climb above 2 GH z and voltage s wing s s hrin k to con s erve power, the

timing jitter in a s y s tem become s a s ignificant percentage of the s ignaling interval. Under the s e circum s tance s , jitter become s a fundamental performance limit. Under s tanding what jitter i s , and how to characteri z e it, i s the fir s t s tep to s ucce ss fully deploy high-s peed s y s tem s that dependably meet their performance requirement s .

Conceptually, jitter i s the deviation of timing edge s from their “correct ” location s . In a timing-ba s ed s y s tem, timing jitter i s the mo s t obviou s and direct form of non-ideal behavior. A s a form of noi s e, jitter mu s t be treated a s a random proce ss and characteri z ed in term s of it s s tati s tic s .

Jitter i s pided into two generali z ed categorie s : determini s tic jitter and random jitter. Determini s tic jitter i s predictable and con s i s tent, and it ha s s pecific cau s e s . Random jitter exhibit s a Gau ss ian di s tribution which i s theoretically uncon s trained in amplitude. S ince random jitter normally fit s a Gau ss ian di s tribution, certain s tati s tical rule s apply.

Time-interval error (TIE) i s the ba s i s for many jitter mea s ure-ment s . TIE i s the difference between the recovered cloc k (the jitter timing reference) and the actual waveform edge, a s s hown in Figure 15. Performing hi s togram and s pectrum analy s i s on the TIE waveform provide s the ba s i s for

advanced jitter mea s urement s , which i s a k ey s tep in trac k ing down the root cau s e of jitter in the DUT.

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Figure 15. Time-interval error i s the difference between the recovered cloc k and the actual waveform edge.

Fundamental s of S ignal Integrity e31a51f52af90242a895e5e8/signal_integrity With the s pectrum approach, jitter i s mea s ured by u s ing an o s cillo s cope to acquire a s ingle s hot or real-time acqui s ition of the data s ignal. To mo s t accurately capture the jitter, it ’s e ss ential that the o s cillo s cope have the be s t available

timing accuracy, s ignal-to-noi s e ratio, effective bit s and s ignal fidelity.

After the acqui s ition i s complete, the record i s par s ed by s oft-ware to determine the TIE for each of the cloc k edge s . Then the TIE re s ult s are pa ss ed through an FFT to compute their s pectrum. The re s ult i s a s pectrum of the acquired s ignal ’s jitter, which s how s the variou s component s of the total jitter,a s s hown in Figure 16. Once that i s complete, the Bit Error Rate (BER) re s ulting from jitter can be e s timated.

In ca s e s where more dynamic range i s required, a real-time s pectrum analy z er (RT S A) may be the right choice for jitter mea s urement s . Becau s e an RT S A i s , by definition, band-lim-ited to it s capture bandwidth (which in turn i s proce ss ed by a re s olution bandwidth filter), the noi s e floor of an RT S A mea s urement i s much lower than that of an o s cillo s cope.

That ma k e s the RT S A much more s en s itive to low level s puri-ou s s ignal s that are embedded in noi s e. The RT S A i s al s o capable of mea s uring the jitter on a s mall s ignal that's in the pre s ence of larger one s .

Jitter mea s urement i s a challenge that grow s in importance,with each new advancement in s y s tem performance and data rate s . There are s everal approache s to jitter mea s ure-ment, and each ha s it s own s trength s and tool s . The o s cillo-s cope offer s the ability to ob s erve jitter, u s ing technique s

li k e hi s togram s and eye diagram s . With bac k -end proce ss ing s oftware pac k age s , o s cillo s cope s provide other u s eful func-tion s li k e cycle-to-cycle mea s urement s , trend and s pectrum plot s , data logging and wor s t ca s e capture. When more dynamic range i s needed, a real-time s pectrum analy z er (RT S A) may be the be s t s olution, e s pecially if jitter need s to be mea s ured in the pre s ence of interfering s ignal s .Regardle ss of the approach, s oftware tool s are available to s implify complex jitter mea s urement s .Providing Critical Impedance Measurements with Time Domain Reflectometry Solutions The ideal tool for mea s uring impedance s and channel lo ss i s a s ampling o s cillo s cope equipped with a Time Domain Reflectometer (TDR) module. The TDR module enable s the s ignal tran s mi ss ion environment to be analy z ed in the time domain, ju s t a s the s ignal integrity of live s ignal s will be analy z ed in the time domain.Time domain reflectometry mea s ure s the reflection s that re s ult from a s ignal traveling through tran s mi ss ion environ-ment s li k e circuit board trace s , cable s or connector s . The TDR di s play will s how the impedance variation s in the s ignal path. Figure 17 i s an example of a TDR impedance mea s urement s

creen.

Figure 16. Total jitter s

pectrum.

Figure 17. TDR impedance mea s urement s creen.

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