IDT7203中文资料

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First-In/First-Out Dual-Port memory2048 x 9 organization (IDT7203)4096 x 9 organization (IDT7204)8192 x 9 organization (IDT7205)16384 x 9 organization (IDT7206)High-speed: 12ns access timeLow power consumption— Active: 770mW (max.)

— Power-down: 44mW (max.)

Asynchronous and simultaneous read and writeFully expandable in both word depth and width

Pin and functionally compatible with IDT720X familyStatus Flags: Empty, Half-Full, FullRetransmit capability

High-performance CMOS technology

Military product compliant to MIL-STD-883, Class BStandard Military Drawing for #5962-88669 (IDT7203),5962-89567 (IDT7203), and 5962-89568 (IDT7204) arelisted on this function

Industrial temperature range (-40oC to +85oC) is avail-able, tested to military electrical specifications

The IDT7203/7204/7205/7206 are dual-port memory buff-ers with internal pointers that load and empty data on a first-in/first-out basis. The device uses Full and Empty flags toprevent data overflow and underflow and expansion logic toallow for unlimited expansion capability in both word size anddepth.

Data is toggled in and out of the device through the use ofthe Write (W) and Read (R) pins.

The devices 9-bit width provides a bit for a control or parityat the user’s option. It also features a Retransmit (RT) capa-bility that allows the read pointer to be reset to its initial positionwhen RT is pulsed LOW. A Half-Full Flag is available in thesingle device and width expansion modes.

The IDT7203/7204/7205/7206 are fabricated using IDT’shigh-speed CMOS technology. They are designed for appli-cations requiring asynchronous and simultaneous read/writesin multiprocessing, rate buffering, and other applications.Military grade product is manufactured in compliance withthe latest revision of MIL-STD-883, Class B.

.

FUNCTIONAL BLOCK DIAGRAM

DATA INPUTSW

R

XI

The IDT logo is a registered trademark of Integrated Device Techology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

©1996 Integrated Device Technology, Inc.

For latest information contact IDT's web site at or fax-on-demand at 408-492-8391.

DECEMBER 1996

DSC-2661/9

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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

WD8D3D2D1D0XIFFQ0Q1Q2Q3Q8GND

Q3Q8

GNDNCQ4Q5

PLCC/LCCTOP VIEW

VccD4D5D6D7FL/RTRSEFXO/HFQ7Q6Q542661 drw 02a

DDDXIFFQQNCQcD6D7NCFL/RTRSEFXO/HF7Q6

2661 drw 02b

DIPTOP VIEW

NOTES:

1.The THINDIPs P28-2 and D28-3 are only available for the 7203/7204/7205.

2.The small outline package SO28-3 is only available for the 7204.3.Consult factory for CERPACK pinout.

ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED DC OPERATING

NOTE:2661 tbl 011.Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-INGS may cause permanent damage to the device. This is a stress ratingonly and functional operation of the device at these or any other conditionsabove those indicated in the operational sections of this specification is notimplied. Exposure to absolute maximum rating conditions for extendedperiods may affect reliability.

NOTE:

1.1.5V undershoots are allowed for 10ns once per cycle.

2661 tbl 02

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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

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DC ELECTRICAL CHARACTERISTICS FOR THE 7203 AND 7204

2661 tbl 03

NOTES:

1.Speed grades 65, 80, and 120ns are only available in the ceramic DIP.2.Measurements with 0.4 ≤ VIN ≤ VCC.3.R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.

4. ICC measurements are made with outputs open (only capacitive loading).5. Tested at f = 20MHz.

DC ELECTRICAL CHARACTERISTICS FOR THE 7205 AND 7206

2661 tbl 04

1.Measurements with 0.4 ≤ VIN ≤ VCC.2.R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.

3.ICC measurements are made with outputs open (only capacitive loading).4.Tested at f = 20MHz.

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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

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AC ELECTRICAL CHARACTERISTICS(1)

2661 tbl 05

1.Timings referenced as in AC Test Conditions.2.Pulse widths less than minimum are not allowed.3.Values guaranteed by design, not currently tested.4.Only applies to read data flow-through mode.

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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

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AC ELECTRICAL CHARACTERISTICS(1) (Continued)

CCACCA2661 tbl 06

1.Timings referenced as in AC Test Conditions.

2.Speed grades 65, 80, and 120ns are only available in the ceramic DIP.3.Pulse widths less than minimum are not allowed.4.Values guaranteed by design, not currently tested.5.Only applies to read data flow-through mode.

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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

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5V

1.1K

D.U.T.

30pF*

CAPACITANCE(1)

(TA = +25°C, f = 1.0 MHz)

Figure 1. Output Load*Includes jig and scope capacitances.

OR EQUIVALENT CIRCUIT

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1.This parameter is sampled and not 100% tested.2.With output deselected.

SIGNAL DESCRIPTIONSInputs:

DATA IN (D0–D8) — Data inputs for 9-bit wide data.

Controls:

RESET (RS) — Reset is accomplished whenever the Reset(RS) input is taken to a LOW state. During reset, both internalread and write pointers are set to the first location. A reset isrequired after power-up before a write operation can take place.Both the Read Enable (R) and Write Enable (W) inputs mustbe in the HIGH state during the window shown in Figure 2(i.e. tRSS before the rising edge of RS) and should notchange until tRSR after the rising edge of RS.

WRITE ENABLE (W) — A write cycle is initiated on the fallingedge of this input if the Full Flag (FF) is not set. Data set-up andhold times must be adhered-to, with respect to the rising edgeof the Write Enable (W). Data is stored in the RAM arraysequentially and independently of any on-going read operation.After half of the memory is filled, and at the falling edge of thenext write operation, the Half-Full Flag (HF) will be set to LOW,and will remain set until the difference between the write pointerand read pointer is less-than or equal to one-half of the totalmemory of the device. The Half-Full Flag (HF) is reset by therising edge of the read operation.

To prevent data overflow, the Full Flag (FF) will go LOW onthe falling edge of the last write signal, which inhibits further writeoperations. Upon the completion of a valid read operation, theFull Flag (FF) will go HIGH after tRFF, allowing a new valid writeto begin. When the FIFO is full, the internal write pointer isblocked from W, so external changes in W will not affect the FIFOwhen it is full.

READ ENABLE (R) — A read cycle is initiated on the fallingedge of the Read Enable (R), provided the Empty Flag (EF) is notset. The data is accessed on a First-In/First-Out basis, inde-pendent of any ongoing write operations. After Read Enable (R)goes HIGH, the Data Outputs (Q0 through Q8) will return to ahigh-impedance condition until the next Read operation. Whenall the data has been read from the FIFO, the Empty Flag (EF)will go LOW, allowing the “final” read cycle but inhibiting furtherread operations, with the data outputs remaining in a high-impedance state. Once a valid write operation has been accom-plished, the Empty Flag (EF) will go HIGH after tWEF and a validRead can then begin. When the FIFO is empty, the internal readpointer is blocked from R so external changes will not affect theFIFO when it is empty.

FIRST LOAD/RETRANSMIT (FL/RT) —

This is a dual-purpose input. In the Depth Expansion Mode, this pin isgrounded to indicate that it is the first device loaded (seeOperating Modes). The Single Device Mode is initiated bygrounding the Expansion In (XI).

The IDT7203/7204/7205/7206 can be made to retransmitdata when the Retransmit Enable Control (RT) input is pulsedLOW. A retransmit operation will set the internal read pointer tothe first location and will not affect the write pointer. The statusof the Flags will change depending on the relative locations ofthe read and write pointers. Read Enable (R) and Write Enable(W) must be in the HIGH state during retransmit. This feature isuseful when less than 2048/4096/8192/16384 writes are per-formed between resets. The retransmit feature is not compat-ible with the Depth Expansion Mode.

EXPANSION IN (XI) — This input is a dual-purpose pin.Expansion In (XI) is grounded to indicate an operation in thesingle device mode. Expansion In (XI) is connected to Expan-sion Out (XO) of the previous device in the Depth Expansion orDaisy-Chain Mode.

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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

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Outputs:

FULL FLAG (FF) — The Full Flag (FF) will go LOW, inhibitingfurther write operations, when the device is full. If the readpointer is not moved after Reset (RS), the Full Flag (FF) will goLOW after 2048/4096/8192/16384 writes.

EMPTY FLAG (EF) — The Empty Flag (EF) will go LOW,inhibiting further read operations, when the read pointer is equalto the write pointer, indicating that the device is empty.EXPANSION OUT/HALF-FULL FLAG (XO/HF) — This is adual-purpose output. In the single device mode, when Expan-sion In (XI) is grounded, this output acts as an indication of a half-full memory.

After half of the memory is filled, and at the falling edge of thenext write operation, the Half-Full Flag (HF) will be set to LOW

and will remain set until the difference between the write pointerand read pointer is less than or equal to one half of the totalmemory of the device. The Half-Full Flag (HF) is then reset bythe rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI) is con-nected to Expansion Out (XO) of the previous device. Thisoutput acts as a signal to the next device in the Daisy Chain byproviding a pulse to the next device when the previous devicereaches the last location of memory. There will be an XO pulsewhen the Write pointer reaches the last location of memory, andan additional XO pulse when the Read pointer reaches the lastlocation of memory.

DATA OUTPUTS (Q0-Q8) — Q0-Q8 are data outputs for 9-bit wide data. These outputs are in a high-impedance conditionwhenever Read (R) is in a HIGH state.

tRSC

tRS

RS

tRSS

W

tRSS

R

tEFL

EF

tHFH, tFFH

HF, FF

2661 drw 04

tRSR

NOTE:

1. W and R = VIH around the rising edge of RS.

Figure 2. Reset

R

Q0–Q8

W

D

0–D8

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Figure 3. Asynchronous Write and Read Operation

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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

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R

W

FF

Figure 4. Full FlagTiming From Last Write to First Read

W

R

EF

DATAOUT

Figure 5. Empty Flag Timing From Last Read to First Write

tRTCtRT

RT

tRTS

W,R

RTF

tRTR

HF, EF, FF

FLAG VALID

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NOTE:

1. EF, FF and HF may change status during Retransmit, but flags will be valid at tRTC.

Figure 6. Retransmit

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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

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W

EF

R

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Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.

R

FF

W

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Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse.

W

R

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HF

Figure 9. Half-Full Flag Timing

W

R

XO

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Figure 10. Expansion Out

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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

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XI

W

2661 drw 11

R

Figure 11. Expansion In

OPERATING MODES:

Care must be taken to assure that the appropriate flag ismonitored by each system (i.e. FF is monitored on the devicewhere W is used; EF is monitored on the device where R isused). For additional information, refer to Tech Note 8: Oper-ating FIFOs on Full and Empty Boundary Conditions andTech Note 6: Designing with FIFOs.

Single Device Mode

A single IDT7203/7204/7205/7206 may be used when theapplication requirements are for 2048/4096/8192/16384 wordsor less. The IDT7203/7204/7205/7206 is in a Single DeviceConfiguration when the Expansion In (XI) control input isgrounded (see Figure 12).

Depth Expansion

The IDT7203/7204/7205/7206 can easily be adapted toapplications when the requirements are for greater than 2048/4096/8192/16384 words. Figure 14 demonstrates Depth Ex-pansion using three IDT7203/7204/7205/7206s. Any depthcan be attained by adding additional IDT7203/7204/7205/7206s. The IDT7203/7204/7205/7206 operates in the DepthExpansion mode when the following conditions are met:1.The first device must be designated by grounding the FirstLoad (FL) control input.

2.All other devices must have FL in the HIGH state.

3.The Expansion Out (XO) pin of each device must be tied tothe Expansion In (XI) pin of the next device. See Figure 14.4.External logic is needed to generate a composite Full Flag(FF) and Empty Flag (EF). This requires the ORing of allEFs and ORing of all FFs (i.e. all must be set to generate thecorrect composite FF or EF). See Figure 14.

5.The Retransmit (RT) function and Half-Full Flag (HF) arenot available in the Depth Expansion Mode.For additional information, refer to Tech Note 9: CascadingFIFOs or FIFO Modules.

USAGE MODES:

Width Expansion

Word width may be increased simply by connecting thecorresponding input control signals of multiple devices. Sta-tus flags (EF, FF and HF) can be detected from any one device.Figure 13 demonstrates an 18-bit word width by using twoIDT7203/7204/7205/7206s. Any word width can be attainedby adding additional IDT7203/7204/7205/7206s (Figure 13).Bidirectional Operation

Applications which require data buffering between twosystems (each system capable of Read and Write operations)can be achieved by pairing IDT7203/7204/7205/7206s asshown in Figure 16. Both Depth Expansion and Width Expan-sion may be used in this mode.

Data Flow-Through

Two types of flow-through modes are permitted, a readflow-through and write flow-through mode. For the read flow-through mode (Figure 17), the FIFO permits a reading of asingle word after writing one word of data into an empty FIFO.The data is enabled on the bus in (tWEF + tA) ns after the risingedge of W, called the first write edge, and it remains on the busuntil the R line is raised from LOW-to-HIGH, after which thebus would go into a three-state mode after tRHZ ns. The EF linewould have a pulse showing temporary deassertion and thenwould be asserted.

In the write flow-through mode (Figure 18), the FIFOpermits the writing of a single word of data immediately afterreading one word of data from a full FIFO. The R line causesthe FF to be deasserted but the W line being LOW causes it tobe asserted again in anticipation of a new data word. On therising edge of W, the new word is loaded in the FIFO. The Wline must be toggled when FF is not asserted to write new datain the FIFO and to increment the write pointer.

Compound Expansion

The two expansion techniques described above can beapplied together in a straightforward manner to achieve largeFIFO arrays (see Figure 15).

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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

WRITE (W)

FULL FLAG (FF)

RESET (RS)

READ (R)

DATA OUT (Q)EMPTY FLAG (EF)RETRANSMIT (RT)

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Figure 12. Block Diagram of 2048 x 9/4096 x 9/8192 x 9/16384 x 9 FIFO Used in Single Device Mode

DATA IN(D)WRITE (W)FULL FLAG (FF)

RESET (RS

)

READ (R)

EMPTY FLAG (EF)RETRANSMIT (RT)

DATA OUT (Q)

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NOTE:

1.Flag detection is accomplished by monitoring the FF, EF and HF signals on either (any) device used in the width expansion configuration.

Do not connect any output signals together.

Figure 13. Block Diagram of 2048 x 18/4096 x 18/8192 x 18/16384 x 18 FIFO Memory Used in Width Expansion Mode

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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

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TRUTH TABLES

TABLE I – RESET AND RETRANSMIT

2661 tbl 09

1. Pointer will Increment if flag is HIGH.

TABLE II – RESET AND FIRST LOAD

2661 tbl 101. XI is connected to XO of previous device. See Figure 14.

2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output

WD

FULL

RS

EMPTY

RQVCC

Figure 14. Block Diagram of 6149 x 9/12298 x 9/24596 x 9/49152 x 9 FIFO Memory (Depth Expansion)

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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

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Q0–Q8D0–DN

D9-DN

NOTES:

1. For depth expansion block see section on Depth Expansion and Figure 14.2. For Flag detection see section on Width Expansion and Figure 13.

Q9–Q17

D18-DN

D(N-8)-DN

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R, W, RS

Figure 15. Compound FIFO Expansion

SYSTEM ASYSTEM B

Figure 16. Bidirectional FIFO Operation

DATAIN

W

R

EF

DATAOUT

Figure 17. Read Data Flow-Through Mode

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IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

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R

W

FF

DATAIN

DATAOUT

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Figure 18. Write Data Flow-Through Mode

ORDERING INFORMATION

IDT

XXXX

X

XXSpeed

XPackage

XProcess/

BlankB

Commercial (0°C to +70

°C)Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class BPlastic DIP

Plastic THINDIPCeramic DIP

Ceramic THINDIP (all except 7206)Plastic Leaded Chip Carrier

Leadless Chip Carrier (Military only)Small Outline IC (7204 only)Commercial 7203/04 OnlyCommercial OnlyCommercial OnlyMilitary Only

Commercial OnlyMilitary 7203/04 OnlyMilitary 7203/04DB Only

Standard Power (7203/7204 only)Low Power2048 x 9 FIFO4096 x 9 FIFO8192 x 9 FIFO16384 x 9 FIFO

Access Time (tA)Speed in ns

DeviceTypePower

PTPDTDJLSO12152025303540506580SL7203720472057206

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