TMS320F28232系列规格书,Datasheet 资料

TMS320F28335,TMS320F28334,TMS320F28332 TMS320F28235,TMS320F28234,TMS320F28232 Digital Signal Controllers(DSCs)

Data Manual

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty.Production processing does not

necessarily include testing of all parameters.

Literature Number:SPRS439M

June2007–Revised August2012

芯天下--63bca34d312b3169a451a478/

TMS320F28335,TMS320F28334,TMS320F28332

TMS320F28235,TMS320F28234,TMS320F28232

63bca34d312b3169a451a478 SPRS439M–JUNE2007–REVISED AUGUST2012

Contents

1TMS320F2833x,TMS320F2823x DSCs (10)

1.1Features (10)

1.2Getting Started (11)

2Introduction (12)

2.1Pin Assignments (14)

2.2Signal Descriptions (23)

3Functional Overview (33)

3.1Memory Maps (34)

3.2Brief Descriptions (41)

3.2.1C28x CPU (41)

3.2.2Memory Bus(Harvard Bus Architecture) (41)

3.2.3Peripheral Bus (41)

3.2.4Real-Time JTAG and Analysis (42)

3.2.5External Interface(XINTF) (42)

3.2.6Flash (42)

3.2.7M0,M1SARAMs (42)

3.2.8L0,L1,L2,L3,L4,L5,L6,L7SARAMs (43)

3.2.9Boot ROM (43)

3.2.9.1Peripheral Pins Used by the Bootloader (44)

3.2.10Security (44)

3.2.11Peripheral Interrupt Expansion(PIE)Block (46)

3.2.12External Interrupts(XINT1–XINT7,XNMI) (46)

3.2.13Oscillator and PLL (46)

3.2.14Watchdog (46)

3.2.15Peripheral Clocking (46)

3.2.16Low-Power Modes (46)

3.2.17Peripheral Frames0,1,2,3(PFn) (47)

3.2.18General-Purpose Input/Output(GPIO)Multiplexer (47)

3.2.1932-Bit CPU-Timers(0,1,2) (47)

3.2.20Control Peripherals (48)

3.2.21Serial Port Peripherals (48)

3.3Register Map (49)

3.4Device Emulation Registers (51)

3.5Interrupts (52)

3.5.1External Interrupts (56)

3.6System Control (57)

3.6.1OSC and PLL Block (58)

3.6.1.1External Reference Oscillator Clock Option (59)

3.6.1.2PLL-Based Clock Module (60)

3.6.1.3Loss of Input Clock (61)

3.6.2Watchdog Block (62)

3.7Low-Power Modes Block (63)

4Peripherals (64)

4.1DMA Overview (64)

4.232-Bit CPU-Timer0,CPU-Timer1,CPU-Timer2 (66)

4.3Enhanced PWM Modules (68)

4.4High-Resolution PWM(HRPWM) (72)

4.5Enhanced CAP Modules (73)

4.6Enhanced QEP Modules (75)

4.7Analog-to-Digital Converter(ADC)Module (77)

4.7.1ADC Connections if the ADC Is Not Used (81)

2Contents Copyright?2007–2012,Texas Instruments Incorporated 芯天下--63bca34d312b3169a451a478/

TMS320F28335,TMS320F28334,TMS320F28332

TMS320F28235,TMS320F28234,TMS320F28232 63bca34d312b3169a451a478 SPRS439M–JUNE2007–REVISED AUGUST2012

4.7.2ADC Registers (82)

4.7.3ADC Calibration (83)

4.8Multichannel Buffered Serial Port(McBSP)Module (83)

4.9Enhanced Controller Area Network(eCAN)Modules(eCAN-A and eCAN-B) (86)

4.10Serial Communications Interface(SCI)Modules(SCI-A,SCI-B,SCI-C) (91)

4.11Serial Peripheral Interface(SPI)Module(SPI-A) (95)

4.12Inter-Integrated Circuit(I2C) (98)

4.13GPIO MUX (99)

4.14External Interface(XINTF) (106)

5Device Support (108)

5.1Device and Development Support Tool Nomenclature (108)

5.2Documentation Support (110)

5.3Community Resources (115)

6Electrical Specifications (116)

6.1Absolute Maximum Ratings (116)

6.2Recommended Operating Conditions (117)

6.3Electrical Characteristics (117)

6.4Current Consumption (118)

6.4.1Reducing Current Consumption (120)

6.4.2Current Consumption Graphs (121)

6.4.3Thermal Design Considerations (122)

6.5Emulator Connection Without Signal Buffering for the DSP (123)

6.6Timing Parameter Symbology (124)

6.6.1General Notes on Timing Parameters (124)

6.6.2Test Load Circuit (124)

6.6.3Device Clock Table (125)

6.7Clock Requirements and Characteristics (126)

6.8Power Sequencing (127)

6.8.1Power Management and Supervisory Circuit Solutions (128)

6.9General-Purpose Input/Output(GPIO) (131)

6.9.1GPIO-Output Timing (131)

6.9.2GPIO-Input Timing (132)

6.9.3Sampling Window Width for Input Signals (133)

6.9.4Low-Power Mode Wakeup Timing (134)

6.10Enhanced Control Peripherals (139)

6.10.1Enhanced Pulse Width Modulator(ePWM)Timing (139)

6.10.2Trip-Zone Input Timing (139)

6.10.3High-Resolution PWM Timing (140)

6.10.4Enhanced Capture(eCAP)Timing (140)

6.10.5Enhanced Quadrature Encoder Pulse(eQEP)Timing (141)

6.10.6ADC Start-of-Conversion Timing (142)

6.11External Interrupt Timing (142)

6.12I2C Electrical Specification and Timing (143)

6.13Serial Peripheral Interface(SPI)Timing (143)

6.13.1Master Mode Timing (143)

6.13.2SPI Slave Mode Timing (148)

6.14External Interface(XINTF)Timing (151)

6.14.1USEREADY=0 (151)

6.14.2Synchronous Mode(USEREADY=1,READYMODE=0) (152)

6.14.3Asynchronous Mode(USEREADY=1,READYMODE=1) (153)

6.14.4XINTF Signal Alignment to XCLKOUT (155)

6.14.5External Interface Read Timing (156)

6.14.6External Interface Write Timing (158)

Copyright?2007–2012,Texas Instruments Incorporated Contents3芯天下--63bca34d312b3169a451a478/

TMS320F28335,TMS320F28334,TMS320F28332

TMS320F28235,TMS320F28234,TMS320F28232

SPRS439M–JUNE2007–REVISED 63bca34d312b3169a451a478

6.14.7External Interface Ready-on-Read Timing With One External Wait State (160)

6.14.8External Interface Ready-on-Write Timing With One External Wait State (163)

6.14.9and Timing (166)

6.15On-Chip Analog-to-Digital Converter (169)

6.15.1ADC Power-Up Control Bit Timing (170)

6.15.2Definitions (171)

6.15.3Sequential Sampling Mode(Single-Channel)(SMODE=0) (172)

6.15.4Simultaneous Sampling Mode(Dual-Channel)(SMODE=1) (173)

6.15.5Detailed Descriptions (174)

6.16Multichannel Buffered Serial Port(McBSP)Timing (175)

6.16.1McBSP Transmit and Receive Timing (175)

6.16.2McBSP as SPI Master or Slave Timing (178)

6.17Flash Timing (182)

6.18Migrating Between F2833x Devices and F2823x Devices (184)

7L-to-M Revision History (185)

8K-to-L Revision History (186)

9Thermal and Mechanical Data (187)

4Contents Copyright?2007–2012,Texas Instruments Incorporated 芯天下--63bca34d312b3169a451a478/

TMS320F28335,TMS320F28334,TMS320F28332

TMS320F28235,TMS320F28234,TMS320F28232 63bca34d312b3169a451a478 SPRS439M–JUNE2007–REVISED AUGUST2012

List of Figures

2-1F2833x,F2823x176-Pin PGF/PTP LQFP(Top View) (14)

2-2F2833x,F2823x179-Ball ZHH MicroStar BGA?(Upper Left Quadrant)(Bottom View) (16)

2-3F2833x,F2823x179-Ball ZHH MicroStar BGA?(Upper Right Quadrant)(Bottom View) (17)

2-4F2833x,F2823x179-Ball ZHH MicroStar BGA?(Lower Left Quadrant)(Bottom View) (18)

2-5F2833x,F2823x179-Ball ZHH MicroStar BGA?(Lower Right Quadrant)(Bottom View) (19)

2-6F2833x,F2823x176-Ball ZJZ Plastic BGA(Upper Left Quadrant)(Bottom View) (20)

2-7F2833x,F2823x176-Ball ZJZ Plastic BGA(Upper Right Quadrant)(Bottom View) (21)

2-8F2833x,F2823x176-Ball ZJZ Plastic BGA(Lower Left Quadrant)(Bottom View) (22)

2-9F2833x,F2823x176-Ball ZJZ Plastic BGA(Lower Right Quadrant)(Bottom View) (22)

3-1Functional Block Diagram (34)

3-2F28335,F28235Memory Map (36)

3-3F28334,F28234Memory Map (37)

3-4F28332,F28232Memory Map (37)

3-5External and PIE Interrupt Sources (53)

3-6External Interrupts (53)

3-7Multiplexing of Interrupts Using the PIE Block (54)

3-8Clock and Reset Domains (57)

3-9OSC and PLL Block Diagram (58)

3-10Using a3.3-V External Oscillator (59)

3-11Using a1.9-V External Oscillator (59)

3-12Using the Internal Oscillator (59)

3-13Watchdog Module (62)

4-1DMA Functional Block Diagram (65)

4-2CPU-Timers (66)

4-3CPU-Timer Interrupt Signals and Output Signal (66)

4-4Time-Base Counter Synchronization Scheme3 (68)

4-5ePWM Submodules Showing Critical Internal Signal Interconnections (71)

4-6eCAP Functional Block Diagram (73)

4-7eQEP Functional Block Diagram (75)

4-8Block Diagram of the ADC Module (78)

4-9ADC Pin Connections With Internal Reference (79)

4-10ADC Pin Connections With External Reference (80)

4-11McBSP Module (84)

4-12eCAN Block Diagram and Interface Circuit (87)

4-13eCAN-A Memory Map (88)

4-14eCAN-B Memory Map (89)

4-15Serial Communications Interface(SCI)Module Block Diagram (94)

4-16SPI Module Block Diagram(Slave Mode) (97)

4-17I2C Peripheral Module Interfaces (98)

4-18GPIO MUX Block Diagram (100)

4-19Qualification Using Sampling Window (105)

4-20External Interface Block Diagram (106)

4-21Typical16-bit Data Bus XINTF Connections (107)

4-22Typical32-bit Data Bus XINTF Connections (107)

5-1Example of F2833x,F2823x Device Nomenclature (109)

6-1Typical Operational Current Versus Frequency(F28335,F28235,F28334,F28234) (122)

6-2Typical Operational Power Versus Frequency(F28335,F28235,F28334,F28234) (122)

Copyright?2007–2012,Texas Instruments Incorporated List of Figures5芯天下--63bca34d312b3169a451a478/

TMS320F28335,TMS320F28334,TMS320F28332

TMS320F28235,TMS320F28234,TMS320F28232

SPRS439M–JUNE2007–REVISED 63bca34d312b3169a451a478 6-3Emulator Connection Without Signal Buffering for the DSP (123)

6-4 3.3-V Test Load Circuit (124)

6-5Clock Timing (127)

6-6Power-on Reset (129)

6-7Warm Reset (130)

6-8Example of Effect of Writing Into PLLCR Register (131)

6-9General-Purpose Output Timing (132)

6-10Sampling Mode (132)

6-11General-Purpose Input Timing (133)

6-12IDLE Entry and Exit Timing (134)

6-13STANDBY Entry and Exit Timing Diagram (136)

6-14HALT Wake-Up Using GPIOn (138)

6-15PWM Hi-Z Characteristics (139)

6-16or Timing (142)

6-17External Interrupt Timing (142)

6-18SPI Master Mode External Timing(Clock Phase=0) (145)

6-19SPI Master Mode External Timing(Clock Phase=1) (147)

6-20SPI Slave Mode External Timing(Clock Phase=0) (149)

6-21SPI Slave Mode External Timing(Clock Phase=1) (150)

6-22Relationship Between XTIMCLK and SYSCLKOUT (154)

6-23Example Read Access (157)

6-24Example Write Access (159)

6-25Example Read With Synchronous XREADY Access (161)

6-26Example Read With Asynchronous XREADY Access (162)

6-27Write With Synchronous XREADY Access (164)

6-28Write With Asynchronous XREADY Access (165)

6-29External Interface Hold Waveform (167)

6-30Timing Requirements(XCLKOUT=1/2XTIMCLK) (168)

6-31ADC Power-Up Control Bit Timing (170)

6-32ADC Analog Input Impedance Model (171)

6-33Sequential Sampling Mode(Single-Channel)Timing (172)

6-34Simultaneous Sampling Mode Timing (173)

6-35McBSP Receive Timing (177)

6-36McBSP Transmit Timing (177)

6-37McBSP Timing as SPI Master or Slave:CLKSTP=10b,CLKXP=0 (178)

6-38McBSP Timing as SPI Master or Slave:CLKSTP=11b,CLKXP=0 (179)

6-39McBSP Timing as SPI Master or Slave:CLKSTP=10b,CLKXP=1 (180)

6-40McBSP Timing as SPI Master or Slave:CLKSTP=11b,CLKXP=1 (181)

6List of Figures Copyright?2007–2012,Texas Instruments Incorporated 芯天下--63bca34d312b3169a451a478/

TMS320F28335,TMS320F28334,TMS320F28332

TMS320F28235,TMS320F28234,TMS320F28232 63bca34d312b3169a451a478 SPRS439M–JUNE2007–REVISED AUGUST2012

List of Tables

2-1F2833x Hardware Features (12)

2-2F2823x Hardware Features (13)

2-3Signal Descriptions (23)

3-1Addresses of Flash Sectors in F28335,F28235 (38)

3-2Addresses of Flash Sectors in F28334,F28234 (38)

3-3Addresses of Flash Sectors in F28332,F28232 (38)

3-4Handling Security Code Locations (39)

3-5Wait-states (40)

3-6Boot Mode Selection (43)

3-7Peripheral Bootload Pins (44)

3-8Peripheral Frame0Registers (49)

3-9Peripheral Frame1Registers (49)

3-10Peripheral Frame2Registers (50)

3-11Peripheral Frame3Registers (50)

3-12Device Emulation Registers (51)

3-13PIE Peripheral Interrupts (54)

3-14PIE Configuration and Control Registers (55)

3-15External Interrupt Registers (56)

3-16PLL,Clocking,Watchdog,and Low-Power Mode Registers (58)

3-17PLL Settings (60)

3-18CLKIN Divide Options (60)

3-19Possible PLL Configuration Modes (61)

3-20Low-Power Modes (63)

4-1CPU-Timers0,1,2Configuration and Control Registers (67)

4-2ePWM Control and Status Registers(Default Configuration in PF1) (69)

4-3ePWM Control and Status Registers(Remapped Configuration in PF3-DMA-Accessible) (70)

4-4eCAP Control and Status Registers (74)

4-5eQEP Control and Status Registers (76)

4-6ADC Registers (82)

4-7McBSP Register Summary (85)

4-8 3.3-V eCAN Transceivers (87)

4-9CAN Register Map (90)

4-10SCI-A Registers (92)

4-11SCI-B Registers (92)

4-12SCI-C Registers (93)

4-13SPI-A Registers (96)

4-14I2C-A Registers (99)

4-15GPIO Registers (101)

4-16GPIO-A Mux Peripheral Selection Matrix (102)

4-17GPIO-B Mux Peripheral Selection Matrix (103)

4-18GPIO-C Mux Peripheral Selection Matrix (104)

4-19XINTF Configuration and Control Register Mapping (107)

5-1TMS320x2833x,2823x Peripheral Selection Guide (110)

6-1TMS320F28335/F28235Current Consumption by Power-Supply Pins at150-MHz SYSCLKOUT (118)

6-2TMS320F28334/F28234Current Consumption by Power-Supply Pins at150-MHz SYSCLKOUT (119)

6-3Typical Current Consumption by Various Peripherals(at150MHz) (120)

6-4Clocking and Nomenclature(150-MHz Devices) (125)

Copyright?2007–2012,Texas Instruments Incorporated List of Tables7芯天下--63bca34d312b3169a451a478/

TMS320F28335,TMS320F28334,TMS320F28332

TMS320F28235,TMS320F28234,TMS320F28232

SPRS439M–JUNE2007–REVISED 63bca34d312b3169a451a478 6-5Clocking and Nomenclature(100-MHz Devices) (125)

6-6Input Clock Frequency (126)

6-7XCLKIN Timing Requirements–PLL Enabled (126)

6-8XCLKIN Timing Requirements–PLL Disabled (126)

6-9XCLKOUT Switching Characteristics(PLL Bypassed or Enabled) (126)

6-10Power Management and Supervisory Circuit Solutions (128)

6-11Reset(XRS)Timing Requirements (130)

6-12General-Purpose Output Switching Characteristics (131)

6-13General-Purpose Input Timing Requirements (132)

6-14IDLE Mode Timing Requirements (134)

6-15IDLE Mode Switching Characteristics (134)

6-16STANDBY Mode Timing Requirements (135)

6-17STANDBY Mode Switching Characteristics (135)

6-18HALT Mode Timing Requirements (137)

6-19HALT Mode Switching Characteristics (137)

6-20ePWM Timing Requirements (139)

6-21ePWM Switching Characteristics (139)

6-22Trip-Zone Input Timing Requirements (139)

6-23High-Resolution PWM Characteristics at SYSCLKOUT=(60–150MHz) (140)

6-24Enhanced Capture(eCAP)Timing Requirement (140)

6-25eCAP Switching Characteristics (140)

6-26Enhanced Quadrature Encoder Pulse(eQEP)Timing Requirements (141)

6-27eQEP Switching Characteristics (141)

6-28External ADC Start-of-Conversion Switching Characteristics (142)

6-29External Interrupt Timing Requirements (142)

6-30External Interrupt Switching Characteristics (142)

6-31I2C Timing (143)

6-32SPI Master Mode External Timing(Clock Phase=0) (144)

6-33SPI Master Mode External Timing(Clock Phase=1) (146)

6-34SPI Slave Mode External Timing(Clock Phase=0) (148)

6-35SPI Slave Mode External Timing(Clock Phase=1) (150)

6-36Relationship Between Parameters Configured in XTIMING and Duration of Pulse (151)

6-37XINTF Clock Configurations (154)

6-38External Interface Read Timing Requirements (156)

6-39External Interface Read Switching Characteristics (156)

6-40External Interface Write Switching Characteristics (158)

6-41External Interface Read Switching Characteristics(Ready-on-Read,1Wait State) (160)

6-42External Interface Read Timing Requirements(Ready-on-Read,1Wait State) (160)

6-43Synchronous XREADY Timing Requirements(Ready-on-Read,1Wait State) (160)

6-44Asynchronous XREADY Timing Requirements(Ready-on-Read,1Wait State) (160)

6-45External Interface Write Switching Characteristics(Ready-on-Write,1Wait State) (163)

6-46Synchronous XREADY Timing Requirements(Ready-on-Write,1Wait State) (163)

6-47Asynchronous XREADY Timing Requirements(Ready-on-Write,1Wait State) (163)

6-48Timing Requirements(XCLKOUT=XTIMCLK) (167)

6-49XHOLD/XHOLDA Timing Requirements(XCLKOUT=1/2XTIMCLK) (168)

6-50ADC Electrical Characteristics(over recommended operating conditions) (169)

6-51ADC Power-Up Delays (170)

6-52Typical Current Consumption for Different ADC Configurations(at25-MHz ADCCLK) (170)

8List of Tables Copyright?2007–2012,Texas Instruments Incorporated 芯天下--63bca34d312b3169a451a478/

TMS320F28335,TMS320F28334,TMS320F28332

TMS320F28235,TMS320F28234,TMS320F28232 63bca34d312b3169a451a478 SPRS439M–JUNE2007–REVISED AUGUST2012 6-53Sequential Sampling Mode Timing (172)

6-54Simultaneous Sampling Mode Timing (173)

6-55McBSP Timing Requirements (175)

6-56McBSP Switching Characteristics (176)

6-57McBSP as SPI Master or Slave Timing Requirements(CLKSTP=10b,CLKXP=0) (178)

6-58McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=10b,CLKXP=0) (178)

6-59McBSP as SPI Master or Slave Timing Requirements(CLKSTP=11b,CLKXP=0) (179)

6-60McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=11b,CLKXP=0) (179)

6-61McBSP as SPI Master or Slave Timing Requirements(CLKSTP=10b,CLKXP=1) (180)

6-62McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=10b,CLKXP=1) (180)

6-63McBSP as SPI Master or Slave Timing Requirements(CLKSTP=11b,CLKXP=1) (181)

6-64McBSP as SPI Master or Slave Switching Characteristics(CLKSTP=11b,CLKXP=1) (181)

6-65Flash Endurance for A and S Temperature Material (182)

6-66Flash Endurance for Q Temperature Material (182)

6-67Flash Parameters at150-MHz SYSCLKOUT (182)

6-68Flash/OTP Access Timing (182)

6-69Flash Data Retention Duration (182)

6-70Minimum Required Flash/OTP Wait-States at Different Frequencies (183)

9-1Thermal Model176-Pin PGF Results (187)

9-2Thermal Model176-Pin PTP Results (187)

9-3Thermal Model179-Ball ZHH Results (187)

9-4Thermal Model176-Ball ZJZ Results (188)

Copyright?2007–2012,Texas Instruments Incorporated List of Tables9芯天下--63bca34d312b3169a451a478/

TMS320F28335,TMS320F28334,TMS320F28332

TMS320F28235,TMS320F28234,TMS320F28232

SPRS439M–JUNE2007–REVISED 63bca34d312b3169a451a478

Digital Signal Controllers(DSCs)

Check for Samples:TMS320F28335,TMS320F28334,TMS320F28332,TMS320F28235,TMS320F28234,TMS320F28232

1TMS320F2833x,TMS320F2823x DSCs

1.1Features

?High-Performance Static CMOS Technology?Enhanced Control Peripherals –Up to150MHz(6.67-ns Cycle Time)–Up to18PWM Outputs

– 1.9-V/1.8-V Core,3.3-V I/O Design–Up to6HRPWM Outputs With150ps MEP

Resolution

?High-Performance32-Bit CPU(TMS320C28x)

–Up to6Event Capture Inputs –IEEE-754Single-Precision Floating-Point

Unit(FPU)(F2833x only)–Up to2Quadrature Encoder Interfaces –16x16and32x32MAC Operations–Up to832-Bit Timers

(6for eCAPs and2for eQEPs)–16x16Dual MAC

–Up to916-Bit Timers

–Harvard Bus Architecture

(6for ePWMs and3XINTCTRs)–Fast Interrupt Response and Processing

?Three32-Bit CPU Timers –Unified Memory Programming Model

?Serial Port Peripherals

–Code-Efficient(in C/C++and Assembly)

–Up to2CAN Modules

?Six-Channel DMA Controller(for ADC,McBSP,

–Up to3SCI(UART)Modules ePWM,XINTF,and SARAM)

–Up to2McBSP Modules(Configurable as ?16-Bit or32-Bit External Interface(XINTF)

SPI)

–Over2M x16Address Reach

–One SPI Module

?On-Chip Memory

–One Inter-Integrated-Circuit(I2C)Bus –F28335,F28235:

?12-Bit ADC,16Channels

256K x16Flash,34K x16SARAM

–80-ns Conversion Rate –F28334,F28234:

128K x16Flash,34K x16SARAM–2x8Channel Input Multiplexer –F28332,F28232:–Two Sample-and-Hold

64K x16Flash,26K x16SARAM–Single/Simultaneous Conversions –1K x16OTP ROM–Internal or External Reference

?Boot ROM(8K x16)?Up to88Inpidually Programmable,–With Software Boot Modes(via SCI,SPI,Multiplexed GPIO Pins With Input Filtering CAN,I2C,McBSP,XINTF,and Parallel I/O)?JTAG Boundary Scan Support(1)–Standard Math Tables?Advanced Emulation Features

?Clock and System Control–Analysis and Breakpoint Functions –Dynamic PLL Ratio Changes Supported–Real-Time Debug via Hardware

–On-Chip Oscillator?Development Support Includes

–Watchdog Timer Module–ANSI C/C++Compiler/Assembler/Linker ?GPIO0to GPIO63Pins Can Be Connected to–Code Composer Studio?IDE One of the Eight External Core Interrupts–DSP/BIOS?

?Peripheral Interrupt Expansion(PIE)Block That–Digital Motor Control and Digital Power Supports All58Peripheral Interrupts Software Libraries

?128-Bit Security Key/Lock

–Protects Flash/OTP/RAM Blocks

–Prevents Firmware Reverse Engineering

(1)IEEE Standard1149.1-1990Standard Test Access Port and

Boundary Scan Architecture

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar BGA,Code Composer Studio,DSP/BIOS,TMS320C28x,Delfino,PowerPAD,TMS320C54x,TMS320C55x,C28x

are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.Products conform to Copyright?2007–2012,Texas Instruments Incorporated

specifications per the terms of the Texas Instruments standard warranty.Production

processing does not necessarily include testing of all parameters.

芯天下--63bca34d312b3169a451a478/

TMS320F28335,TMS320F28334,TMS320F28332

TMS320F28235,TMS320F28234,TMS320F28232 63bca34d312b3169a451a478 SPRS439M–JUNE2007–REVISED AUGUST2012

?Low-Power Modes and Power Savings?Temperature Options:

–IDLE,STANDBY,HALT Modes Supported–A:–40°C to85°C(PGF,ZHH,ZJZ)

–Disable Inpidual Peripheral Clocks–S:–40°C to125°C(PTP,ZJZ)?Endianness:Little Endian–Q:–40°C to125°C(PTP,ZJZ)

?Package Options:

–Lead-free,Green Packaging

–Low-Profile Quad Flatpack(PGF,PTP)

–MicroStar BGA?(ZHH)

–Plastic BGA(ZJZ)

1.2Getting Started

This section gives a brief overview of the steps to take when first developing for a C28x device.For more detail on each of these steps,see the following:

?Getting Started With TMS320C28x Digital Signal Controllers(literature number SPRAAM0).

?C2000Getting Started Website(63bca34d312b3169a451a478/c2000getstarted)

?TMS320F28x DSC Development and Experimenter's Kits(63bca34d312b3169a451a478/f28xkits)

Copyright?2007–2012,Texas Instruments Incorporated TMS320F2833x,TMS320F2823x DSCs11

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TMS320F28335,TMS320F28334,TMS320F28332

TMS320F28235,TMS320F28234,TMS320F28232

SPRS439M–JUNE2007–REVISED 63bca34d312b3169a451a478 2Introduction

The TMS320F28335,TMS320F28334,TMS320F28332,TMS320F28235,TMS320F28234,and TMS320F28232devices,members of the TMS320C28x?/Delfino?DSC/MCU generation,are highly integrated,high-performance solutions for demanding control applications.

Throughout this document,the devices are abbreviated as F28335,F28334,F28332,F28235,F28234, and F28232,respectively.Table2-1and Table2-2provide a summary of features for each device.

Table2-1.F2833x Hardware Features

FEATURE TYPE(1)F28335(150MHz)F28334(150MHz)F28332(100MHz)

Instruction cycle– 6.67ns 6.67ns10ns

Floating-point Unit–Yes Yes Yes

3.3-V on-chip flash(16-bit word)–256K128K64K

Single-access RAM(SARAM)(16-bit word)–34K34K26K

One-time programmable(OTP)ROM

–1K1K1K

(16-bit word)

Code security for on-chip

–Yes Yes Yes

flash/SARAM/OTP blocks

Boot ROM(8K x16)–Yes Yes Yes

16/32-bit External Interface(XINTF)1Yes Yes Yes

6-channel Direct Memory Access(DMA)0Yes Yes Yes

PWM outputs0ePWM1/2/3/4/5/6ePWM1/2/3/4/5/6ePWM1/2/3/4/5/6

ePWM1A/2A/3A/4A/5A/

HRPWM channels0ePWM1A/2A/3A/4A/5A/6A ePWM1A/2A/3A/4A

6A

32-bit Capture inputs or auxiliary PWM

0eCAP1/2/3/4/5/6eCAP1/2/3/4eCAP1/2/3/4 outputs

32-bit QEP channels(four inputs/channel)0eQEP1/2eQEP1/2eQEP1/2

Watchdog timer–Yes Yes Yes

No.of channels161616

12-Bit ADC MSPS212.512.512.5

Conversion time80ns80ns80ns

32-Bit CPU timers–333

Multichannel Buffered Serial Port

12(A/B)2(A/B)1(A) (McBSP)/SPI

Serial Peripheral Interface(SPI)0111

Serial Communications Interface(SCI)03(A/B/C)3(A/B/C)2(A/B)

Enhanced Controller Area Network(eCAN)02(A/B)2(A/B)2(A/B)

Inter-Integrated Circuit(I2C)0111

General Purpose I/O pins(shared)–888888

External interrupts–888

176-Pin PGF–Yes Yes Yes

176-Pin PTP–Yes Yes Yes Packaging

179-Ball ZHH–Yes Yes Yes

176-Ball ZJZ–Yes Yes Yes

A:–40°C to85°C–(PGF,ZHH,ZJZ)(PGF,ZHH,ZJZ)(PGF,ZHH,ZJZ)

Temperature S:–40°C to125°C–(PTP,ZJZ)(PTP,ZJZ)(PTP,ZJZ) options Q:–40°C to125°C

–(PTP,ZJZ)(PTP,ZJZ)(PTP,ZJZ) (Q100Qualification)

(1)A type change represents a major functional feature difference in a peripheral module.Within a peripheral type,there may be minor

differences between devices that do not affect the basic functionality of the module.These device-specific differences are listed in the

12Introduction Copyright?2007–2012,Texas Instruments Incorporated

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Table2-1.F2833x Hardware Features(continued)

FEATURE TYPE(1)F28335(150MHz)F28334(150MHz)F28332(100MHz)

Product status(2)–TMS TMS TMS

(2)See Section5.1,Device and Development Support Tool Nomenclature,for descriptions of device stages.

Table2-2.F2823x Hardware Features

FEATURE TYPE(1)F28235(150MHz)F28234(150MHz)F28232(100MHz)

Instruction cycle– 6.67ns 6.67ns10ns

Floating-point Unit–No No No

3.3-V on-chip flash(16-bit word)–256K128K64K

Single-access RAM(SARAM)(16-bit

–34K34K26K

word)

One-time programmable(OTP)ROM

–1K1K1K

(16-bit word)

Code security for on-chip

–Yes Yes Yes

flash/SARAM/OTP blocks

Boot ROM(8K x16)–Yes Yes Yes

16/32-bit External Interface(XINTF)1Yes Yes Yes

6-channel Direct Memory Access(DMA)0Yes Yes Yes

PWM outputs0ePWM1/2/3/4/5/6ePWM1/2/3/4/5/6ePWM1/2/3/4/5/6

HRPWM channels0ePWM1A/2A/3A/4A/5A/6A ePWM1A/2A/3A/4A/5A/6A ePWM1A/2A/3A/4A

32-bit Capture inputs or auxiliary PWM

0eCAP1/2/3/4/5/6eCAP1/2/3/4eCAP1/2/3/4 outputs

32-bit QEP channels(four inputs/channel)0eQEP1/2eQEP1/2eQEP1/2

Watchdog timer–Yes Yes Yes

No.of channels161616

12-Bit ADC MSPS212.512.512.5

Conversion time80ns80ns80ns

32-Bit CPU timers–333

Multichannel Buffered Serial Port

12(A/B)2(A/B)1(A) (McBSP)/SPI

Serial Peripheral Interface(SPI)0111

Serial Communications Interface(SCI)03(A/B/C)3(A/B/C)2(A/B)

Enhanced Controller Area Network

02(A/B)2(A/B)2(A/B) (eCAN)

Inter-Integrated Circuit(I2C)0111

General Purpose I/O pins(shared)–888888

External interrupts–888

176-Pin PGF–Yes Yes Yes

176-Pin PTP–Yes Yes Yes Packaging

179-Ball ZHH–Yes Yes Yes

176-Ball ZJZ–Yes Yes Yes

A:–40°C to85°C–(PGF,ZHH,ZJZ)(PGF,ZHH,ZJZ)(PGF,ZHH,ZJZ)

S:–40°C to125°C–(PTP,ZJZ)(PTP,ZJZ)(PTP,ZJZ) Temperature options Q:–40°C to125°C

(Q100–(PTP,ZJZ)(PTP,ZJZ)(PTP,ZJZ)

Qualification)

Product status(2)–TMS TMS TMS

(1)A type change represents a major functional feature difference in a peripheral module.Within a peripheral type,there may be minor

differences between devices that do not affect the basic functionality of the module.These device-specific differences are listed in the TMS320x28xx,28xxx DSP Peripheral Reference Guide(literature number SPRU566)and in the peripheral reference guides.

(2)See Section5.1,Device and Development Support Tool Nomenclature,for descriptions of device stages.

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GPIO33/SCLA/EPWMSYNCO/ADCSOCBO GPIO32/SDAA/EPWMSYNCI/ADCSOCAO GPIO19//SCIRXDB/CANTXA SPISTEA G P I O 75/X D 4G P I O 74/X D 5G P I O 73/X D 6G P I O 72/X D 7G P I O 71/X D 8G P I O 70/X D 9V D D V S S G P I O 69/X D 10G P I O 68/X D 11G P I O 67/X D 12V D D I O V S S G P I O 66/X D 13V S S V D D G P I O 65/X D 14G P I O 64/X D 15G P I O 63/S C I T X D C /X D 16G P I O 62/S C I R X D C /X D 17G P I O 61/M F S R B /X D 18G P I O 60/M C L K R B /X D 19G P I O 59/M F S R A /X D 20V D D V S S V D D I O V S S X C L K I N X 1V S S X 2V D D G P I O 58/M C L K R A /X D 21G P I O 57/X D 22S P I S T E A G P I O 56/S P I C L K A /X D 23G P I O 55/S P I S O M I A /X D 24G P I O 54/S P I S I M O A /X D 25G P I O 53/E Q E P 1I /X D 26G P I O 52/E Q E P 1S /X D 27V D D I O V S S G P I O 51/E Q E P 1B /X D 28G P I O 50/E Q E P 1A /X D 29G P I O 49/E C A P 6/X D 30

G P I O 30/G P I O 29/S G P G P I O 1/E P W M 1B /E G P G P I O 3/E P W M 2B /E C G P G P I O 5/E P W M 3B /G P I O 6/E P W M 4A /E P W M S Y N C I /G P I O 7/E P W M 4B /M G P I O 8/E P W M 5A /C A N T X G P I O 9/E P W M 5B /S C I G P I O 10/E P W M 6A /C A N R X G P I O 11/E P W M 6B /S C I G P I O 12/C /T Z 1G P I O 13//C T Z 2G P I O 14//X H O L D /T Z 3S C I T G P I O 15//X H O L D A T Z 4/S C I G P I O 16/S P I S I M O A G P I O 17/S P I S O M I A /GPIO28/SCIRXDA/XZCS6TMS320F28335,TMS320F28334,TMS320F28332TMS320F28235,TMS320F28234,TMS320F28232

SPRS439M –JUNE 2007–REVISED AUGUST 2012

63bca34d312b3169a451a478

2.1Pin Assignments

The 176-pin PGF/PTP low-profile quad flatpack (LQFP)pin assignments are shown in Figure 2-1.The 179-ball ZHH ball grid array (BGA)terminal assignments are shown in Figure 2-2through Figure 2-5.The 176-ball ZJZ plastic ball grid array (PBGA)terminal assignments are shown in Figure 2-6through Figure 2-9.Table 2-3describes the function(s)of each pin.

Figure 2-1.F2833x,F2823x 176-Pin PGF/PTP LQFP (Top View)

NOTE

The powerpad on the bottom side of the PTP package is not connected to the ground (GND)of the die.Proper thermal management of the PowerPAD?package requires PCB preparation.A thermal land is required on the surface of the PCB directly underneath the body of the PowerPAD package.The size of the thermal land should be as large as needed to dissipate the required heat.Note that the PowerPAD package with exposed pad down must be soldered to the PCB.Refer to the PowerPAD?Thermally Enhanced Package Application Report (literature number SLMA002)for more details on using the PowerPAD package.

14

Introduction

Copyright ?2007–2012,Texas Instruments Incorporated

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P N M L K J H 1234567

TMS320F28335,TMS320F28334,TMS320F28332

TMS320F28235,TMS320F28234,TMS320F28232

63bca34d312b3169a451a478 SPRS439M–JUNE2007–REVISED AUGUST2012

Figure2-2.F2833x,F2823x179-Ball ZHH MicroStar BGA?(Upper Left Quadrant)(Bottom View) Copyright?2007–2012,Texas Instruments Incorporated Introduction15

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P

N

M

L

K

J

H

891011121314TMS320F28335,TMS320F28334,TMS320F28332TMS320F28235,TMS320F28234,TMS320F28232

SPRS439M –JUNE 2007–REVISED AUGUST 2012

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Figure 2-3.F2833x,F2823x 179-Ball ZHH MicroStar BGA?(Upper Right Quadrant)(Bottom View)

16Introduction Copyright ?2007–2012,Texas Instruments Incorporated

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G

F

E

D C

B A

1

2

34567

TMS320F28335,TMS320F28334,TMS320F28332TMS320F28235,TMS320F28234,TMS320F28232

63bca34d312b3169a451a478

SPRS439M –JUNE 2007–REVISED AUGUST 2012

Figure 2-4.F2833x,F2823x 179-Ball ZHH MicroStar BGA?(Lower Left Quadrant)(Bottom View)

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891011121314G F E D C B A

TMS320F28335,TMS320F28334,TMS320F28332

TMS320F28235,TMS320F28234,TMS320F28232

SPRS439M–JUNE2007–REVISED 63bca34d312b3169a451a478 Figure2-5.F2833x,F2823x179-Ball ZHH MicroStar BGA?(Lower Right Quadrant)(Bottom View)

18Introduction Copyright?2007–2012,Texas Instruments Incorporated

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P N M L K J H 1234567

TMS320F28335,TMS320F28334,TMS320F28332

TMS320F28235,TMS320F28234,TMS320F28232

63bca34d312b3169a451a478 SPRS439M–JUNE2007–REVISED AUGUST2012

Figure2-6.F2833x,F2823x176-Ball ZJZ Plastic BGA(Upper Left Quadrant)(Bottom View) Copyright?2007–2012,Texas Instruments Incorporated Introduction19

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P

N

M

L

K

J

H

89101112

1314

TMS320F28335,TMS320F28334,TMS320F28332TMS320F28235,TMS320F28234,TMS320F28232

SPRS439M –JUNE 2007–REVISED AUGUST 2012

63bca34d312b3169a451a478

Figure 2-7.F2833x,F2823x 176-Ball ZJZ Plastic BGA (Upper Right Quadrant)(Bottom View)

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G

F E

D

C

B A 1234567

TMS320F28335,TMS320F28334,TMS320F28332TMS320F28235,TMS320F28234,TMS320F28232

63bca34d312b3169a451a478

SPRS439M –JUNE 2007–REVISED AUGUST 2012

Figure 2-8.F2833x,F2823x 176-Ball ZJZ Plastic BGA (Lower Left Quadrant)(Bottom View)

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