Verdi_HWSW_Debug_Customer_Presentation

Verdi 教程

Verdi HW/SW DebugEmbedded Software DebugVerification GroupJuly 2013© Synopsys 20131Synopsys Confidential

Verdi 教程

LegalCONFIDENTIAL INFORMATION The following material is being disclosed to you pursuant to a nondisclosure agreement between you or your employer and Synopsys. Information disclosed in this presentation may be used only as permitted under such an agreement. LEGAL NOTICE Information contained in this presentation reflects Synopsys plans as of the date of this presentation. Such plans are subject to completion and are subject to change. Products may be offered and purchased only pursuant to an authorized quote and purchase order. Synopsys is not obligated to develop the software with the features and functionality discussed in the materials.© Synopsys 20132Synopsys Confidential

Verdi 教程

SoC Debug ChallengesNeed a Programmers view of the CPUCPU Software Debug Encrypted Model ? Registers + Nets ? No or Low-Visibility Looks like a Black Box Need Software DebuggerUSB VIP CPU (RTL) SoC Simulation CPU (RTL) Memory Model Memory Image arm-gcc C CodeInterconnect Fabric User Block (C/DPI) User Logic (RTL)USB IIPProtocol Analyzer VIP Debug© Synopsys 2013 3Verdi Debug C (PLI & DPI)Synopsys ConfidentialVerdi Debug RTL, Testbench

Verdi 教程

HW/SW DebugEmbedded Processor Debug with Synchronized RTL, C, Assembly Enables co-debug between RTL and SW HW and SW debug synchronized in time View C/Assembly source, C variables, stack Debugs multiple core simultaneously Supports ARM A5, A7, A8, A9, A15, M3 Easy to support additional coresCPU (RTL) Mem Model Mem Image Programmer’s ViewX-Bar (RTL)USB Host IIPApplication Logic (RTL)SoC SimulationFull Verdi Features© Synopsys 20134Confidential

Verdi 教程

HW/SW Debug Use ModelsVerification environment with C-tests Part of SoC verification schedule Hardware debug with C tests / stimulus C tests may have minimal OS or boot code Requires concurrent software and hardware debug Use HW/SW Debug for this task Prepare for First Silicon Bring-Up Debug synthetic tests mimic specific use scenarios Tests run on a bare-metal OS Develop and bug tests on a pre-silicon model Get ready for silicon bring up Use HW/SW Debug for this task Driver Development Software (driver) development Fast speed is required (1MHz +) Approximate hardware is acceptable Use Virtualizer for this task Use HW/SW-Accel for this task First Silicon Debug Observed failure running test on first silicon Debug the failure and isolate a design bug Create/Validate software/firmware workaroundUse HW/SW Debug for this task© Synopsys 20135Synopsys Confidential

Verdi 教程

SW Debug in Eclipse UIProvides programmers view of code on RTL CPUCall StackRegistersVariablesC Source Code© Synopsys 2013 6Assembly CodeSynopsys ConfidentialMemory View

Verdi 教程

Post-Process DebugEclipse/CDT for SW debug Step forward, into, out, backBi-Directional time synchronization between RTL & programmer viewsEnable/Disable BreakpointsUp/Down CallstackExisting VerdiHW debug Features© Synopsys 2013 7Synchronized RTL time cursor (bi-directional)Synopsys ConfidentialAdvance forward/backward to C breakpoints

Verdi 教程

Multi-Core DebugMultiple cores with program and call stack Register view pinned to cpu0Provides programmers views into multiple core simultaneouslyRegister view pinned to cpu1If a Register view is not pinned, it shows the selected coreC Source Code of the selected core© Synopsys 2013 8Assembler Source Code of the selected coreSynopsys Confidential

Verdi 教程

Embedded HW/SW DebuggingInteractive and Post Process Debug FlowEclipse CDTSoC Design FilesRecorder modulesC SrcVerdigdb armcc gccVCSHW/SW DebugsimvELF filesTarmacFSDBVCS CompileC-CompileNew HW/SW Debug Components Existing C/Customer ComponentsRuntimesimv© Synopsys 20139Synopsys Internal Only/Confidential

Verdi 教程

HW/SW ModularizationDATA GATHERING Core register Program counter Flag register (CPSR, …) DATA STORING Record data for non-linear access in interactive and post process flows 10x smaller in fsdb ENGINE Communicate with gdb Access data VIZUALIZATION SW debug HW debug HW/SW debug syncVerilog recorder modules ARM TARMAC (RTL and ISS) Custom Cores XMR Log-Filegdbcore targetedSW debugEclipse CDTFSDB HW-SW Core HW debugVerdiVerdi Platform© Synopsys 201310Synopsys Confidential

Verdi 教程

Zebu+HW/SW Debug Planned IntegrationZebu Zebu– Dump PC + Registers into FSDB File Add Recorder + Cross-Module references VCS Co-Simulation with probes for TARMAC Post-Process Debug– Use standard HW/SW Post-Process FlowFSDB+© Synopsys 201311Synopsys Confidential

Verdi 教程

HW/SW-Accel : ISS/Fast Model CoresAccurate RTL SimulationTradeoffFast ISS + RTL SimulationARM RTL (Verilog)ARM RTL (Verilog) Soc FabricARM FM (C / ISS)TLM TransactorARM FM (C / ISS)TLM TransactorSoc Fabric Mem/Denali/… Memory BackdoorMem/Denali/…SocSoc RTL Core Solution– – – RTL or DSM Model TARMAC based (ARM cores) Log or XMR based (non ARM cores) ISS Core Solution– – – Replace RTL or DSM with ISS Model DW-VIP Models for AXI/Fabric BFM’s ISS runs faster than RTL, faster performance Accurate Simulation– – Real RTL, cycle accurate RTL Speed, not suitable for OS boot Faster Simulation– – – Memory Access via Backdoor or Fabric Backdoor allows boot of OS Access peripherals via fabric as needed© Synopsys 201312Synopsys Confidential

Verdi 教程

Verdi HW/SW Debug Release Schedule2013 Q2Beta Release Verdi 13.04 Patch 2 Processor Support ARM M3, A7, A8, A9, A15 Custom cores as needed Features Eclipse CDT debug C/ASM source views C Variables C Stack C/RTL Breakpoints Step forward/backward Synchronized time-view Post Process Mode OnlyVerdi 2013.07Processor Support ARM A5, R5 Based on Customer Needs Custom cores as needed Features Multi-Core Debug V1 Shared memory for all cores Breakpoints per active coreVerdi 2013.10Processor Support ARM v8 cores (A50 series) Based on Customer Needs Custom cores as needed Features Multi-Core Debug V2 Cluster/Memory config Global break-pointing Improved launch/sync options Interactive Mode V1© Synopsys 201313Synopsys Confidential

Verdi 教程

Verdi HW/SW Debug - InstallationTarmac Migrate design to VCS 2012.09 or later Dump Tarmac trace from your designInstall Download & Install Verdi 2013.04-Patch-2 & Latest HWSW-Patch Run Dhrystone Example to verify installation Instantiate HwSw-Debug Recorder Module Recorders Run Simulation & Verify values are stored in FSDB fileDebug Invoke Verdi + HWSW-Debug/Eclipse Debug your design© Synopsys 201314Synopsys Confidential

Verdi 教程

Verdi HW/SW DebugEmbedded Software DebugVerification GroupJuly 2013© Synopsys 201315Synopsys Confidential

Verdi 教程

Recorder Modules – Trace Log BasedSimulation Recorder Module Writes instruction trace FSDB Reads back trace Simulation writes out instruction trace Recorder instance reads back the trace and extracts the information Recorder instances stores extracted information in FSDBInstruction TraceHW/SW DebugProvided based on TARMAC for ARM Cortex A5, A7, A8, A9, A15, M3, R5 Recorder can be implemented based on custom instruction traces.© Synopsys 2013 16Synopsys Confidential

Verdi 教程

Recorder Modules – XMR/Logic BasedSimulation Recorder Module FSDB Recorder instance extracts the information based on XMRs (cross module references) and logic codeHW/SW Debug`define CPU_top minitb.cpu_inst reg [31:0] pc; wire[31:0] core_regs[0:14]; wire CLK; wire [31:1] ETMIA; wire [25:0] ETMICTL; … (more definitions here) assign core_regs[0] = `CPU_top.uix.regfile.reg00; …assign CLK=`CPU_top.uix.ck_gclkc; assign ETMICTL = `CPU_top.uix.ETMICTL; assign ETMIA = { `CPU_top.uix.ETMIA, 1'b0 }; … (more assignments here) always @(ETMIA or ETMICTL) begin if (ETMICTL[0]) pc = ETMIA; else pc = {32{1'bx}}; endSynopsys Confidential© Synopsys 201317

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