3 - Hardware - Verification - of - a - Hpyer-Efficient - Kasper - APEC - 2015 - 01 - 图文
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? 2015 IEEE
Proceedings of the 30th Applied Power Electronics Conference and Exposition (APEC 2015), Charlotte, NC, USA, March 15-19, 2015.
Hardware Verification of a Hyper-Efficient (98%) and Super-Compact (2.2kW/dm3) Isolated AC/DCTelecom Power Supply Module based on Multi-Cell Converter Approach
M. KasperC. W. ChenD. BortisJ. W. KolarG. Deboy
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HardwareVeri?cationofaHyper-Ef?cient(98%)andSuper-Compact(2.2kW/dm3)IsolatedAC/DCTelecomPowerSupplyModulebasedonMulti-Cell
ConverterApproach
MatthiasKasper?,Cheng-WeiChen?,DominikBortis?,JohannW.Kolar?andGeraldDeboy??PowerElectronicSystemsLaboratory,ETHZurich,Switzerland,Email:kasper@lem.ee.ethz.ch
?ElectricEnergyProcessingLaboratory,NationalTaiwanUniversity,Taipei,Taiwan
?In?neonTechnologiesAustriaAG,Villach,Austria
Abstract—Duetotheincreasingelectricitydemandofdatacentersdrivenbytheemergenceofcloudcomputingandbigdata,thefocusonthedevelopmentoftelecomanddatacenterpowersuppliesisshiftedtowardshighef?ciencies.Inthispaper,amulti-cellconverterapproachforatelecomrecti?ermodulebreakingthroughtheef?ciencyandpowerdensitybarriersoftraditionalsingle-cellconvertersystemsisshown.Thecom-prehensiveoptimizationoftheentiresystemwithrespecttoef?ciencyandvolumeisdescribedandtheappliedcomponentlossmodelsareexplained.Furthermore,thedesignofahardwaredemonstratorbasedontheoptimizationresultsispresentedandseveralimportantdesignaspectsareexplainedindetail.
LgConverter CellACDCACDCDCDCDCDCVout
Vg
vFB,totACDCACDCDCDC=??
VDC,iI.INTRODUCTION
Duetotheincreasingpopularityofcloudbasedinternet
servicesandthetrendaroundbigdata,theelectricityconsump-tionofdatacentershasgrowntremendouslyinthepastdecadeandisprojectedtogrowinthefutureevenfurther,e.g.around70%from2013to2020intheUSalone[1].Asaconsequence,datacentersarenowoneofthelargestconsumersofelectricityandthereforealsounderagrowing?nancialandpoliticalpressuretoincreasetheirenergyef?ciency.
Nowadays,conventionalsingle-phasetelecompowersuppliestypicallyconsistofaPFCrecti?erstageinconnectionwithanisolatedDC-DCconverterstageinordertogenerateanoutputvoltageof48Vforthesubsequentconversionstages.Therecti?erstageisusuallyaboost-typePFCconverterwithafullbridgedioderecti?er,thatcreatesconsiderableconductionlossesduetotheforwardvoltagedropsoftheemployeddiodes.Thishasinitiatedatrendtowardsbridge-lesstopologiesasanalternativetopology[2],[3].Oneexampleofahighlyef?cientpowersupplyfortelecomapplicationsisatriple-parallel-interleavedTCMPFCrecti?ersystem[4]incombinationwithadouble-parallel-interleavedphase-shiftedfull-bridgeisolatedDC-DCconverter(ratedpowerPout=3.3kW,outputvoltageVout=48V)featuringapowerdensityofρ=3.3kW/dm3andanef?ciencyofη=97%athalfoftheratedpower.Asshownin[5],thisconceptcurrentlypresentstheleadingedgetechnologyfortelecompowersupplies.
Anewandverydifferentapproachtowardsahyper-ef?cient
DCDC=??
Fig.1:Multi-celltelecompowersupplymodulewithinput-series
output-parallelconnectionoftheconvertercells.EachcellconsistsofafullbridgeAC-DCrecti?erinputstageandanisolatedDC-DCconvertercomprisingaphase-shiftedfull-bridgeconverter.
andsuper-compacttelecomrecti?erdesignbeyondthebarriersoftraditionalconverterconceptshasbeenpresentedin[6].Theapproachisbasedonamulti-cellconverterconceptwithseriesconnectionoftheconvertercellsattheinputsideandparallelconnectionattheoutputside(i.e.ISOP),asshowninFig.1.EachconvertercellformedbyanAC-DCrecti?erstageswhichisoperatedwithaTotem-PolemodulationandanisolatedDC-DCconverterstageconsistingofphase-shiftedfullbridgeconverter.Thismulti-cellISOPcon?gurationallowstosharetheinputvoltageamongtheconvertercellsandthusenablestheuseoflow-voltageratedsemiconductorsthroughouttheconvertercells.Accordingtothescalinglawsof[7]withthisapproachsigni?cantbene?tsintermsofreducedconductionandswitchinglossesandsmallervolumeofinductivecompo-nentsandheatsinks,amongothers,canbeachieved.Basedonthespeci?cationofTab.Ithesystemperformancetargetsthatshouldbereachedbyutilizingtheadvantagesofthemulti-cellconvertertopologyareanoutputpowerofPout=3.3kWwith
Tab.I:Speci?cationsofthemulti-celltelecomrecti?ermodule.
Parameter
VariableValue
NominalgridvoltageVgrid,RMS,nom230V/50HzGridvoltagerangeVgrid,RMS180V-270VRatedoutputpowerPout3.3kWNominaloutputvoltageVout,nom48VOutputvoltagerangeVout40V-60VTotalDC-linkvoltageVDC400V
Hold-uptime
Thold10ms@ratedpower
Switchingfreq.percellfsw
≥18kHz
EMIstandards
CISPRClassAandB
aconversionef?ciencyof98%atpartloadoperationandapowerdensityofρ=2.2kW/dm3.
Inthispaper,at?rsttheoptimizationandofthesystemisdiscussedindetailandtheresultsareanalyzedinSec.II.Afterwards,therealizationofthehardwaredemonstratorisdescribedinSec.IIIanddifferentdesignaspectsareaddressed.Finally,conclusionsaredrawninSec.IV.
II.SYSTEMOPTIMIZATIONANDRESULTS
In[7]acomprehensivesystemmodelingandoptimizationintermsofef?ciencyandpowerdensityoftheISOPmulti-celltelecomrecti?ermodulehasbeenpresented.InthisoptimizationallavailabledegreesoffreedomforthedesignoftheAC-DCandtheDC-DCconverterstageshavebeenconsideredsuchas
?SwitchingoftheAC-DCfrequencyrecti?er:Thestageeffectiveequalsswitchingtheswitchingfrequencyfre-quencyofasinglecellmultipliedbythenumberofcellsduetheinterleavedoperationoftherecti?erstages,i.e.fsw,eff=Ncells·fsw.Anaturallowerlimitoftheswitchingfrequencyofasinglecellcanbedeductedfromtherangeofaudiblefrequencywhichshouldbeavoidedbychoosingfsw≥18kHz.TheupperboundaryoffeasibleswitchingfrequenciescanbederivedbytheCISPREMIstandardsthatimposelimitsonharmonicsatfrequenciesabovefEMI≥150kHz[8].Asaconsequencetheswitchingfrequencypercellshouldbelimitedtofsw ?MOSFETsizeofthechipMOSFETssizeandisjunctionanimportanttemperatureparameter:Theforchipthetrade-offbetweenconductionandswitchinglosses[4],asgivenfortheAC-DCstagewhichisoperatedunderhard-switching.Furthermore,thethermalresistancebetweenthejunctionandthecaseofthesemiconductorchangeswiththechipsize,whichalsoin?uencesthedesignandvolumeoftheheatsink. η / ?98.5N=798N=697.5N=8N=59796.5Selected Designρ / kW96dm3012345Fig.2:Pareto-optimal(ef?ciency/power-density)designsofthemulti-celltelecompowersupplymodulefordifferentnumbersofconvertercellsandadropoftheDC-linkvoltageduringthehold-uptimeofkDC,drop=20%. ? DC-linkemployedcapacitorDC-linkrealizationcapacitors:offersThesizeantrade-offandtypebetweenofthetheoverallvolumeoftheDC-linkcapacitorsandthelossescausedbytheequivalentseriesresistance(ESR).Theseparameters,amongothers,aresubjecttoatrade-offbetweenthepower-densityandtheef?ciencyoftheentiresystem.Therefore,forallcombinationsofdesignparametersthesystemperformancehastobedeterminedbyemployingcomponentlossandvolumemodels. Thevolumesoftheconverterdesignshavebeendeterminedbyconsideringthesumofallcomponentboxedvolumes,suchasthevolumeofthe?DC-linkInductivecapacitors?EMI?ltercomponents?sink. components?HeatThevolumeofPCBsandcontrolelectronicshavenotbeenconsideredsincetheyarelayoutdependentandthusnotavail-ablefortheoptimization.Forthecalculationoftheconversionef?ciencyfollowinglosseshavebeenincluded:?AC-DCFull-bridgeMOSFETs –Switchinglosses–Conductionlosses–Gatedrivelosses ?Phase-shiftedFull-bridgeMOSFETs –Conductionlosses–Gatedrivelosses ?Synchronousrecti?erMOSFETs –Conductionlosses –Reverserecoverylosses–Gatedrivelosses?Inductivecomponents –Corelosses –Windinglosses(incl.HF-losses). Inaddtion,thelossescausedbytheequivalentseriesresistanceoftheelectrolyticcapacitorsandconstantlossescausedbyauxiliaryandcontrolelectronicshavebeenincluded.Designspeci?clossessuchastheconductionlossesofthePCBhavebeenomittedinthecalculationastheyvarywiththelayout.Asaresultofthiscomprehensivesystemoptimizationaclear η / ?98.59897.59796.59699.599.5kDC,drop=10 0@?.4599.499.3599.399.25kDC,drop=10 0@?98.59897.597kDC,drop=10 0@%ρ / kWdm325Full system01234599.2AC-DC Rectifier Stage0246896.5DC-DC Conversion Stage05101520Fig.3:ImpactofdifferentvaluesofthemaximumpermissibledropoftheDC-linkvoltageduringthehold-uptime,kDC,drop,ontheachievablePareto-optimalresultsoftheentiresystem,theAC-DCrecti?erstagesandtheDC-DCconverterstages. optimumcanbefoundforthenumberofemployedconvertercellsatNopt=6.Eventhoughthescalinglawsderivedin[7]predictabetterperformancewithincreasingnumberofcells,externalandotherpracticalconstraintsoutweighthebene?tsofalargercellnumber,suchasEMIlimitingstandardsbeginningatfEMI=150kHz,thepackageresistanceofMOSFETs,andcommunicationandcontroloverhead. Thetelecomsupplyisrequiredtofeatureahold-uptimeofThold=10ms(cf.Tab.Iforthefullsetofspeci?cations)whichnecessitateselectrolyticcapacitorswithineachcell.Thevoltagedropofthesecapacitorsduringthehold-uptimewasfoundtobeanotheroptimizationparametersthatexhibitsanoptimumatavalueofkDC,drop=20%. ThePareto-optimalresultsofthesystemoptimizationareshowninFig.2forfullloadoperationatthenominalop-eratingpointfordifferentnumbersofconvertercellsandamaximumpermissibledropoftheDC-linkvoltageduringthehold-uptimeofkDC,drop=20%. Thein?uenceofkDC,dropontheachievablesystemperformanceisdepictedinFig.3(a)fortheentiresystemandinFig.3(b)and(c)fortheAC-DCandDC-DCstage,respectively.InthecalculationstheelectrolyticDClinkcapacitorshavebeenallocatedtotheAC-DCconverter. III.HARDWAREDEMONSTRATORDESIGN Thedesignwhichisselectedforthehardwaredemonstratorwithacalculatedmaximumef?ciencyofη=98%at75%oftheratedoutputpowerandapowerdensityaboveρcalc=3kW/dm3ismarkedinFig.2.ThemainsystemparametersoftheselecteddesignarelistedinTab.II.ApictureoftheassembledprototypeisshowninFig.4whichfeaturesavolumeofVol=30.4cm·4.5cm·11cm=1.504dm3andthusanoverallpowerdensityofρsys=2.2kW/dm3.ThepowerdensityoftheprototypeislowerthanthecalculatedvaluesincethespacebetweenthecomponentsadverselyaffectstheachievablepowerdensityandthevolumeofthePCBandthecontrolboardshavenotbeenincludedinthecalculations.AdetailedbreakdownofthecalculatedlossesandvolumesisprovidedinFig.5forfullloadoperation. Inthefollowingparagraphsdifferentdesignaspectsoftheconvertersystemaredescribedindetail. Tab.II:MainsystemparametersoftheselecteddesignforthehardwaredemonstratorwithN=6convertercells.(Allvaluesgivenpercomponent,e.g.parallelMOSFETs,ifnototherwisenoted.) AC-DCrecti?er Switchingfrequencyfsw,cell=20kHz BoostinductanceAMCC-4,2605SA1,36μH,5turnsMOSFETs2xBSC046N10NS3G,100V,4.6m?DC-linkcap.4xPanasonicECO-S1KA222CA,alum.elect., 80V,2.2mF EMI?lter 3stages,2xcommonmodechokes (EPCOSR40coresT38,10turns),3x680nFDC-DCconverter Switchingfrequencyfsw=200kHz Transformerturnsratio7:7,ETD34/17/11,N87,EPCOS litzwire(600x71μm) Inductance ETD34/17/11,N87,EPCOS,20.5μHPrim.MOSFETsBSC046N10NS3G,100V,4.6m?Sec.MOSFETs BSC046N10NS3G,100V,4.6m? Phase-shiftedfullbridgeconverter Thephase-shiftedfullbridgeconverter(PSFB)withfullbridgesynchronousrecti?cation(SR)ischosenfortheisolatedDC-DCconverterstagesinceitallowstoachieveacomparablyhighef?ciencybyoperatingthesemiconductorsunderzero-voltageswitching(ZVS)andstillprovidesaneasywaytocontrolthepower?owbymeansofthephaseshiftbetweenthebridgelegsontheprimarysideataconstantswitchingfrequency.Foraproperoperationoftheconverter,however,certaindesignguidelineshavetobeconsidered[10].WhileZVScanbeachievedforthelagginglegoftheprimaryfullbridgeeasilybyutilizingboththeenergystoredintheoutputinductorandintheleakageinductorofthetransformer,theoperationoftheleadinglegwithZVSreliessolelyontheen-ergystoredintheleakageinductanceduringthefreewheelingphase E=12 Lσ2Lσ(ILoad·ntr+Imag) (1)Thisenergyhastobesuf?cienttocharge/dischargethepar-asiticoutputcapacitancesoftheMOSFETsintheleadingbridgeleg.AnenergyanalysisrevealsthatsoftswitchingcanonlybeachievediftheenergyELσislargerthantheenergywhichisfedbackintotheDCinputvoltageduringdischarge Inductor DC LinkCapacitorsControlBoard PowerBoard Transformer(a) DC LinkCapacitors SingleCell Increasingtheleakageinductanceevenfurtherforabroaderrangeofloadcurrentsforsoftswitchingwouldintroducethedrawbackofalargerdutycyclelosscausedbythetimerequiredtoreversethecurrentintheleakageinductancefrom(?ILoad·ntrafo)to(+ILoad·ntrafo)orviceversa,thusrenderingitasanunpracticalsolution. AnotherissueintheoperationofthePSFBisthevoltagering-ingatthesecondaryrecti?erMOSFETsafterthefreewheelingphase.TheringingiscausedbytheresonantcircuitcomprisingtheleakageinductanceLσofthetransformerandtheparasiticcapacitancesoftherecti?erMOSFETs(2·COSS)sincethevoltageacrosstheoutputrecti?erisdecoupledbytheoutputinductorfromtheoutputvoltageandthereforenotclampedtoa?xedvoltage(cf.Fig.6(b)).Theresonantfrequencyofthisresonantcircuitequals ?? (3)ωres=1/2CossLσn2trandthecharacteristicimpedanceamountsto ?? Zres=Lσn2tr/(2Coss). EMIFilterRelayCurrent Sensor BoostInductor ControlBoard PowerBoard (4) (b) Fig.4:Multi-cellsingle-phaseAC-DCtelecomrecti?erprototypewith6convertercellsinISOPcon?gurationforaratedpowerof3.3kWandapowerdensityofρ=2.2kW/dm3:(a)singlecelland(b)fullsystem(30.4cm·11cm·4.5cm/12in·4.3in·1.8in). ofthechargeequivalentcapacitanceofaMOSFET,i.e. 2.EC,sw=Coss,Qeq·VDC (2) Theworstcasevoltageovershootcanreachthevalueoftwice thetransformedprimaryvoltageVSR,peak=2Vsec=2ntrVDC,asshowninFig.6(d).Inthecaseatthehand,theDC-busvoltageineachcellequalsVDC=VDC,tot/Ncells=400V/6=66Vandwithatransfomerturnsratioofntr=1theworstcasevoltagespikecouldreacharoundVSR,peak=133Vwhichwouldleadtothedestructionofthesynchronousrecti?cationMOSFETswithavoltageratingofVDS,max=100V.Sincethediodesintherecti?erMOSFETsarepronetoreverserecoveryeffects,thevoltagespikeincreasesdependingonthepeakreverserecoverycurrentIRRandcanbecalculatedas ?? (5)VSR,pk=VDCntr+(VDCntr)2+(ZresIRR)2Inorderlimitthevoltagespikealoss-lesssnubbercircuit consistingofasnubbercapacitorCSnubandtwodiodesisaddedtotheconverter[11].Analternativesnubberthatworkswithanadditionaltransformerwindingcanbefoundin[12].Byintroducingthesnubbertheequivalentcircuitof Intheprototypeathand,theleakageinductanceofthetrans-formerwasselectedtobeLσ=1μHbyadjustingthewindingarrangement.Thisallowstoachievesoft-switchingintheleadinglegatlevelsoftheoutputcurrentaboveILoad≥3.4A(i.e.30%)accordingto(1)and(2). Auxiliary(3.0 W) Inductors(8.1 W)AC/DCstageMOSFETs (11.8 W)DC-linkcapacitors (6.4 W)Auxiliary(3.0 W) DC/DCstage Boost ind.(0.9 W)MOSFETs(17.2 W) Inductors(0.15 dm3) AC/DCstageTransformers(15.2 W) Transformers(0.21 dm3)DC-linkcapacitors (0.52 dm3) DC/DCstage Boost ind.(0.04 dm3)(a)(b) EMI filter(0.08 dm3) Fig.5:Calculatedbreak-downofthelosses(a)andthevolume(b)fortheselectedconverterdesignofthemulti-celltelecompowersupplymoduleatfullload. Snubber circuitLσ1:nCsnubtrV+-v+DCSR-Vout(a) n2trLσn2LCtrσsnubn+trV2C+DC vSR-OSSntrVDCvSR-2COSSVout (b) (c) Z i.ZresISRwithout withSnubberSnubberZres,snubISRvSR VoutntrVDCVSR,pk,sbVSR,pk(d) Fig.6:Phase-shiftedfullbridgeconverterwithover-voltagelimitingloss-lesssnubbercircuit[11]forthesecondaryrecti?erMOSFETs:(a)applicationofthesnubbercircuittotheconverter;(b)equivalentcircuitoftheresonantnetworkforthecasewithoutsnubber;(c)modi?edresonantnetworkforcasewithsnubberelements;(d)comparisonoftheresonanttrajectoriesforthecaseswithandwithoutsnubberelementsandtheirresultingvoltagepeaksVSR,pk,sbandVSR,pk,respectively.(Thein?uenceofthereverserecoverycurrentoftheMOSFETbodydiodesisnotshown.) theresonantnetworkchangesasshowninFig.6(c)andtheresonantfrequencybecomes ?? fres,snub=1/Lσn2tr(2Coss+Csnub)(6)whiletheresonantimpedance?? becomes Zres,snub=Lσn2tr/(2Coss+Csnub) (7) afterthevoltagevSRhasrisenabovetheleveloftheoutputvoltagVout.ThisisalsodepictedinFig.6(d)wherethesuddenchangeoftheresonantimpedanceleadstoadropinthevSR?Z·iplane.Themaximumvoltagespikecanthenbederivedasafunctionoftheoutputvoltagetobe Vn?? SR,pk,sb=VDCtr+(VDCntr?Vout)2+(Zres,snubISR)2.(8)ThesnubbercapacitorischosentohaveavalueofCSnub=15nFwhichlimitstheworstcasevoltagespikeatthelowestoutputvoltageofVout,min=40VtoVSR,peak,snub=92Vwithoutconsideringthein?uenceofthereverserecoverycurrent.ForthematerialoftheceramicsnubbercapacitorstheC0G(NP0)dielectricischosensinceitprovidesastablecapacitancevalueundervaryingtemperatureandvoltage.Inorderminimizethereverserecoverycurrentsofthediodes,theconductiontimeofthediodesintheSRMOSFETsiskepttoaminimum(around10ns)byadjustmentsofthetimingsofthegatesignals[13]. Master Controller VDC,tot,ref+-VDC,1VDC,1V??NVV+DC,2DC,iDC,totVi=1-mDC,NGu,1(s)u+grid-VDC,2ugridKmii+g,refgrid-+-VDC,N ModulationmG(a) i,1(s)iindexgridmV++DC,N--VoutGate signalsiPWM?outGi,3(s)iV+ref,cellDC,ref-G++u,2(s)iout,refSlave ControllersMaster Controller VDC,1??NVDC,2VVDC,refii=1DC,iout,ref Gi,2(s)Vout Vout,ref (b) VDC,NNFig.7:Controlimplementationofthemulti-celltelecomrecti?er:(a)totalDC-busvoltagecontrollerandinputcurrentcontroller;(b)outputcurrentcontrollerandDC-linkvoltagecontroller. Controlimplementation Oneofthemainchallengesregardingthecontrolofmulti-cellconvertersingeneralistheunbalanceoftheDC-link voltagesofthecell.Inordertoovercomethisproblemdifferentcontrolstrategieshavebeenproposed[14]–[18].ThebasicideabehindthoseconceptsistoperformvoltagebalancingcontroleitherbythecascadedH-bridgerecti?erortheisolatedDC-DCconverters.In[14]avoltagebalancecontrolispresentedwhichisbasedonthesingle-phasedq-controlfortherecti?er,andapowerbalancecontrolmethodtoregulatethepowertransferredthroughtheDC-DCconverterthatareconnectedinparallelattheiroutputs.ThisallowstoindividuallyadjustthepowertransferfromeachDC-linktotheoutputinordertobal-ancetheDC-linkvoltages.Incontrast,[15]presentsamethodtocontrolandbalancethevoltageoftheDC-linksbyoperatingtherecti?erstageswithamixtureoflowandhighfrequencyPWM.However,bothoftheaforementionedmethodsresultinrathercomplicatedcontrollerimplementationssincethevoltagebalancingrequiresadditionalcontrolloops.AsimplerwaytooperatetheISOPsystemispresentedin[16]whichusesacommon-duty-ratiocontrolmethodwhichreliesonthenaturalbalancingbehaviorofISOPmulti-cellconverters[17].However,thismethodisnotactivelybalancingtheDC-linkvoltages.Therefore,anymismatchbetweentheconverters, CCM3CCM2CCM1LCM2LCM2LgCCVDM3DM2CDM1gvFB,totCCM3CCM2CCM1filter stage 3filter stage 2filter stage 1Fig.8:Schematicoftheemployed3-stagecommon-modeanddifferential-modeEMI?lter. suchase.g.slightlydifferenttransformerterminalbehaviors,willleadtodifferentACvoltageripplesontheDC-linkcapacitorscausedbythepulsatingpowerofthemains.ThesedifferencesintheDC-linkvoltageswillgeneratecirculatingcurrentsattheparallelconnectedconverteroutputswhichde-creasestheef?ciencyofthesystem.Thus,thecontrolschemewhichisselectedfortheimplementationintheprototypehasatotaldc-linkvoltageregulatorontherecti?ersideinordertohaveaconstanttotaldc-linkvoltage(i.e.thesumofallDC-linkvoltages).Inaddition,eachcellpossessesindividualDC-linkvoltageandloadcurrentcontrolfortheisolatedDC-DCconverters[18].Fig.7showsthecontrolblockimplementationoftheentiresystem.Thecontrolloopscanbeimplementedasamaster-slavecontrolregimewherethesloweroutervoltagecontrolloopsareprocessedbythemastercellandthefasterinnercontrolloopslikethecurrentcontrollersarecomputedlocallyoneachcell.Thecommunicationbetweenthecellsisrealizedbytheserialperipheralinterface(SPI).EMIFilterDesign ForthedesignoftheEMI?lterthein?uenceofthedifferential-modeandthecommon-modenoisehavetobeconsidered.The?lterdesigncanbeperformedindividuallyforthecommon-modeandthedifferential-modenoiseiftherequiredattentuationforeachcaseiscalculatedwithamarginofaround16dBtothelimits,i.e.6dBfortheworstcaseadditionofthetwonoisesignalsand10dBtoaccountforcomponenttolerances. Inordertocalculatetherequiredattenuationforthedifferential-modenoise,the?rstharmonicthatfallsintotheEMIconstrainedspectrum(fEMI≥150kHz)isconsidered,sincetheamplitudeoftheharmonicspectrumofsquarewavevoltagedecreaseswith?20dBperfrequencydecade,whereasthe?lterattenuationincreaseswith?40·NsdBwithNsbeingthenumberof?lterstages.Forthecaseathand,the?rstharmonicintheconstrainedfrequencyrangeisattwicetheeffectiveswitchingfrequencyfsw,eff=120kHzoftheinter-leavedAC-DCstages,i.e.f?lt=240kHz.ThecompliancewithEMIstandardsisevaluatedbydeterminingthequasi-peakemissionlevelsoftheconverter.Thequasi-peakvoltageoftheharmonicatf?lt=240kHziscalculatedbyconsideringa9kHzbandaroundthatharmonicandbysynthesizingatimedomainsignalwhichisfedintothenon-linearquasi-peakdetectionnetwork[19]andresultsinaquasi-peaknoise voltageoftheconverteratf?lt=240kHzofV?lt,qp=17.2Vand/orarequiredattenuationof92.8dBincludingthemarginpreviouslymentioned.Followingthe?ltervolumeoptimiza-tionguidelinespresentedin[20]thenumberof?lterstagesforaminimumvolumeanditsassociatedvolumecanbefoundatn?lt=3asshowninFig.8.Themaximumvalueofthetotaldifferentialmodecapacitanceislimitedbythemaximumallowablereactivepowerconsumptionofthe?lter.Thelimitwassetsuchthatapowerfactorofcosφ=0.9canbereachedabove10%ofthenominalpower.ThisleadstototaldifferentialmodecapacitanceofCDM,tot=2μF,whichmeanseachdifferentialmodecapacitanceamountstoCDM=660nF.ThisleadstodifferentialmodeinductancesofLDM=18μHinordertoachievetherequiredattenuationincombinationwiththeboostinductorLg. Theprecisemodelingofthecommon-modenoiseischal-lengingsinceitrequirestheexactknowledgeofthestraycapacitancesofallelectricnodesintheconvertercellstotheground.Sincethisispracticallyimpossibletodetermineformulti-cellconvertersystems,anapproachaspresentedin[21]wasfollowedwhichdeducesanequivalentcircuitforthecommon-modenoise.Byapplyingaworst-caseapproximationandneglectingsmallcapacitancescomparedtolargerones,itcanbefoundthatduetothenatureoftheseriesconnectionoftheconverterinputsthemeasuredcommon-modevoltageatthelineimpedancestabilizationnetwork(LISN)dependsonwhichcelloftheseriesstackisswitching.So,forexampleeachtimethelowestcelloftheseriesstackswitches,alluppercellsarealsomovedinrespecttotheirpotentialtoground.Sincethecellsareoperatedinterleaved,thecommon-modevoltageresemblesastaircaselikevoltagewaveformwiththelevelsbeing vNCM(i)= cells?i N·VcellsDC(9)fori∈[1,Ncells]wherei=1meansthatthelowestcellofthestackisswitchedandi=Ncellsmeanstheuppermostcellisswitched.Basedonthatvoltagewaveformthequasi-peakvoltagespectrumcanbederivedbymeansofsimula-tionsandtherequiredcommon-mode?lterattenuationcanbedeterminedtobe78dB.Themaximumallowabletotalcommon-mode?ltercapacitanceislimitedbythemaximumtotalleakagecurrenttoearth(e.g.3.5mARMS)whichleadstoCCM,tot=36nFandthusthevalueforeachcommon-modecapacitorisselectedasCCM=4.7nF.Usually,thesmallestcommon-mode?ltervolumeisobtainedbyutilizingthemaximumallowableamountofcommon-mode?lterca-pacitance[22].Asaresult,thecommon-modeinductancescanbedeterminedtobeLCM=1.6mH.Intheprotoype,theleakageinductanceofthecommon-modechokesisutilizedasdifferential-mode?lterinductances. IV.CONCLUSION Anewapproachtowardsahighlyef?cientandverycompacttelecomreciti?ermodulebeyondthelimitsofstate-of-the-artsystemsispresented.Thedegreesoffreedominthedesignprocedureofamulti-celltelecompowersupplymoduleinISOPcon?gurationareoutlinedandtheoptimizationprocess isdescribedindetail.Theoptimizationresultsshowthataconverterdesignwithanef?ciencyofη=98%andapowerdensityofρ=2.2kW/dm3canbeachieved.TheresultsalsorevealanoptimumvalueofN=6forthenumberofconvertercellsandanoptimummaximumpermissibledropof20%theDC-linkvoltageduringthehold-uptime.Basedontheoptimizationresultsahardwaredemonstratorrealizationispresentedandspeci?cdesignaspectsareexplained.Firstmeasurementresultsverifytheoperationofthesystemandwillbesummarizedinfuturepublication. REFERENCES [1]NationalResourcesDefenseCounsil,“DataCenterEf?ciencyAssement -ScalingUpEnergyEf?ciencyAcrosstheDataCenterIndustry:EvaluatingKeyDriversandBarriers,”August2014. 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