Equalization and Clock and Data Recovery Techniques for 10-Gbps CMOS Serial-Link Receivers - 图文

IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.42,NO.9,SEPTEMBER20071999

EqualizationandClockandDataRecoveryTechniquesfor10-Gb/sCMOSSerial-LinkReceivers

SrikanthGondiandBehzadRazavi,Fellow,IEEE

Abstract—Twoequalizer?ltertopologiesandamergedequal-izer/CDRcircuitaredescribedthatoperateat10Gb/sin0.13-mCMOStechnology.Usingtechniquessuchasreversescaling,pas-sivepeakingnetworks,anddual-andtriple-loopadaptation,theprototypesadapttoFR4tracelengthsupto24inches.Theequal-izer/CDRcircuitretimesthedatawithabiterrorrateof1013whileconsuming133mWfroma1.6-Vsupply.

IndexTerms—Adaptiveequalization,analogequalization,broadbandreceivers,DFE,FFE,high-speedlinks,lossychannel,reversescaling.

withotherequalizationmethods[6]soastomitigatebotheffects.

SectionIIpresentsvariousgainpeakingmethodsthatareusedinSectionIIItodeveloptwoequalizer?ltertopologies.SectionIVdescribesanadaptiveequalizerarchitectureandSectionVthemergedequalizer/CDRcircuit.SectionVIsum-marizestheexperimentalresultsforthetwoprototypes.

II.GAINPEAKINGTECHNIQUES

A.GeneralConsiderations

CoppertracesdesignedastransmissionlinesonFR4sub-stratessufferfrombothskineffectanddielectricloss.Forex-ample,a30-intraceexhibitsalossofapproximately21dBat5GHzand34dBat10GHz(AppendixI).Theequalizer?ltermustthereforeprovideadequategainpeakingaround5GHzsoastoequalizethesignalspectrum.

Thedesignofgain-peakingcircuitsmustsatisfymanydif?cultrequirements:1)suf?cientboostathighfrequencies;2)matchingtheinverselosspro?leofthechannelwithreason-abletolerance;3)minimallow-frequencylosstominimizethenoiseaccumulationincascadedstagesandprovidesuf?cientswingsfortheCDR;4)well-behavedphaseresponsetoachievealowjitter;5)reasonablelinearitysothattheequalizertransferfunctionindeedactsastheinverseofthechannellosspro?le;

requirements;and6)smallinputcapacitancetosatisfythe

7)tunabilityoftheboosttoallowadaptation.

Inaddition,thechallengestypicallyencounteredinthedesignoflow-voltagebroadbandampli?ers–suchaslimitedbandwidthanddrivecapability–persisthereaswell.B.PeakingByComplexPolesorRealZeros

Theavailabilityofmonolithicinductorsmaysuggesttheuseofunderdampedcomplexpolestoprovidetherequiredboostathighfrequencies.Forexample,theshunt-peakingcircuitofFig.1(a)yieldsatransferfunctionoftheform

(1)

,,.Whileprovidingenoughboosttomatch

theinverseoftheFR4frequencyresponse,high-complexpolesintroducesubstantialphasedistortion.Asanexample,acascadeoftwosuchstagesisdesignedtoequalizea30-intrace[Fig.1(b)],yieldingtheequalizedeyeshowninFig.1(d).

Thisissuerestrictsrealizationstonon-feedbackstructurescontainingrealzerosandpolesorfeedbackstructureshavingwhere

I.INTRODUCTION

HEfrequency-dependentlossoftracesonFR4printedcir-cuitboards(PCBs)posesincreasinglymoredif?cultde-signchallengesasdataratesapproach10Gb/sandtracelengthsreachtensofinches.Preemphasisinthetransmittercanpartiallycompensateforthechannellossbutatthecostofdynamicrange.Forexample,the12dBpreemphasisin[1]requiresasupplyvoltageof2.5Vtoaccommodatethelargeampli?edcompo-nentswithoutsacri?cingthelow-frequencyswings.Thus,lowsupplyvoltagesandchannellossesashighas25dBdictatethatmostoftheequalizationbeperformedinthereceiver.Examplesincludeabipolarimplementationconsuming195mW[2]andaCMOSrealizationsufferingfromhighintersymbolinterference(ISI)andlackingautomaticadaptation[3].

Recentwork[1],[4],[5]hasincorporatednonlinear(e.g.,de-cision-feedback)equalizerssoastoaccommodatesharpnotchesinthechannelduetoimpedancediscontinuitiesandalsoavoidtheampli?cationofcrosstalkduetohigh-frequencypeaking.Thecomplexityandpowerdissipationofsuchrealizations(e.g.,210mWforthe6.25-Gb/s0.13-mCMOSreceiverin[5])arejusti?edforonlydemandingapplications.

Thispaperdescribesadaptiveequalizationandclockanddatarecovery(CDR)techniquessuitedto10-Gb/sbinaryreceivers.Theconceptsintroducedhereaddresstheproblemofhighlosses.Losscompensationisachievedbyusinglinearequalizationtechniquesthattendtoamplifycrosstalknoise.Ifcrosstalkandimpedancediscontinuitiesduetoconnectorsandviasalsobecomecritical,thesetechniquescanbecombined

ManuscriptreceivedJuly26,2006;revisedFebruary26,2007.ThisworkwassupportedbyKawasakiMicroelectronicsAmerica.FabricationsupportwasprovidedbyTaiwanSemiconductorManufacturingCompany.

S.GondiwaswiththeElectricalEngineeringDepartment,UniversityofCal-ifornia,LosAngeles,CA90095USA.HeisnowwithKawasakiMicroelec-tronics,SanJose,CA95131USA.

TheauthorsarewiththeElectricalEngineeringDepartment,UniversityofCalifornia,LosAngeles,CA90095USA(e-mail:razavi@icsl.ucla.edu).DigitalObjectIdenti?er10.1109/JSSC.2007.903076

T

0018-9200/$25.00?2007IEEE

2000IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.42,NO.9,SEPTEMBER2007

Fig.1.Complexpolepeakingcircuit.(a)Implementation.(b)Magnituderesponse.(c)Phaseresponse.(d)transientresponse.

Fig.2.RC-degenerateddifferentialpair.(a)Circuitimplementation.(b)Fre-quencyresponse:actualresponse(solidline);bodeapproximation(dashedline).

low-complexpoles.Ofcourse,inductorscanstillactasshunt-peakingelementstobroadenthebandwidthofequalizerstages.Anef?cientmethodofboostingbymeansofrealzerosiscapacitivedegeneration.Fig.2(a)showsade-generateddifferentialpairthatyieldsazeroat

andpolesatand

,withalow-frequencygain

.Fig.2(b)depictsof

thefrequencyresponse.Improvingthelinearityofthestage,degenerationnonethelesscreatesatrade-offbetweenthe

.Interestingly,low-frequencygainandtheboostfactor,

onecanwrite

concludingthattheproductofthegain,theboostfactor,andthe

ofthetechnology.1bandwidthofthestageislimitedbythe

Itisimportanttoappreciatetheimpactofthelimited(about75GHzin0.13-mCMOStechnology)onequaliza-tion.Forasmall-signalgainof2,anundegenerateddifferen-tialpairwithanoverdrivevoltageof300mVandfanoutofunityyieldsabandwidthoflessthan12.5GHz.Thedegener-atedstructuretradesthisgain-bandwidthproductfortheboostfactor,thelow-frequencygain,andthelinearrange.

Withtheperformanceenvelopeimposedby(2),acascadeofstagessuchasthecircuitofFig.2(a)failstoprovidetherequiredboostfactorwhileaccommodatingadatarateof10Gb/sandareasonablelow-frequencygain(e.g.,6dB–0dB).Asthenumberofstagesinthecascadeincreasestoachieveahigherboostfactor,theoverallbandwidthtendstodropunlessagreaterlow-frequencylossisallowedineachstage.Simulationsindicatethat,foratotalboostfactorof22dBat5GHzandanoverallbandwidthof5.5GHz,2threedegeneratedstageswithalow-frequencylossof6dBperstagearerequired.Suchahighlossresultsinasensitivitydegradationofabout3dB.C.PeakingByPassiveNetworks

Weproposetheuseofpassivehigh-passnetworkstopro-videboostatthefrontendofanequalizer,thusrelaxingthelinearityandgainpeakingofthesubsequentactivestagesandsavingpowerconsumption.Fig.3(a)depictsanexamplewherethezeroandpolefrequenciesarerespectivelygivenby

andandtheboostfactorbyifisneglected.Toavoiddegradingtheinput

Cincludestheinputcapacitanceofthenextstage.

2TheoverallbandwidthreferstothatoftheFR4tracealongwiththeequalizercircuit.

1Here,

(2)

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Fig.3.(a)Passivenetwork.(b)Proposedpassivenetworkwithseries-inductivepeaking.

Fig.4.Illustrationofthereversescalingtechnique.(a)Blockdiagram.(b)Single-endedcircuitrealization.

returnloss,,,andmustbechosenhighenough

.Also,sincetheinputcapacitance,,sothat

lowersthepolefrequencyto,were-.Forexample,if,quirethat

(foraboostof4.7dB),andfF,thenmustremainbelow20fF,restrictingthesizeofthetransistorsinthe?rstac-tivestage.

Theaboverestrictioncanbeeasedthroughtheuseofseries

providesadditionalinductivepeaking[Fig.3(b)].Here

peakingatfrequenciesabove5GHzevenforlargevaluesof

.Forexample,if,,fF,

fF,thenetworkyieldsaboostfactorof8dBandand

ofdBat10GHz.an

D.ReverseScaling

Withthetrade-offsdescribedabove,thepeakingcircuitspre-sentedthusfarprovideaboostofapproximately8dBat5GHz,dictatingtheuseofatleastthreepeakingstagesintheequalizer.Moreover,thecumulativelow-frequencylossrequirestwoad-ditionalgainstagestorestorethesignallevel.

Ifidenticalstagesarecascaded,theoverallsmall-signalbandwidthisgivenby[7]

(3)

denotesthebandwidthofasinglestageandiswhere

equalto2for?rst-orderstagesand4forsecond-orderstages.

,thenthesmall-signalbandwidthdropsbyaThus,if

factorof2.6for?vestages.Forexample,withthreepeakingandtwogainstages,thebandwidthoftheequalizerfallsbelow4GHzifnobandwidthenhancementtechniquesareemployed.Reversescaling[8]providesbandwidthimprovementinap-plicationswheretheinputimpedanceneednotbeveryhigh.Inthiswork,weproposetheconceptofreversescalingforequal-izerdesign[9].AsillustratedinFig.4,successivestagesarescaleddowninsizebyafactorofsuchthatthegainand

Fig.5.Transistor-levelsimulationsofa?ve-stageequalizerwith(a)noscaling,and(b)reversescaling.

boostcharacteristicsaremaintainedbutthetimeconstantattheoutputnodeofeachstageisreduced.Thetotalcapacitanceseen

canbeexpressedattheinterfacebetweenstagesand

,whereincludesthejunc-as

tionandoverlapcapacitancesattheoutputofthethstageand

theinputcapacitanceofthethstage.Inare-verse-scaleddesign[Fig.4(b)],thecorrespondingtimeconstant

isgivenby

(4)

revealingabandwidthimprovementresultingfromthesecondtermintheparentheses.Forexample,withfF,

fF,and,thebandwidthincreasesbyabout

33%.

,thevalueofAsevidentfromtherelationship

isdictatedprimarilybythreefactors:1)themaximumtoler-;2)theminimumacceptablevalueof(theablevalueof

inputcapacitanceoftheCDRcircuit);and3)theminimumac-ceptablenumberofstages.The?rstcomponentisdeterminedbytherequiredinputbandwidthand/orreturnloss.Iftheequal-izerpathdirectlydrivestheCDRcircuit,theminimumaccept-isgivenbythetotalinputcapacitanceoftheablevalueof

2002IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.42,NO.9,SEPTEMBER2007

Fig.6.Equalizer?lterIwithreversescaling.

phasedetector—aratherlargevalue.Thus,asimplegainstage

fF.Aspreferablyfollowstheequalizer.Inourdesign,

mentionedabove,theminimumnumberofstagesisdictatedbythetrade-offbetweentherequiredpeakingandthebandwidth.Forexample,a?ve-stagecascadenecessitatesabandwidthof14GHzateachnode,limitingthetotalinputcapacitanceto

of10dBat10GHztranslates450fF.Ontheotherhand,an

toatotalinputcapacitanceof213fF.AllowingforESDand

fF.3Also,fF.padcapacitance,weassume

.Thus,

Inthiswork,ascalingfactorof1.3ischosentoachieveanimprovementof22%inspeed.Fig.5showsthesimulatedout-putsoftheequalizerforscaledandunscaleddesigns.4Theeyeopeningincreasesbyapproximatelythesamefactor.5

NotethattheuseofmonolithicT-coils[10]cangreatlyin-creasethetolerableinputcapacitanceandhenceprovideaddi-tionalbandwidthimprovementwithreversescaling.

III.EQUALIZERFILTERDESIGN

Inthissection,thepeakingtechniquespresentedinSectionIIIareusedtodesignequalizer?lters.Thesedesignsalsoincorpo-rateadaptiveboostingsoastoallowdifferenttracelengths.A.EqualizerFilterI

ShowninFig.6,the?rstequalizer[9]interspersesthreepeakingstageswithtwogainstagestoprovideaboostfactorofabout22dBat5GHzwhileexhibitingalow-frequencylossoflessthan3dB.6Thedesignexploitsthereversescaling

3Forthesakeofsimplicity,thesecalculationsdonotincludetheuseofpassive

Fig.7.Tuningbehaviorof?ve-stagecascade.

peakingatthefrontend.

4ThedetailsofthiscircuitareshowninFig.6.

designsincorporateotherbroadbandtechniquesaswell(SectionIII).

6Thetwogainstagespartiallycompensatethelossofthepeakingstages,pro-vidinganoutputswingofapproximately1V.

5These

techniquedescribedinSectionIIbutwithslightvariationinthevalueoffromonestagetothenexttoallowoptimizationforhigh-frequencypeakingandlow-frequencyloss.

AsmentionedinSectionII,simpleresistively-loadeddiffer-entialpairscannotyieldtherequiredbandwidth.Thus,induc-tivepeakingandnegativeMillercapacitances[11]havebeenaddedtoimprovethespeedwithoutsacri?cingthevoltagehead-room.Tosavearea,onlythreeofthestagesincorporateinduc-tivepeaking.

Thepeakingstagesintheequalizerpathemployavariable

anddegenerationresistancealongwithMOSvaractors

toprovideawideboostrange.Asthecontrolvoltagerises,theon-resistanceoffallsandsodoesthecapacitanceofand,raisingthemagnitudeofthezero.Notethatthesimul-taneouschangeoftheresistanceandcapacitancegreatlysimpli-?estheadaptationloop(SectionIV).Fig.7illustratesthesim-ulatedtuningbehaviorofthecascadeasthecontrolvoltageissweptfrom0.1Vto1.1V.

AsindicatedinFig.6,thecascadeemployscapacitivecouplingbetweensomestagestoisolatecommon-mode

GONDIANDRAZAVI:EQUALIZATIONANDCLOCKANDDATARECOVERYTECHNIQUESFOR10-GB/SCMOSSERIAL-LINKRECEIVERS2003

Fig.8.Equalizer?lterIIarchitecture.

(CM)levels.Thismitigatesthevoltageheadroomissueand,moreimportantly,avoidsvariabilityintheCMlevelseenby-duetotheprecedingstage,thusmaintainingaconstant

0.25pFarerealizedusingtuningrange.Thecapacitors

multi-?ngerfringestructureshavingaparasiticcomponentofabout3%.TheCMlevelisgeneratedusingaresistivedivider.Thecornerfrequencyassociatedwiththiscapacitivecouplingisaround3MHz,resultinginnegligibledroopwithencodeddata.

B.EqualizerFilterII

InSectionII,thehigh-passpassivenetworkwasintroducedtoprovideapeakingpro?le.Theuseofthisnetworkintheequal-izer?ltercansavepowerconsumptionbyrelaxingthelinearityandgainpeakingrequirementsoftheactivestages.Fig.8showsthesecondequalizer?lterarchitecture[12],whichincorporatesbothpassivepeakingandreversescaling.Incontrasttothe?rstequalizer,thisdesignperformsboosttuningbyinterpolationbe-tweenapeakingpathandanall-passpath(setbycoef?cientsand),thusachievingawidertuningrangethanthatob-tainedbymeansofMOSvaractorsandvariableresistors.Also,aconstant(linear)degenerationresistanceinthedifferentialpairsyieldshigherlinearityandamoreaccurately-de?nedlow-fre-quencygain.

Theuseofinterpolationnonethelesspresentsadif?cultyfor

.Thedisparatede-intermediatelinelengths,i.e.,if

laysthroughthetwopathsresultinsubstantialISIaftertheircorrespondingoutputsaresummed.Realizedasadegenerateddifferentialpair,thephaseshiftblockintheall-passpathpar-tiallycorrectsthiserror.Thezeroofthisdifferentialpairispo-sitionedsuchthatthephaseresponseapproximatestheeffectiveresponseofthethreezerosinthepeakingpathforthefrequency

rangeof1–4GHz.Thepoleprovidesadditionaladjustmentoftheoverallphaseresponseintheall-passpath.7

Theuseofseriesinductivepeaking(with3-nHinductors)inthepassivebooststageallowswideinputtransistors(

m)inthe?rstdifferentialpairandhencereversescalingthroughthecascade.Thelow-frequencylossof7dBinthepassivenetworkdegradesthesensitivitytosomeextent.WithinductivepeakingandnegativeMillercapacitances,theband-widthofeachactivestagereaches18GHz.Thesummingstageincorporatesactivefeedback[10]toimprovethespeedwhileavoidinginductors.Sinceactivefeedbacktradeslow-frequencygainforbandwidth,ithasbeenappliedtoonlyonestage.

Thechoicebetweenthetwotypesofequalizersdescribedabovesomewhatdependsontheapplication.Theformerdoesnotincorporateapassivenetworkattheinput,providinggreatersensitivitybutconsumingahigherpower.Thelatterachievesahigherlinearityandwidertuningrange.

IV.ADAPTIVEEQUALIZER

Fig.9showsthe?rstadaptiveequalizerarchitecture[9],wheretheequalizer?lterisfollowedbyaslicer,andtwoloopscontroltheboostinthe?lterandtheswingintheslicer.The

,issensedatnodeAratherthanBbecauseequalizeddata,

theslicerincorporatessomepeakingtoimproveconvergenceoftheloops,therebyleadingtolargerjitteratBthanatAwhentheloopsreachsteadystate.Theneedfortheswingcontrolloopisjusti?edasfollows.

High-speedadaptiveequalizerssetthepeakinginthe?lterstagessoastocompensateforthehigh-frequencylossofthechannel.Tothisend,theequalizeroutputissharpenedbyaslicerandtheadaptationloopadjuststhepeakingaccordingtothe

indicatethata20Tlaymismatchproduceslessthan5psof

ISIjitterattheequalizeroutput.

7Simulations

2004IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.42,NO.9,SEPTEMBER2007

Fig.9.Proposedadaptiveequalizerarchitecture.

Fig.10.Spectrumbeforeandafterslicerwithswingmismatch.

Fig.11.Simulateddynamicsoftheswingandboostcontrolloops.

differencebetweenhigh-frequencycontentsofthedatabeforeandafterslicing[2],[13],[14].Notethattheslicergeneratesa

spectrum.Ifoperatingrandombinarysequencehavinga

optimally,theequalizermustdothesame.

Theadaptationrequiresthattheequalizernotslice(hard-limit)thedata.Otherwise,theinputandoutputofthe?nalslicercarrysimilarspectra,andtheerrorintheadaptationloopap-proacheszeroevenwithincompleteequalization.Thisissueinturnnecessitatesadequatelinearityintheequalizerpath,8leadingtotwoimportanteffects:1)theequalizeroutputswingis

8A

variable-gainampli?ercanprecedetheequalizertoensurelinearity.

afunctionofthetransmittedsignallevelandotherparametersinthesignalpath,whereasthesliceroutputisnot;and2)theequalizercircuitryisfundamentallydifferentfromthatintheslicer.Forexample,thedifferentialpairsintheequalizermaynotexperiencecompleteswitchingwhereasthoseintheslicermust.

Thus,asillustratedinFig.10,theadaptationmaysettlesuchthatthesignalsatAandBexhibitequalhighfrequencyener-gies(betweenand)whileAisverypoorlyequalized.Theabovedif?cultycanbealleviatedbyaddingaloopforlow-fre-quencyadaptationtomaintainequalswingsatAandB[15].In[15],however,theswingsintheequalizerpathareadjusted,po-tentiallylimitingthetuningrangeandinterferingwiththemainadaptationloop.TheapproachintroducedinthisworkisshowninFig.9,wheretheinputandoutputswingsoftheslicerarecomparedafterrecti?cation,andtheresultingerrorisusedtoadjustthesliceroutputswingratherthantheequalizeroutputswing.Theswingiscontrolledbyadjustingthetailcurrentofalimitingdifferentialpairintheslicer.Theslicerthereforegen-eratesswingsthatmatchtheequalizeroutputswings,allowingnearlycompleteoverlapofspectraatAandBafterequalization.Unlikeimplementationsthatprecedetherecti?erswithhigh-pass?lters(HPFs)[13]–[15],thisdesignemploysbandpass?l-]aroundters(BPFs)tomeasuretheenergyinaband[

5GHz.Thisisbecausethegainpeakingoccursinthevicinityofthisfrequencyandmustbecontrolledaccurately.

GONDIANDRAZAVI:EQUALIZATIONANDCLOCKANDDATARECOVERYTECHNIQUESFOR10-GB/SCMOSSERIAL-LINKRECEIVERS2005

Fig.12.Responseoftheadaptiveequalizertoa25%mismatchintheline.(a)Frequencyresponse.(b)Eyediagram.

Fig.13.Proposedmergedadaptiveequalizer/CDRarchitecture.

ThetwodynamicfeedbackloopsinthearchitectureofFig.9canpotentially“?ght”eachother,thusfailingtoconvergetoap-propriatesettings.Suchacon?ictisavoidedbychoosingsub-stantiallydifferenttimeconstantsforthetwoloops,namely,65nsforswingcontroland105nsforboostcontrol.Fig.11depictsthesimulateddynamicsofthetwoloopsastheysettletotheir?nalvaluesforworst-caseinitialconditions.(Thissim-ulationisperformedonthetransistor-levelimplementationofthecircuit.)

Apossiblepointofconcernisthesensitivityoftheproposedadaptiveequalizertomismatchesinthetransmissionline.Fig.12showstheresponseoftheadaptiveequalizerfora25%mismatchinthetransmissionlineat3.4GHz.Asexpected,thereisonlyagradualdegradationintheeyecomparedtothetransmissionlinewithminimalmismatch[Fig.5(b)].Thisdesignmaybefollowedbyamulti-tapdecision-feedbackequalizertoremovetheresultingISI.

V.MERGEDADAPTIVEEQUALIZER/CDRCIRCUIT

Inbroadbandreceivers,theequalizeristypicallyfollowedbyaCDRcircuit.ThetwofunctionscansimplybecascadedbutwerecognizethattheretimeddataproducedbytheCDRcircuitexhibitsthepropertiesofaslicedwaveform,obviatingtheneedforanexplicitslicer.Sinceslicerstypicallyconsumeseveralinductorsandconsiderablepowertoachievetherequiredbandwidthandgain,theconsolidationofequalizerandCDRcircuitscanyieldsavingsinareaandpowerdissipation.

Fig.14.Simulateddynamicsof(a)boostandswingcontrolsignals,and(b)thecontrolvoltageoftheVCOintheCDRloop.

Fig.15.CDRarchitecture.

Fig.16.VCOandbuffercircuit.

A.Architecture

ShowninFig.13isthearchitectureofthemergedequal-izer/CDRcircuit[12].Theretimeddata,

,providesbothlow-frequencyandhigh-frequencyinformationforadjustingtheboostandswingcontrols.Theswingadjustcircuitisrealizedasasingledifferentialpairwhilethe?lterandtheenergycompar-isonmechanismsaresimilartothoseinFigs.8and9,respec-tively.

ThearchitectureinFig.13entailsastart-upissue.Withhighintersymbolinterference(e.g.,fora24-intrace),iftheequalizerbeginswithminimumboost,theneachdataedgeappliedtotheCDRspansseveralbitperiods,thusprohibitingproperphase-lock.Thearchitecturecontainsthreefeedbackloopswhosetimeconstantsmustbechosencarefullytoensureconvergence.Fig.14showsthedynamicsofthethreeloopsastheyreachsteadystate.OnlywithproperphaselockcantheCDRprovidetheretimeddatatothefeedbackloop;hence,theCDRloopmustsettlebeforetheboostcontrolloop.Notethattheboostcontrolloopisinitiallyreset,providingmaximumpeakingandenablingtheCDRtolock.Also,evenwithoutphase-lock,theretimeddatafromtheCDRissuf?cientfor

2006Fig.17.XORandV/Icircuit.

Fig.18.Diephotographofadaptiveequalizer.

theswingcontrollooptoconverge.Thus,inthisdesign,theswingcontrolloopisthefastest,andtheboostcontrolloop,theslowest.

ThemergingoftheequalizerandtheCDRsavesabout19mWinpowerdissipation.Furthermore,itobviatesseveralinductorsthatwouldotherwisebenecessaryintheslicer.

Theoverallperformanceoftheequalizer/CDRcascadede-pendsontheresidualISI,additivenoise,andclockjitter.Itisthereforenecessarytoquantifythetrade-offsamongthesepa-rameterssothatareasonablejitterbudgetcanbeallocatedtoeachstage.Aframeworkfortheanalysisoftheseeffectsispro-posedinAppendixII.B.CDRCircuit

Thisworkemploysafull-rateCDRcircuitconsistingofanAlexanderphasedetector(PD)[16]andanvoltage-con-trolledoscillator(VCO)(Fig.15).Whileoperatingasabang-bangcircuitandexhibitingahighgain,theAlexanderPDpro-ducesnooutputintheabsenceofdatatransitions,thusleaving

undisturbed.ThehighgainofthePDobviatesachargepumpandpermitstheuseofasimplevoltage-to-current(/)convertertodrivetheloop?lter.NotethatnodesXandYneednotprovideahighbandwidthasonlytheiraveragevoltagesaresensedbythe/converter—animportantadvantageofthisre-alizationoverthoseusingchargepumps.

Thespeed,jitter,anddrivingcapabilityrequiredoftheoscil-latorpointtotheuseofan

implementation.Fig.16depictstheVCOanditsbuffer.Resistor

setsthecorecommon-modeIEEEJOURNALOFSOLID-STATECIRCUITS,VOL.42,NO.9,SEPTEMBER2007

voltagetoapproximately

,maximizingthecapacitancerangeoftheMOSvaractorsandhencethetuningrangeoftheos-cillator.ThebufferisolatesthecorefromthelargecapacitancesassociatedwiththePDdevicesandinterconnectswhilesup-pressingthedatatransitionsthatwouldotherwisecouplefromthePD?ip-?opstotheVCOcore.

TheVCOphasenoiseisdominatedbythemodulationofthevaractorcapacitancesduetothenoisecurrentof.Inthisde-sign,thesimulatedphasenoiseofthefree-runningVCOaspre-dictedbySpectreRFisapproximatelyequalto106dBc/Hzat1-MHzoffset.

TheXORgatesusedinthePDofFig.15mustexhibitsym-metrywithrespecttotheirtwoinputsandoperatewithalowsupplyvoltage.ShowninFig.17alongwiththe/converter,

theXORgateisamodi?edversionofthatin[17].Here

–formtheXORcoreandcopiestheaverageoutputcurrent

into

.Toallowlow-voltageoperation,thedrainvoltageofisraisedbyaboveitsgatevoltage,thussavingonethresholdintheheadroom.Thereferencevoltageisapproximatelyequaltothecommon-modelevelofAandB.The/convertercopiestheaverageoutputcurrentoftheXOR,providingnearlyrail-to-railswingsfortheoscillatorcon-trolline.SensingtheaveragevoltageproducedbytheXOR,the/converterremainsfreefromadeadzone.

VI.EXPERIMENTALRESULTS

ThissectionpresentsexperimentalresultsforthetwocircuitsdescribedinSectionsIVandV.Botharefabricatedin0.13-mCMOStechnology.A.AdaptiveEqualizerI

Fig.18showsaphotographofthedie,whichmeasures0.45mm0.36mm.Thecircuithasbeentestedonahigh-speedprobestationwhilesensing10-Gb/sdatathathastraveledonanFR4board.Thepseudorandombitsequencefollowsa21pattern.Fig.19showstheequalizerinputandoutputwaveformsat10Gb/sfor30-inand6-indifferentialtracesontheFR4boardwithoutanyexternalchangesinthebiasorothercircuitconditions.Inthissetup,the30-inFR4tracehasalossof21dBat5GHz.Theresultsshowthatthehigh-frequencyadaptationloopaccommodatesvaryinglossconditions.Tochecktheoperationofthelow-frequencyadaptationloop,thepatterngeneratoroutputswingwasvariedfrom520–700mVandsimilarresultswereobtained.Notethatthepatterngenerator

GONDIANDRAZAVI:EQUALIZATIONANDCLOCKANDDATARECOVERYTECHNIQUESFOR10-GB/SCMOSSERIAL-LINKRECEIVERS2007

Fig.19.Measuredresultsbeforeandafterequalizationat10Gb/sforFR4traces,(horizontalscale:20ps/div.):(a)beforeequalizationfor30-inFR4(verticalscale:100mV/div.),(b)afterequalizationfor30-inFR4(verticalscale:100mV/div.),(c)afterequalizationfor6-inFR4(verticalscale:100mV/div.).

theequalizer.Thecircuitconsumes133mW,ofwhich41mWisdissipatedintheequalizerand92mWintheCDR.

Fig.23(a)showstherecoveredclockspectrumfora24-inFR4at10Gb/s,displayingaphasenoiseof109dBc/Hzat1-MHzoffset.ThejitterhistograminFig.23(b)suggestsanrmsjitterof2.22ps.TheVCOprovidesatuningrangefrom8.9GHzto11.6GHz.

VII.CONCLUSION

ThehighlossoflongtracesonFR4boardscanbecompen-satedthroughtheuseofequalizationtechniquessuchaspas-sivepeakingnetworks,reversescaling,andcapacitivedegener-ation.Toadapttothelinelength,equalizersmustincorporatebothboostandswingcontrolwhileguaranteeingsmooth,con-?ict-freeconvergence.Finally,theequalizationandCDRfunc-tionscanbemergedtoeliminateslicers.Thisworkhasdemon-stratedtheseconceptsforadatarateof10Gb/sandtracelengthsof24inchesin0.13-mCMOStechnology.

APPENDIXILINEMODELING

Fig.24(a)plotsthelosspro?leofadifferential30-inmicrostriplineonanFR4board.Designedforadifferentialcharacteristicimpedanceof100,thetwotraceshaveawidthof6milandaspacingof12mil.(Thispro?leisobtainedbysimulationofthestructureinSONNET.)Theskineffectand

anddependencies,dielectriclossexhibitapproximately

respectively,andthelosspro?lecanberepresentedas

(5)

whereanddependonthetraceandboardproperties,re-spectively,anddenotesthetracelength.Thus,skineffectisdominantatlowerfrequenciesanddielectricloss,athigherfre-quencies.Inthisexample,skineffectlossbecomesequaltodi-electriclossatapproximately2.5GHz.Thestrongfrequencydependenceofthelossesinthemicrostripmakesitdif?culttousethestandardtransmissionlinemodel[Fig.24(b)],wherethe

andtheparallelconductanceremaincon-seriesresistance

stantwithfrequency.

Whilebroadbandmodelshavebeendevelopedforskineffect[18],anaccuratemodelisnotavailablefordielectricloss.Itis

Fig.20.Diephotographofmergedadaptiveequalizer/CDR.

itselfsuffersfromapeak-to-peakjitterof15ps.Thecircuit(excludingtheoutputbuffer)consumes25mWfroma1.2-Vsupply.

ThedoubletracevisibleinFig.19(c)fora6-inlineresultsfromapproximately2dBofrippleinthecascadefrequencyre-sponseoftheFR4boardandtheequalizer.Con?rmedbysim-ulations,thisripplepossiblyarisesfromtheimperfectmatchbetweenthepeakingpro?leprovidedbytheequalizerandtheinverseofthechannelfrequencyresponse.B.MergedEqualizer/CDRCircuit

Fig.20showsthephotographofthedie,whichmeasures0.94mm0.65mm.Themergedequalizer/CDRcircuituti-lizestheequalizer?lterarchitectureproposedinSectionIII.B.Thecircuithasbeentestedinachip-on-boardassemblywitha10-Gb/s21bitsequence.

Fig.21depictsthemeasuredinputandoutputeyediagramsforanFR4tracelengthof24incheshavingalossof18dBat5GHz.Forthissetup,theequalizer/CDRcircuitwastestedwithasupplyvoltageof1.6V.ThesensitivityofthemergedcircuitisplottedinFig.22,indicatingabiterrorrate(BER)oflessthan

foradifferentialtransmittedvoltageof640mV.Thissensitivitycanbeimprovedbyaddingasimplegainstageafter

2008IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.42,NO.9,SEPTEMBER2007

Fig.21.Measuredresultsbeforeandafterequalization/datarecoveryat10Gb/sforFR4traces(horizontalscale:20ps/div.):(a)beforeequalization/datarecoveryfor24-inFR4(horizontalscale:10ps/div.,verticalscale:75mV/div.),(b)afterequalization/datarecoveryfor24-inFR4(horizontalscale:20ps/div.,verticalscale:20mV/div.),(c)afterequalization/datarecoveryfor6-inFR4(horizontalscale:20ps/div.,verticalscale:20mV/div.).

Fig.22.BERsensitivitygraphforequalization/datarecoveryfor24-inFR4at10Gb/s.

Fig.24.(a)Losspro?leof30-inmicrostriponFR4board.(b)Narrowbandlossmodel.

Fig.23.Measuredresultsafterequalization/clockrecoveryfor24-inFR4at10Gb/s.(a)Recoveredclockspectrum.(b)Recoveredclockjitterhistogram(horizontalscale:5ps/div.).

possibletoextractthe-parametersofagivenlineacrossafre-quencybandusingavectornetworkanalyzerora?eldsimulatorandprovideittoatoolcapableofgeneratingaspicemodel(e.g.,SONNET).However,thisapproachprovideslittleintuitionand,moreimportantly,requiresentirelydifferentsetsofdatafordif-ferentlinelengths.Itisthereforedesirabletodevelopaphys-ical,scalablecircuitmodelthatincludesfrequency-dependentdielectriclossandeasilylendsitselftocircuitsimulations.Suchamodelmustalsorepresentthephasepro?leofthelinewithreasonableaccuracy.

ModelingbeginswithacorrectionofthecircuitinFig.24(b)toaccommodatefrequency-dependentskineffect.Illustratedin

andisadded[18],Fig.25(a),thesectionconsistingof

()modelingthelow-frequencyresistanceofwith

forcingthehigh-frequencycurrentthrough,thelineand

Fig.25.(a)Modelforvariableskineffect.(b)Proposedbroadbandmodelfor

a1-intrace.

thusraisingthelossathigherfrequencies.Additionalsectionscanbeaddedtore?nethemodel,butsimulationsindicatethatonebranchisadequateformodelingupto7GHz.

Inordertoincludethedielectricloss,theconstantparallelconductance,,inFig.24(b)isreplacedwithafrequency-de-pendentimpedancethatincursgreaterlossathigherfrequencies

GONDIANDRAZAVI:EQUALIZATIONANDCLOCKANDDATARECOVERYTECHNIQUESFOR10-GB/SCMOSSERIAL-LINKRECEIVERS2009

Fig.26.Pro?lesofactualmicrostrip(dashedlines)andscalablemodel(solidlines)fora30-intrace.(a)Magnitudepro?le.(b)Phasepro?le.

[Fig.25(b)].Theconductancetothesubstrate,therefore,in-creaseswithfrequency.Accuratemodelingofthedielectricloss

necessitatesatleasttwosuchsections:thelossinthe

–branchbecomesappreciableabove0.4GHzandthatinthe–branchabove20GHz,thusprovidinggoodaccuracyupto7GHz.Theabovemodelcansimplybecascadedtorepresentlongertraces.Fig.26comparesthelossandphasepro?lesfora30-intraceaspredictedby?eldsimulationsandthemodel,demonstratingareasonable?t.9

APPENDIXIIBERESTIMATION

TheBERofequalizer/CDRchainsisafunctionofadditivenoise,ISI,andCDRskewandjitter.Inthissection,weproposeamethodofestimatingtheBERbasedontheseparameters.Theobjectiveistodevelopanintuitiveunderstandingofthetradeoffsandhencearriveatareasonablecompromise.

ConsidertheeyediagramshowninFig.27(a),whereanddenotethepeakreceivedswingandthepeakeyeopening,respectively.We?rstexcludeclockjitter.TheISIduetolimitedbandwidthorincompleteequalizationleadstoa

roughlyuniformdistributionoftheamplitudebetween

and.Denotingthisdistributionbyandthatofadditive

Gaussiannoiseby

,weobservethatanerroroccursifnoisecausesalevelbetweenandtofallbelowzero

(oralevelbetween

andtoexceedzero).Thus,theprobabilityoferrorisgivenby

(6)

Also,

(7)(8)

and

(9)

9Simulations

indicatethatiftheproposedmodelisalteredtoincuronemore

dBoferror,theequalizeroutputsuffersfrom2.6dBofadditionalverticalclo-sureand0.03UIofadditionaljitter.

Fig.27.(a)Errorduetoadditivenoisebasedonthesamplingpointsintheeye.(b)BERasafunctionofclockskew.

where

denotesthermsvalueofnoise.Carryingouttheinte-grationin(6)andneglectinghigher-orderterms,wehave

(10)

Forexample,with

mV,mV,mV,10andsamplinginthemiddleoftheeye,weobtain.

Inthepresenceofclockskewandjitter,thesamplingpointde-viatesfromthemaximumeyeopening,rapidlyraisingtheBER.(SincetheISI-inducedjitterinthedatawaveformcontainspre-dominantlyhigh-frequencycomponents[19],theCDRcircuitfailstotrackthecorrespondingphasevariations.)FortoinFig.27(a),weapproximatetheeyeopeningas

andplotasafunctionofthe

clockskew[Fig.27(b)].Here,theabovevaluesof,,areusedand.

Wecannowincorporatetheeffectofclockjitterbyweighting

(10)accordingtothejitterdistribution,

,wheredenotestherandomdepartureofthesamplingpointfromthe

centeroftheeye.AsillustratedinFig.28(a),if

placesthesamplinginstantat,then

islowerandtheeffectofmorepronounced.Theerrorprobabilitydensityfunctionacrossthebitperiodcanthereforebeexpressedas

(11)

PlottedinFig.28(b)foraGaussianjitterdistributionhavinganrmsvalueofps,thisresultrevealsthaterrorsaremostlikelytooccurinthevicinityofps,wherethe

dramaticriseinstillcompensatesforthefallin

.Beyondthispointtheclockjitterbecomessoimprobablethaterrorsarelessandlesslikelytooccur.

Theframeworkdevelopedabovecanbeusedtoformulatethetrade-offsbetweenrequiredswings,additivenoise,ISI,and

tolerableclockjitter.Forexample,with

mVand,theplotsinFig.29canbegenerated,where

10The

additivenoiseisobtainedbyintegratingthenoiseattheoutputofthe

equalizerpathupto100GHz.

2010Fig.28.(a)Errorduetoadditivenoiseandclockskew.(b)Errorprobabilitydensityacrossthebitperiod.

Fig.29.BERcurvesfordifferentcombinationofreceivedswingsandclockjitter.

eachcurverepresentstheacceptablecombinationofand

thatyieldsagivenBER.Worthnotinghereisthesharpriseintherequiredswingastheclockjitterexceeds3ps.Also,theexperimentalresultinFig.23(b)indicatesanrmsjitterof2.2ps,whichfromFig.29,woulddictateaminimumswingof

520mVforBER

.Thisvalueisfairlyclosetothemeasuredresultof640mVinFig.22.

ACKNOWLEDGMENT

TheauthorswishtothankV.PathakandKawasakiMicro-electronicsAmericaforsupportofthiswork,Dr.J.Leeforde-signassistance,andTSMCforfabricationsupport.

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SrikanthGondireceivedtheB.E.(Hons.)degreeinelectricalandelectronicsengineeringfromBirlaIn-stituteofTechnologyandScience,Pilani,India,in1997,theM.Sc.degreeincomputerengineeringfromIowaStateUniversity,Ames,in2002,andthePh.D.degreeinelectricalengineeringfromUniversityofCalifornia,LosAngeles,in2006.

HewasaResearchAssistantatIowaStateUni-versityuntil1999,wherehefocusedonmixed-signalcircuitsforthegigabitethernettransceiverandthe1394home-networkingapplications.From2000to

2002,hewasaMixed-SignalDesignEngineeratTexasInstruments,Dallas,TX,workingonhigh-speedinterfacearchitecturesandcircuitsforwirelineapplica-tions,realizedinBiCMOStechnologies.HewasaGraduateStudentResearcherattheUniversityofCalifornia,LosAngeles,from2002to2006,wherehedevel-opedcircuitsandarchitecturesforserializer-deserializer(SerDes)applications.HeiscurrentlyaSeniorDesignEngineerintheR&DDivisionofKawasakiMicroelectronicsAmerica,workingonanalogfront-endsforbothwirelessandwirelineapplications.Hiscurrentresearchinterestsincludemixed-signalequal-izers,dataconverters,phase-lockingandclockrecoveryfordatacommunica-tions.

GONDIANDRAZAVI:EQUALIZATIONANDCLOCKANDDATARECOVERYTECHNIQUESFOR10-GB/SCMOSSERIAL-LINKRECEIVERS2011

BehzadRazavi(S’87–M’90–SM’00–F’03)re-ceivedtheB.S.E.E.degreefromSharifUniversityofTechnology,Tehran,Iran,in1985andtheM.S.E.E.andPh.D.E.E.degreesfromStanfordUniversity,Stanford,CA,in1988and1992,respectively.

HewaswithATTBellLaboratoriesandHewlett-PackardLaboratoriesuntil1996.Since1996,hehasbeenAssociateProfessorandsubsequentlyProfessorofelectricalengineeringattheUniversityofCali-fornia,LosAngeles.HewasanAdjunctProfessoratPrincetonUniversityfrom1992to1994,andat

StanfordUniversityin1995.HeistheauthorofPrinciplesofDataConversionSystemDesign(IEEEPress,1995),RFMicroelectronics(PrenticeHall,1998)(translatedtoChineseandJapanese),DesignofAnalogCMOSIntegratedCir-cuits(McGraw-Hill,2001)(translatedtoChineseandJapanese),DesignofInte-gratedCircuitsforOpticalCommunications(McGraw-Hill,2003),andFunda-mentalsofMicroelectronics(Wiley2006),andtheeditorofMonolithicPhase-LockedLoopsandClockRecoveryCircuits(IEEEPress,1996)andPhase-LockinginHigh-PerformanceSystems(IEEEPress,2003).Hiscurrentresearch

includeswirelesstransceivers,frequencysynthesizers,phase-lockingandclockrecoveryforhigh-speeddatacommunications,anddataconverters.

Prof.RazavireceivedtheBeatriceWinnerAwardforEditorialExcellenceatthe1994ISSCC,thebestpaperawardatthe1994EuropeanSolid-StateCircuitsConference,thebestpanelawardatthe1995and1997ISSCC,theTRWInno-vativeTeachingAwardin1997,andthebestpaperawardattheIEEECustomIntegratedCircuitsConferencein1998.Hewastheco-recipientofboththeJackKilbyOutstandingStudentPaperAwardandtheBeatriceWinnerAwardforEd-itorialExcellenceatthe2001ISSCC.Hewasrecognizedasoneofthetop10authorsinthe50-yearhistoryofISSCC.HereceivedtheLockheedMartinEx-cellenceinTeachingAwardin2006andtheUCLAFacultySenateTeachingAwardin2007.HeservedontheTechnicalProgramCommitteesoftheInter-nationalSolid-StateCircuitsConference(ISSCC)from1993to2002andVLSICircuitsSymposiumfrom1998to2002.HehasalsoservedasGuestEditorandAssociateEditoroftheIEEEJOURNALOFSOLID-STATECIRCUITS,IEEETRANSACTIONSONCIRCUITSANDSYSTEMS,andInternationalJournalofHighSpeedElectronics.HeisanIEEEDistinguishedLecturerandaFellowofIEEE.

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