AT45D081中文资料

AT45D08118-Megabit 5-volt Only Serial DataFlash ?AT45D081Features

?Single 4.5V - 5.5V Supply

?Serial Interface Architecture

?Page Program Operation

–Single Cycle Reprogram (Erase and Program)

–4096 Pages (264 Bytes/Page) Main Memory

?Two 264-Byte Data Buffers – Allows Receiving of Data while Reprogramming of

Non-Volatile Memory

?Internal Program and Control Timer

?Fast Page Program Time – 7 ms Typical

?80 µs Typical Page to Buffer Transfer Time

?Low Power Dissipation

–15 mA Active Read Current Typical

–10 µA CMOS Standby Current Typical

?10 MHz Max Clock Frequency

?Hardware Data Protection Feature

?Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3

?CMOS and TTL Compatible Inputs and Outputs

?Commercial and Industrial Temperature Ranges

Description

The AT45D081 is a 5-volt only, serial interface Flash memory suitable for in-system reprogramming. Its 8,650,752 bits of memory are organized as 4096 pages of 264-bytes each. In addition to the main memory, the AT45D081 also contains two data buffers of 264-bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses a serial interface to sequentially access its data. The simple serial interface facil-itates hardware layout, increases system reliability, minimizes switching noise, and 0871A-A–6/97

Pin Configurations Pin Name Function

CS Chip Select

SCK Serial Clock

SI Serial Input

SO Serial Output

WP Hardware Page Write

Protect Pin

RESET Chip Reset RDY/BUSY Ready/Busy (continued)TSOP Top View Type 1

1234567891011121314151632313029282726252423222120191817RDY/BUSY RESET WP NC NC NC VCC GND NC NC NC NC CS SCK SI SO NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC NC

NC

NC

NC SOIC 12345678910111213142827262524232221201918171615GND NC NC CS SCK SI SO NC NC NC NC NC NC NC VCC NC NC WP RESET RDY/BUSY NC NC NC NC NC

NC NC NC 元器件交易网

AT45D081

2

Device Operation

The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Tables 1 and 2. A valid instruc-tion starts with the falling edge of CS followed by the appro-priate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI (serial input) pin. All instructions, addresses, and data are transferred with the most significant bit (MSB) first.

Read

By specifying the appropriate opcode, data can be read from the main memory or from either one of the two data buffers.

MAIN MEMORY PAGE READ: A main memory read allows the user to read data directly from any one of the 4096pages in the main memory, bypassing both of the data buff-ers and leaving the contents of the buffers unchanged. To start a page read, the 8-bit opcode, 52H, is followed by 24

address bits and 32 don’t care bits. In the AT45D081, the first three address bits are reserved for larger density devices (see Notes on page 7), the next 12 address bits (PA11-PA0) specify the page address, and the next nine address bits (BA8-BA0) specify the starting byte address within the page. The 32 don’t care bits which follow the 24address bits are sent to initialize the read operation. Fol-lowing the 32 don’t care bits, additional pulses on SCK result in serial data being output on the SO (serial output)pin. The CS pin must remain low during the loading of the opcode, the address bits, and the reading of data. When the end of a page in main memory is reached during a main memory page read, the device will continue reading at the beginning of the same page. A low to high transition on the CS pin will terminate the read operation and tri-state the SO pin.

BUFFER READ: Data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. An opcode of 54H is used to read data from buffer 1, and an opcode of 56H is used to read data from

Block Diagram

FLASH MEMORY ARRAY

PAGE (264 BYTES)

BUFFER 2 (264 BYTES)

BUFFER 1 (264 BYTES)I/O INTERFACE

SCK CS RESET

V CC GND RDY/BUSY

WP

SO

SI reduces package size and active pin count. The device is optimized for use in many commercial and industrial appli-cations where high density, low pin count, low voltage, and low power are essential. Typical applications for the DataFlash are digital voice storage, image storage, and data storage. The device operates at clock frequencies up to 10 Mhz with a typical active read current consumption of 15m A.

To allow for simple in-system reprogrammability, the AT45D081 does not require high input voltages for pro-

gramming. The device operates from a single power sup-ply, 4.5V to 5.5V, for both the program and read opera-tions. The AT45D081 is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).

All programming cycles are self-timed, and no separate erase cycle is required before programming.

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buffer 2. To perform a buffer read, the eight bits of the opcode must be followed by 15 don’t care bits, nine address bits, and eight don't care bits. Since the buffer size is 264-bytes, nine address bits (BFA8-BFA0) are required to specify the first byte of data to be read from the buffer.The CS pin must remain low during the loading of the opcode, the address bits, the don’t care bits, and the read-ing of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low to high transition on the CS pin will terminate the read operation and tri-state the SO pin.

MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred from the main memory to either buffer 1 or buffer 2. An 8-bit opcode, 53H for buffer 1 and 55H for buffer 2, is followed by the three reserved bits, 12address bits (PA11-PA0) which specify the page in main memory that is to be transferred, and nine don’t care bits.The CS pin must be low while toggling the SCK pin to load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the transfer of a page of data (t XFR ), the status register can be read to determine whether the transfer has been completed or not.

MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can be compared to the data in buffer 1 or buffer 2. An 8-bit opcode, 60H for buffer 1 and 61H for buffer 2, is followed by 24 address bits consisting of the three reserved bits, 12 address bits (PA11-PA0) which specify the page in the main memory that is to be com-pared to the buffer, and nine don't care bits. The loading of the opcode and the address bits is the same as described previously. The CS pin must be low while toggling the SCK pin to load the opcode, the address bits, and the don't care bits from the SI pin. On the low to high transition of the CS pin, the 264 bytes in the selected main memory page will be compared with the 264 bytes in buffer 1 or buffer 2. Dur-ing this time (t XFR ), the status register will indicate that the part is busy. On completion of the compare operation, bit 6of the status register is updated with the result of the com-pare.

Program

BUFFER WRITE: Data can be shifted in from the SI pin into either buffer 1 or buffer 2. To load data into either buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2,is followed by 15 don't care bits and nine address bits (BFA8-BFA0). The nine address bits specify the first byte in the buffer to be written. The data is entered following the address bits. If the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer.Data will continue to be loaded into the buffer until a low to high transition is detected on the CS pin.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT -IN ERASE: Data written into either buffer 1 or buffer 2 can be programmed into the main memory. An 8-bit opcode, 83H for buffer 1 or 86H for buffer 2, is followed by the three reserved bits, 12 address bits (PA11-PA0) that specify the page in the main memory to be written, and nine additional don't care bits. When a low to high transition occurs on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both the erase and the programming of the page are internally self timed and should take place in a maxi-mum time of t EP . During this time, the status register will indicate that the part is busy.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH-OUT BUILT-IN ERASE: A previously erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. An 8-bit opcode, 88H for buffer 1or 89H for buffer 2, is followed by the three reserved bits,12 address bits (PA11-PA0) that specify the page in the main memory to be written, and nine additional don’t care bits. When a low to high transition occurs on the CS pin, the part will program the data stored in the buffer into the spec-ified page in the main memory. It is necessary that the page in main memory that is being programmed has been previously programmed to all 1s (erased state). The pro-gramming of the page is internally self timed and should take place in a maximum time of t P . During this time, the status register will indicate that the part is busy.

MAIN MEMORY PAGE PROGRAM: This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-In Erase operations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and then pro-grammed into a specified page in the main memory. An 8-bit opcode, 82H for buffer 1 or 85H for buffer 2, is followed by the three reserved bits and 21 address bits. The 12 most significant address bits (PA11-PA0) select the page in the main memory where data is to be written, and the next nine address bits (BFA8-BFA0) select the first byte in the buffer to be written. After all address bits are shifted in, the part will take data from the SI pin and store it in one of the data buffers. If the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. When there is a low to high transition on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both the erase and the program-ming of the page are internally self timed and should take place in a maximum of time t EP . During this time, the status register will indicate that the part is busy.

AUTO PAGE REWRITE: This mode is only needed if multi-ple bytes within a page or multiple pages of data are modi-fied in a random fashion. This mode is a combination of two operations: Main Memory Page to Buffer Transfer and

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Buffer to Main Memory Page Program with Built-In Erase.A page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1or buffer 2) is programmed back into its original page of main memory. An 8-bit opcode, 58H for buffer 1 or 59H for buffer 2, is followed by the three reserved bits, 12 address bits (PA11-PA0) that specify the page in main memory to be rewritten, and nine additional don't care bits. When a low to high transition occurs on the CS pin, the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page of main memory. The operation is internally self-timed and should take place in a maximum time of t EP . During this time, the status register will indicate that the part is busy.If the main memory is programmed or reprogrammed sequentially page by page, then the programming algo-rithm shown in Figure 1 is recommended. Otherwise, if multiple bytes in a page or several pages are programmed randomly in the main memory, then the programming algo-rithm shown in Figure 2 is recommended.

STATUS REGISTER: The status register can be used to determine the device’s ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or the device density. To read the status register, an opcode of 57H must be loaded into the device. After the last bit of the opcode is shifted in, the eight bits of the status register,starting with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. The five most-signifi-cant bits of the status register will contain device informa-tion, while the remaining three least-significant bits are reserved for future use and will have undefined values.After bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as CS remains low and SCK is being toggled) starting again with bit 7. The data in the status register is constantly updated, so each repeating sequence will output new data.

Ready/busy status is indicated using bit 7 of the status reg-ister. If bit 7 is a 1, then the device is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy state. The user can continuously poll bit 7 of the status register by stopping SCK once bit 7 has been output.The status of bit 7 will continue to be output on the SO pin,and once the device is no longer busy, the state of SO will change from 0 to 1. There are six operations which can cause the device to be in a busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare,Buffer to Main Memory Page Program with Built-In Erase,Buffer to Main Memory Page Program without Built-In

Erase, Main Memory Page Program, and Auto Page Rewrite.

The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer.

The device density is indicated using bits 5, 4, and 3 of the status register. For the AT45D081, the three bits are 1, 0,and 0. The decimal value of these three binary bits does not equate to the device density; the three bits represent a combinational code relating to differing densities of Serial DataFlash devices, allowing a total of eight different density configurations.

Read/Program Mode Summary

The modes listed above can be separated into two groups — modes which make use of the flash memory array (Group A) and modes which do not make use of the flash memory array (Group B).Group A modes consist of:1.Main memory page read

2.Main memory page to buffer 1 (or 2) transfer

3.Main memory page to buffer 1 (or 2) compare

4.Buffer 1 (or 2) to main memory page program with

built-in erase

5.Buffer 1 (or 2) to main memory page program with-out built-in erase

6.Main memory page program

7.Auto page rewrite

Group B modes consist of:1.Buffer 1 (or 2) read 2.Buffer 1 (or 2) write 3.Status read

If a Group A mode is in progress (not fully completed) then another mode in Group A should not be started. However,during this time in which a Group A mode is in progress,modes in Group B can be started.

This gives the Serial DataFlash the ability to virtually accommodate a continuous data stream. While data is being programmed into main memory from buffer 1, data can be loaded into buffer 2 (or vice versa). See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details.

Status Register Format

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0RDY/BUSY

COMP

1

X

X

X

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HARDWARE PAGE WRITE PROTECT: If the WP pin is held low, the first 256 pages of the main memory cannot be reprogrammed. The only way to reprogram the first 256pages is to first drive the protect pin high and then use the program commands previously mentioned.

RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level.

The device also incorporates an internal power-on reset cir-cuit; therefore, there are no restrictions on the RESET pin during power-on sequences.

READY/BUSY: This open drain output pin will be driven low when the device is busy in an internally self-timed oper-ation. This pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during program-ming operations, compare operations, and during page-to-buffer transfers.

The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed.

Absolute Maximum Ratings*

Temperature Under Bias ......................-55°C to +125°C *NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Storage Temperature............................-65°C to +150°C All Input Voltages (including NC Pins)

with Respect to Ground.........................-0.6V to +6.25V All Output Voltages

with Respect to Ground...................-0.6V to V CC + 0.6V

DC and AC Operating Range

Note:

1.After power is applied and V CC is at the minimum specified data sheet value, the system should wait 20 ms before an oper-ational mode is started.

AT45D081

Operating Temperature (Case)Com.0°C to 70°C Ind.

-40°C to 85°C V CC Power Supply (1)

4.5V to

5.5V

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AC Characteristics

Symbol Parameter Min

Typ

Max Units f SCK SCK Frequency 10

MHz t CS Minimum CS High Time 250ns t CSS CS Setup Time 250ns t CSH CS Hold Time 250ns t WH SCK High Time 40ns t WL SCK Low Time 40ns t SU Data In Setup Time 10ns t H Data In Hold Time 25ns t HO Output Hold Time 0

ns t DIS Output Disable Time 75ns t V Output Valid

80ns t XFR Page to Buffer Transfer/Compare Time 80150µs t EP Page Erase and Programming Time 1020ms t P

Page Programming Time

7

14

ms

DC Characteristics

Symbol Parameter Condition

Min Typ Max Units I SB Standby Current

CS, RESET, WP = V IH , all inputs at CMOS levels

1020µA I CC1Active Current, Read Operation

f = 10 MHz; I OUT = 0 mA; V CC = 5.5V

1525mA I CC2Active Current, Program/Erase Operation 25

50mA I LI Input Load Current V IN = 0V to V CC 10µA I LO Output Leakage Current V I/O = 0V to V CC 10µA V IL Input Low Voltage 0.8

V V IH Input High Voltage 2.0

V V OL Output Low Voltage I OL = 2.1 mA 0.45

V V OH1Output High Voltage I OH = -400 µA

2.4V V OH2

Output High Voltage

I OH = -100 µA; V CC = 4.5V

4.2V

Input Test Waveforms and Measurement Levels

t R , t F < 20 ns (10% to 90%)

AC DRIVING LEVELS

AC

MEASUREMENT LEVEL

0.45V

2.00.8

2.4V

Output Test Load

DEVICE UNDER TEST

30 pF

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AT45D081

7AC Waveforms

Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low when CS makes a high-

to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. Both wavforms show valid timing diagrams. The setup and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal.Waveform 1 shows timing that is also compatible with SPI

Mode 0, and Waveform 2 shows timing that is compatible with SPI Mode 3.

Waveform 1 – Inactive Clock Polarity Low CS

SCK

SI SO tCSS VALID IN

tH

tSU tWH tWL tCSH

tCS

tV HIGH IMPEDANCE VALID OUT tHO tDIS

HIGH IMPEDANCE

Waveform 2 – Inactive Clock Polarity High CS

SCK

SI SO tCSS VALID IN

tH

tSU tWL tWH tCSH

tCS

tV HIGH Z VALID OUT tHO tDIS

HIGH IMPEDANCE

Command Sequence for Read/Write Operations (Except Status Register Read)

Notes: 1.“r” designates bits reserved for larger densities.

2.It is recommended that “r” be a logical “0” for densities of 8M bit or smaller.

3.For densities larger than 8M bit, the “r” bits become the most significant Page Address bit for the appropriate density.

SI CMD 8 bits 8 bits 8 bits

MSB Reserved for larger densities Page Address (PA11-PA0)Byte/Buffer Address

(BA8-BA0/BFA8-BFA0)

LSB

r r r X X X X X X X X X X X X X X X X X X X X X 元器件交易网

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Main Memory Page Program through Buffers

SI

CMD

n

n+1

Last Byte

· Completes writing into selected buffer · Starts self-timed erase/program operation

CS r r r, PA11-7

PA6-0, BFA8

BFA7-0

Buffer Write

SI

CMD

X

X···X, BFA8

BFA7-0

n

n+1

Last Byte

· Completes writing into selected buffer

CS Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)

SI

CMD

PA6-0, X

CS Starts self-timed erase/program operation

r r r, PA11-7

Each transition represents

8 bits and 8 clock cycles

Write Operations

The following block diagram and waveforms illustrate the various write sequences available.

FLASH MEMORY ARRAY

PAGE (264 BYTES)

BUFFER 2 (264 BYTES)

BUFFER 1 (264 BYTES)

I/O INTERFACE

SI

BUFFER 1 TO MAIN MEMORY PAGE PROGRAM

MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 2

BUFFER 2 TO MAIN MEMORY PAGE PROGRAM

MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 1

BUFFER 1

WRITE

BUFFER 2WRITE

n = 1st byte written n+1 = 2nd byte written

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Read Operations

The following block diagram and waveforms illustrate the various read sequences available.

FLASH MEMORY ARRAY

PAGE (264 BYTES)

BUFFER 2 (264 BYTES)

BUFFER 1 (264 BYTES)

I/O INTERFACE

MAIN MEMORY

PAGE TO BUFFER 1

MAIN MEMORY PAGE TO BUFFER 2

MAIN MEMORY PAGE READ

BUFFER 1

READ

BUFFER 2READ

SO

Main Memory Page Read

SI CMD

PA6-0, BA8

BA7-0

X

X

X

X

CS n

n+1

SO

r r r, PA11-7

Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)

SI CMD

PA6-0, X

X

Starts reading page data into buffer

CS SO

r r r, PA11-7

Buffer Read

SI CMD

X

X···X, BFA8

BFA7-0

CS n

n+1

SO

X

Each transition represents 8 bits and 8 clock cycles

n = 1st byte read n+1 = 2nd byte read

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Detailed Bit-Level Read Timing – Inactive Clock Parity Low

Main Memory Page Read

Buffer Read

Status Register Read

SI

1

1

X

X

X

CS

SO

SCK

123456061626364656667

X

X

HIGH-IMPEDANCE

D 7D 6

D 5

DATA OUT

COMMAND OPCODE

MSB

tSU

tV

SI

1

1

X

X

X

CS

SO

SCK

123453637383940414243

X

X

HIGH-IMPEDANCE

D 7D 6

D 5

DATA OUT

COMMAND OPCODE

MSB

tSU

tV

SI

1

1

1

1

1

CS

SO

SCK

123457891011121617

HIGH-IMPEDANCE

D 7D 6

D 5

STATUS REGISTER OUTPUT

COMMAND OPCODE

MSB

tSU

tV

6D 1

D 0D 7LSB

MSB

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AT45D081

11Detailed Bit-Level Read Timing – Inactive Clock Polarity High Main Memory Page Read

Buffer Read

Status Register Read SI 01010X X X CS

SO SCK 1234561626364656667X X

HIGH-IMPEDANCE D 7D 6D 5DATA OUT

COMMAND OPCODE

MSB

tSU

tV

D 4

68SI 01010X X X CS

SO SCK 1234537383940414243X X

HIGH-IMPEDANCE D 7D 6D 5DATA OUT

COMMAND OPCODE

MSB

tSU

tV

D 4

44SI 01010111

CS

SO SCK 123457891011121718

HIGH-IMPEDANCE D 7D 6D 5STATUS REGISTER OUTPUT

COMMAND OPCODE

MSB tSU

tV 6D 4D 0D 7LSB MSB

D 6

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AT45D081 12Table 1

Main Memory Page Read Buffer 1

Read

Buffer 2

Read

Main Memory

Page to Buffer 1

Transfer

Main Memory

Page to Buffer 2

Transfer

Main Memory

Page to Buffer 1

Compare

Main Memory

Page to Buffer 2

Compare

Buffer 1

Write

Buffer 2

Write

Opcode

52H54H56H53H55H60H61H84H87H 000000011 111111100 000001100 111110000 000000000 011010011 101100001 000110101 r X X r r r r X X r X X r r r r X X r X X r r r r X X PA11X X PA11PA11P A11P A11X X PA10X X PA10PA10P A10P A10X X P A9X X P A9P A9PA9PA9X X P A8X X P A8P A8PA8PA8X X P A7X X P A7P A7PA7PA7X X P A6X X P A6P A6PA6PA6X X P A5X X P A5P A5PA5PA5X X P A4X X P A4P A4PA4PA4X X P A3X X P A3P A3PA3PA3X X P A2X X P A2P A2PA2PA2X X P A1X X P A1P A1PA1PA1X X P A0X X P A0P A0PA0PA0X X BA8BFA8BFA8X X X X BFA8BFA8 BA7BFA7BFA7X X X X BFA7BFA7 BA6BFA6BFA6X X X X BFA6BFA6 BA5BFA5BFA5X X X X BFA5BFA5 BA4BFA4BFA4X X X X BFA4BFA4 BA3BFA3BFA3X X X X BFA3BFA3 BA2BFA2BFA2X X X X BFA2BFA2 BA1BFA1BFA1X X X X BFA1BFA1 BA0BFA0BFA0X X X X BFA0BFA0 X X X

X X X

X X X

X X X

X X X

X X X

X X X

X X X

?

?

?

X (64th bit)

X (Don’t Care) r (reserved bits)

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Table 2

X (Don’t Care)r (reserved bits)

Buffer 1 to Main Memory Page Program with Built-In Erase Buffer 2 to Main Memory Page Program with Built-In Erase

Buffer 1 to Main Memory Page Program without Built-In Erase Buffer 2 to Main Memory Page Program without Built-In Erase

Main Memory Page Program Through Buffer 1Main Memory Page Program Through Buffer 2

Auto Page Rewrite Through Buffer 1Auto Page Rewrite Through Buffer 2

Status Register

Opcode

83H 86H 88H 89H 82H 85H 58H 59H 57H 111111000000000111000000000000000111001100110010001001110010001100101011

r r r r r r r r r r r r r r r r r r r r r r r r P A11P A11P A11PA11PA11PA11PA11P A11P A10P A10P A10PA10PA10PA10PA10P A10PA9PA9P A9P A9P A9P A9P A9PA9PA8PA8P A8P A8P A8P A8P A8PA8PA7PA7P A7P A7P A7P A7P A7PA7PA6PA6P A6P A6P A6P A6P A6PA6PA5PA5P A5P A5P A5P A5P A5PA5PA4PA4P A4P A4P A4P A4P A4PA4PA3PA3P A3P A3P A3P A3P A3PA3PA2PA2P A2P A2P A2P A2P A2PA2PA1PA1P A1P A1P A1P A1P A1PA1PA0PA0P A0P A0P A0P A0P A0PA0X X X X BA8BA8X X X X X X BA7BA7X X X X X X BA6BA6X X X X X X BA5BA5X X X X X X BA4BA4X X X X X X BA3BA3X X X X X X BA2BA2X X X X X X BA1BA1X X X

X

X

X

BA0

BA0

X

X

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AT45D08114Algorithm for Programming or Reprogramming of the Entire Array Sequentially START MAIN MEMORY PAGE PROGRAM (82H, 85H)END provide address and data BUFFER WRITE (84H, 87H)BUFFER to MAIN MEMORY PAGE PROGRAM (83H, 86H)Figure 1Notes: 1.

This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-page.2.

A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation.3.

The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array.元器件交易网

AT45D081

15Algorithm for Randomly Modifying Data START

MAIN MEMORY PAGE

to BUFFER TRANSFER

(53H, 55H)INCREMENT PAGE ADDRESS POINTER

(2)Auto Page Rewrite

(2)

(58H, 59H)END

provide address of

page to modify

If planning to modify multiple bytes currently stored within a page of the Flash array

MAIN MEMORY PAGE PROGRAM

(82H, 85H)

BUFFER WRITE

(84H, 87H)

BUFFER to MAIN

MEMORY PAGE PROGRAM

(83H, 86H)

Figure 2

Notes: 1.

T o preserve data integrity, each page of the DataFlash memory array must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations.2.

A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite com-mand must use the address specified by the Page Address Pointer.3.Other algorithms can be used to rewrite portions of the Flash array. Low power applications may choose to wait until

10,000 cumulative page erase/program operations have accumulated before rewriting all pages of the Flash array. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details.

元器件交易网

AT45D08116Ordering Information f SCK

(MHz)

I CC (mA)Ordering Code Package Operation Range Active Standby 10

250.02AT45D081-RC 28R Commercial (0°C to 70°C)AT45D081-TC 32T 10250.02AT45D081-RI

28R Industrial (-40°C to 85°C)

AT45D081-TI 32T Package Type

28R

28-Lead, 0.330” Wide, Plastic Gull-Wing Small Outline Package (SOIC)32T

32-Lead, Plastic Thin Small Outline Package (TSOP)元器件交易网

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